CDP1854ACD3 [INTERSIL]
High Reliability CMOS Programmable Universal Asynchronous Receiver/Transmitter (UART); 高可靠性的CMOS可编程通用异步接收器/发送器（ UART ）
| 型号： | CDP1854ACD3 |
| 厂家： | 
Intersil |
| 描述： | High Reliability CMOS Programmable Universal Asynchronous Receiver/Transmitter (UART) |
| 文件： | 总12页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
CDP1854A/3,
CDP1854AC/3
High Reliability CMOS Programmable Universal
Asynchronous Receiver/Transmitter (UART)
March 1997
Features
Description
• Two Operating Modes
The CDP1854A/3 and CDP1854AC/3 are high reliability
silicon gate CMOS Universal Asynchronous Receiver/Trans-
mitter (UART) circuits. They are designed to provide the
necessary formatting and control for interfacing between
serial and parallel data. For example, these UARTs can be
used to interface between a peripheral or terminal with serial
I/O ports and the 8-bit CDP1800-series microprocessor
parallel data bus system. The CDP1854A/3 is capable of full
duplex operation, i.e., simultaneous conversion of serial
input data to parallel output data and parallel input data to
serial output data.
- Mode 0 - Functionally Compatible with Industry
Types Such as the TR1602A and CDP6402
- Mode 1 - Interfaces Directly with CDP1800 Series
Microprocessors without Additional Components
• Full or Half-Duplex Operation
• Parity, Framing, and Overrun Error Detection
• Fully Programmable with Externally Selectable Word
Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and
1, 1-1/2, or 2 Stop Bits
The CDP1854A/3 UART can be programmed to operate in
one of two modes by using the mode control input. When the
mode input is high (MODE = 1), the CDP1854A/3 is directly
compatible with the CDP1800 series microprocessor system
without additional interface circuitry. When the mode input is
low (MODE = 0), the device is functionally compatible with
industry standard UARTs such as the TR1602A and
CDP6402. It is also pin compatible with these types, except
that pin 2 is used for the mode control input.
Ordering Information
PACK-
AGE
TEMP.
RANGE
5V/200K
BAUD
10V/400K
BAUD
PKG.
NO.
o
o
SBDIP
-55 C to +125 C CDP1854ACD3 CDP1854ACD3 D40.6
The CDP1854A/3 and the CDP1854AC/3 are functionally
identical. The CDP1854A/3 has a recommended operating
voltage range of 4V to 10.5V, and the CDP1854AC/3 has a
recommended operating voltage range of 4V to 6.5V.
Pinouts
CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 0)
CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 1)
TOP VIEW
TOP VIEW
VDD
MODE (V
1
2
3
4
5
6
7
8
9
40 T CLOCK
39 EPE
V
1
2
3
4
5
6
7
8
9
40 T CLOCK
39 CTS
DD
)
MODE (V
)
SS
DD
38 WLS 1
37 WLS 2
36 SBS
V
SS
38 ES
V
SS
RRD
R BUS 7
R BUS 6
R BUS 5
R BUS 4
R BUS 3
CS2
R BUS 7
R BUS 6
R BUS 5
R BUS 4
R BUS 3
37 PS1
36 NC
35 PI
35 CS3
34 RD/WR
33 T BUS 7
32 T BUS 6
31 T BUS 5
30 T BUS 4
29 T BUS 3
28 T BUS 2
27 T BUS 1
26 T BUS 0
25 SD0
34 CRL
33 T BUS 7
32 T BUS 6
31 T BUS 5
30 T BUS 4
29 T BUS 3
28 T BUS 2
27 T BUS 1
26 T BUS 0
25 SD0
R BUS 2 10
R BUS 1 11
R BUS 0 12
INT 13
R BUS 2 10
R BUS 1 11
R BUS 0 12
PE 13
FE 14
FE 14
PE/OE 15
RSEL 16
R CLOCK 17
TPB 18
OE 15
SFD 16
24 RTS
R CLOCK 17
DAR 18
24 TSRE
23 THRL
22 THRE
21 MR
23 CS1
DA 19
22 THRE
21 CLEAR
DA 19
SDI 20
SDI 20
NC = NO CONNECT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
File Number 1715.2
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
CDP1854A/3, CDP1854AC/3
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply-Voltage Range, (V
DD
)
Thermal Resistance (Typical, Note 1)
SBDIP Package. . . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
(All voltages referenced to V terminal)
55
15
o
SS
CDP1854A/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +11V
CDP1854AC/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to V
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +150 C
o
o
Maximum Storage Temperature Range (T
) . . .-65 C to +150 C
STG
Maximum Lead Temperature (Soldering 10s)
+0.5V
DD
o
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
At Distance 1/16 ±1/32 inch (1.59 ±0.79mm) . . . . . . . . . . +265 C
Device Dissipation Per Output Transistor
For T = Full Package-Temperature Range . . . . . . . . . . . 100mW
A
Operating-Temperature Range (T )
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
A
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Static Electrical Specifications
CONDITIONS
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
V
V
DD
O
IN
PARAMETER
(V)
(V)
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
(V)
MIN
MAX
MIN
MAX
UNITS
µA
µA
mA
mA
mA
mA
V
Quiescent Device Current
I
-
5
-
500
500
-
-
1000
1000
-
DD
-
10
5
-
-
Output Low Drive
(Sink) Current
I
0.4
0.75
0.5
OL
0.5
10
5
1.80
-
1.2
-
Output High Drive
(Source) Current
I
4.6
-
-0.5
-1.0
0.1
0.1
-
-
-0.35
-0.70
0.2
0.2
-
OH
9.5
10
5
-
-
Output Voltage Low-Level
(Note 1)
V
-
-
-
OL
-
10
5
-
-
V
Output Voltage
High Level (Note 1)
V
-
4.9
4.9
V
OH
-
10
5
9.9
-
9.8
-
V
Input Low Voltage
Input High Voltage
Input Leakage Current
V
0.5, 4.5
-
1.5
3
-
1.5
3
V
IL
IH
IN
0.5, 9.5
-
10
5
-
3.5
7
-
-
3.5
7
-
V
V
0.5, 4.5
-
-
-
V
0.5, 9.5
-
10
5
-
-
V
I
-
0, 5
0, 10
0, 5
0, 10
-
±1
±1
±1
±1
10
15
±5
±5
±10
±10
10
15
µA
µA
µA
µA
pF
pF
-
0, 5
0, 10
-
10
5
-
-
Three-State Output
Leakage Current
I
-
-
OUT
10
-
-
-
Input Capacitance (Note 1)
Output Capacitance (Note 1)
C
-
-
IN
C
-
-
-
-
-
OUT
NOTE:
1. Guaranteed but not tested.
2
Specifications CDP1854A/3, CDP1854AC/3
Operating Conditions At T = Full Package-Temperature Range. For maximum reliability, operating conditions should be selected
A
so that operation is always within the following ranges:
CONDITIONS
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
DC Operating Voltage Range
(V)
MIN
MAX
MIN
MAX
UNITS
V
-
4
10.5
4
6.5
Input Voltage Range
-
V
V
V
V
DD
V
SS
DD
SS
Baud Rate (Receive or Transmit)
5
-
250
520
-
215
430
K bits/s
K bits/s
10
-
-
Dynamic Electrical Specifications t , t = 15ns, V = V , V = V , C = 100pF, (See Figure 1)
R
F
IH
DD IL
SS
L
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
TRANSMITTER TIMING - MODE 1
Clock Period
(V)
MIN
MAX
MIN
MAX
UNITS
t
5
240
120
-
-
280
145
-
-
ns
ns
CC
10
Pulse Width
t
CL
Clock Low Level
5
10
5
105
55
-
-
-
-
-
-
125
65
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Clock High Level
TPB
t
135
65
155
80
CH
10
5
t
125
70
165
80
TT
10
Propagation Delay Time
Clock to Data Start Bit
t
CD
5
10
5
-
-
-
-
-
-
425
205
315
155
335
160
-
-
-
-
-
-
485
235
380
185
390
190
ns
ns
ns
ns
ns
ns
TPB to THRE
Clock to THRE
t
TTH
10
5
t
CTH
10
3
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications t , t = 15ns, V = V , V = V , C = 100pF, (See Figure 2)
R
F
IH
DD IL
SS
L
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
RECEIVER TIMING - MODE 1
Clock Period
(V)
MIN
MAX
MIN
MAX
UNITS
t
t
t
5
240
120
-
-
280
145
-
-
ns
ns
CC
10
Pulse Width
Clock Low Level
t
5
10
5
105
55
-
-
-
-
-
-
125
65
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL
Clock High Level
TPB
135
65
155
80
CH
10
5
t
125
70
165
80
TT
10
Setup Time
Data Start Bit to Clock
5
105
65
-
-
120
70
-
-
ns
ns
DC
10
Propagation Delay Time
TPB to DATA AVAILABLE
t
5
10
5
-
-
-
-
-
-
-
-
-
-
295
150
305
150
305
150
305
150
280
145
-
-
-
-
-
-
-
-
-
-
340
170
355
170
330
175
330
175
330
165
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDA
CDA
COE
Clock to DATA AVAILABLE
Clock to Overrun Error
Clock to Parity Error
t
10
5
t
10
5
t
CPE
10
5
Clock to Framing Error
t
CFE
10
4
CDP1854A/3, CDP1854AC/3
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
t
CC
t
t
CL
CH
T CLOCK
1
2
3
4
5
6
7
14
15
16
1
2
3
4
t
CD
WRITE (TPB)
(NOTE 3)
t
t
TT
CTH
t
TTH
THRE
SDO
t
CD
1ST DATA BIT
NOTES:
1. The holding register is loaded on the trailing edge of TPB.
2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + t
TC
after the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + t
later.
CD
3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0
FIGURE 1. TRANSMITTER TIMING DIAGRAM - MODE 1
CLOCK 7 1/2
SAMPLE
CLOCK 7 1/2 LOAD
HOLDING REGISTER
t
CC
t
t
CL
CH
R CLOCK
1
2
3
4
5
6
7
16
1
2
3
4
5
6
7
8
9
t
DC
(NOTE 1)
START BIT
TDA
PARITY
STOP BIT 1
SDI
t
CDA
t
DA
READ
(NOTE 2)
t
TT
TPB
t
COE
OE
(NOTE 3)
t
CPE
PE
(NOTE 3)
t
CFE
FE
NOTES:
1. If a start bit occurs at a time less than t
before a high-to-low transition of the clock, the start bit may not be recognized until the next
DC
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the receiver holding register
by the time a new word is loaded into the receiver holding register, the OE signal will come true.
3. OE and PE share terminal 15 and are also available as two separate bits in the status register.
FIGURE 2. MODE 1 RECEIVER TIMING DIAGRAM
5
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications t , t = 15ns, V = V , V = V , C = 100pF, (See Figure 3)
R
F
IH
DD IL
SS
L
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
(V)
MIN
MAX
MIN
MAX
UNITS
CPU INTERFACE - WRITE TIMING - MODE 1
Pulse Width
TPB
t
5
125
70
-
-
165
80
-
-
ns
ns
TT
10
Setup Time
RSEL to Write
t
RSW
5
10
5
20
25
65
45
-
-
-
-
10
25
75
50
-
-
-
-
ns
ns
ns
ns
Data to Write
t
DW
10
Hold Time
RSEL after Write
t
WRS
5
10
5
-10
5
-
-
-
-
-20
5
-
-
-
-
ns
ns
ns
ns
Data after Write
t
95
55
105
55
WD
10
t
TT
TPB
(NOTE 1)
t
WRS
t
RSW
RSEL
t
t
WD
DW
T BUS 0-
T BUS 7
CS3, CS1
(NOTE 1)
RD/WR, CS2
(NOTE 1)
NOTE:
1. Write is the overlap of TPB, CS1, CS3 = 1 and CS2, RD/WR = 0.
FIGURE 3. MODE 1 CPU INTERFACE (WRITE) TIMING DIAGRAM
6
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications t , t = 15ns, V = V , V = V , C = 100pF, (See Figure 4)
R
F
IH
DD IL
SS
L
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
(V)
MIN
MAX
MIN
MAX
UNITS
CPU INTERFACE - READ TIMING - MODE 1
Pulse Width
TPB
t
5
125
70
-
-
165
80
-
-
ns
ns
TT
10
Setup Time
RSEL to TPB
t
t
5
15
20
-
-
0
-
-
ns
ns
RST
TRS
RDV
10
10
Hold Time
RSEL after TPB
5
-10
5
-
-
-25
0
-
-
ns
ns
10
Propagation Delay Time
Read to Data Valid Time
t
5
10
5
-
-
-
-
360
165
250
125
-
-
-
-
420
195
295
145
ns
ns
ns
ns
RESEL to Data Valid Time
t
RSDV
10
t
TT
TPB
t
TRS
t
RST
RSEL
t
RSDV
R BUS 0-
R BUS 7
t
RDV
RD/WR, CS1, CS3
(NOTE 1)
CS2
NOTE:
1. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0.
FIGURE 4. MODE 1 CPU INTERFACE (READ) TIMING DIAGRAM
7
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications t , t = 15ns, V = V , V = V , C = 100pF, (See Figure 5)
R
F
IH
DD IL
SS
L
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
(V)
MIN
MAX
MIN
MAX
UNITS
INTERFACE TIMING - MODE 0
Pulse Width
CRL
t
5
10
5
105
55
-
-
-
-
125
65
-
-
-
-
ns
ns
ns
ns
CRL
MR
t
340
160
385
175
MR
10
Setup Time
Control Word to CRL
t
t
5
80
40
-
-
85
60
-
-
ns
ns
CWC
CCW
10
Hold Time
Control Word after CRL
5
65
45
-
-
65
45
-
-
ns
ns
10
Propagation Delay Time
SFD High to SOD
t
5
10
5
-
-
175
-
-
195
ns
ns
ns
ns
ns
ns
ns
ns
SFDH
105
115
SFD Low to SOD
t
165
90
-
-
195
105
-
-
SFDL
10
5
-
185
110
-
-
205
130
-
RRD High to Receiver Register
High Impedance
t
RRDH
10
5
-
-
RRD Low to Receiver Register Active
t
165
90
195
105
RRDL
10
-
-
CONTROL INPUT WORD TIMING
CONTROL WORD INPUT
CRL
CONTROL WORD BYTE
t
t
CCW
CWC
t
CRL
STATUS OUTPUT TIMING
STATUS OUTPUTS
SFD
t
t
SFDL
SFDH
RECEIVER REGISTER DISCONNECT TIMING
R BUS 0
R BUS 7
t
t
RRDL
RRDH
RRD
FIGURE 5. MODE 0 INTERFACE TIMING DIAGRAM
8
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications t , t = 15ns, V = V , V = V , C = 100pF, (See Figure 6)
R
F
IH
DD IL
SS
L
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
TRANSMITTER TIMING - MODE 0
Clock Period
(V)
MIN
MAX
MIN
MAX
UNITS
t
5
240
120
-
-
280
145
-
-
ns
ns
CC
10
Pulse Width
Clock Low Level
t
5
10
5
105
55
-
-
-
-
-
-
125
65
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL
Clock High Level
THRL
t
135
65
155
80
CH
10
5
t
THTH
140
80
165
85
10
Setup Time
THRL to Clock
t
5
10
5
205
120
25
-
-
-
-
235
140
30
-
-
-
-
ns
ns
ns
ns
THC
Data to THRL
t
t
DT
TD
CD
10
20
25
Hold Time
Data after THRL
5
60
45
-
-
95
75
-
-
ns
ns
10
Propagation Delay Time
Clock to Data Start Bit
t
5
10
5
-
-
-
-
-
-
-
-
435
205
345
175
275
145
345
165
-
-
-
-
-
-
-
-
505
235
420
200
325
165
405
190
ns
ns
ns
ns
ns
ns
ns
ns
Clock to THRE
THRL to THRE
Clock to TSRE
t
CT
10
5
t
TTHR
10
5
t
TTS
10
9
CDP1854A/3, CDP1854AC/3
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
t
CC
t
t
CL
CH
T CLOCK
1
2
3
4
5
6
7
14
15
16
1
2
3
t
THC
THRL
SDO
t
t
t
THTH
CD
t
CD
1ST DATA BIT
t
TTHR
CT
THRE
TSRE
t
TTS
t
t
TD
DT
T BUS 0
T BUS 7
DATA
NOTES:
1. The holding register is loaded on the trailing edge of THRL.
2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + t
THC
after the trailing edge of THRL and transmission of a start bit occurs 1/2 clock period + t
later.
CD
FIGURE 6. MODE 0 TRANSMITTER TIMING DIAGRAM
CLOCK 7 1/2
SAMPLE
CLOCK 7 1/2 LOAD
HOLDING REGISTER
t
CC
t
t
CL
CH
R CLOCK
1
2
3
4
5
6
7
16
1
2
3
4
5
6
7
8
9
t
DC
(NOTE 1)
START BIT
PARITY
STOP BIT 1
SDI
t
CDV
R BUS 0 -
R BUS 7
DATA
DA
t
t
t
DDA
CDA
DAR
t
COE
DD
OE
(NOTE 2)
t
CPE
PE
FE
t
CFE
NOTES:
1. If a start bit occurs at a time less than t
before a high-to-low transition of the clock, the start bit may not be recognized until the next
DC
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding
register, the OE signal will come true.
FIGURE 7. MODE 0 RECEIVER TIMING DIAGRAM
10
CDP1854A/3, CDP1854AC/3
Dynamic Electrical Specifications t , t = 15ns, V = V , V = V , C = 100pF, (See Figure 7)
R
F
IH
DD IL
SS
L
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
RECEIVER TIMING - MODE 0
Clock Period
(V)
MIN
MAX
MIN
MAX
UNITS
t
5
240
120
-
-
280
145
-
-
ns
ns
CC
10
Pulse Width
Clock Low Level
t
5
10
5
105
55
-
-
-
-
-
-
125
65
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CL
CH
DD
Clock High Level
t
t
135
65
155
80
10
5
DATA AVAILABLE RESET
75
90
10
45
50
Setup Time
Data Start Bit to Clock
t
5
105
65
-
-
130
85
-
-
ns
ns
DC
10
Propagation Delay Time
DATA AVAILABLE RESET to
Data Available
t
t
t
5
10
5
-
-
-
-
-
-
-
-
-
-
-
-
240
130
360
175
320
155
365
170
275
135
270
135
-
-
-
-
-
-
-
-
-
-
-
-
280
145
420
195
375
180
415
190
320
155
320
165
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DDA
CDV
CDA
COE
Clock to Data Valid
10
5
Clock to Data Available
Clock to Overrun Error
Clock to Parity Error
Clock to Framing Error
10
5
t
10
5
t
CPE
10
5
t
CFE
10
11
CDP1854A/3, CDP1854AC/3
16 / f
CLOCK
NEXT DATA WORD
5 - 8 DATA BITS
STOP BITS 1, 1-1/2 OR 2
START BIT
PARITY BIT
DATA
LSB
DATA
MSB
FIGURE 8. SERIAL DATA WORD FORMAT
Burn-In Circuit
V
V
V
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
DD
SS
DD
V
SS
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ALL RESISTORS ARE 47kΩ ±20%
TYPE
V
TEMPERATURE
TIME
DD
o
CDP1854A/3
11
7
+125 C
160 hrs.
160 hrs.
o
CDP1854AC/3
+125 C
FIGURE 9. BIAS/STATIC BURN-IN CIRCUIT
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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12
相关型号：
CDP1854AD/3
IC 1 CHANNEL(S), 250K bps, SERIAL COMM CONTROLLER, CDIP40, Serial IO/Communication Controller
RENESAS
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