CDP1879C-1 [INTERSIL]
CMOS Real-Time Clock; CMOS实时时钟
| 型号： | CDP1879C-1 |
| 厂家： | 
Intersil |
| 描述： | CMOS Real-Time Clock |
| 文件： | 总18页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDP1879,
CDP1879C-1
CMOS Real-Time Clock
March 1997
Features
Description
The CDP1879 real-time clock supplies time and calendar information
from seconds to months in BCD format. It consists of 5 separately
addressable and programmable counters that divide down an oscillator
input. The clock input can have any one of 4 possible frequencies,
allowing flexibility in the choice of crystal or external clock sources.
Using an external 32kHz clock source, timekeeping can be performed
down to 2.5V (see Standby (Timekeeping) Voltage Operation).
• CPU Interface for Use with General-Purpose
Microprocessors
• Time Of Day/Calendar
• Reads Seconds, Minutes, Hours
• Reads Day of Month and Month
• Alarm Circuit With Seconds, Minutes or Hours
Operation
The device can be memory-mapped for use with any general-purpose
microprocessor and has the additional capability of operating in the
CDP1800 series input/output mode.
• Power Down Mode
The real-time clock functions as a time-of-day/calendar with an alarm
capability that can be set for combinations of seconds, minutes or
hours. Alarm time is configured by loading alarm latches that activate
an interrupt output through a comparator when the counter and alarm
latch values are equal.
• Separate Clock Output Selects 1 of 15 Square Wave
Signals
• Interrupt Output Activated By Clock Output and/or
Alarm Circuit
Fifteen selectable square-wave signals are available as a separate
clock output signal and can also activate the interrupt output. A status
register is available to indicate the interrupt source. The value in an 8 bit
control register determines the operational characteristics of the device,
by selecting the prescaler divisor and the clock output, and controls the
load and alarm functions.
• Date Integrity Sampling for Clock Rollover Eliminated
• On-Board Oscillator:
- Crystal Operation CDP1879 at 10V. . . . . . . 4.19MHz,
2.09MHz or 1.048MHz
- Crystal Operation CDP1879C-1 at 5V . . . . . 4.19MHz,
2.09MHz or 1.048MHz or 32kHz
A transparent “freeze” circuit preclude clock rollover during counter and
latch access times to assure stable and accurate values in the counters
and alarm latches.
- External Clock Operation at 10V or 5V. . . . 4.19MHz,
2.09MHz, 1.048MHz or 32kHz
The CDP1879 is functionally identical to the CDP1879C-1. The
CDP1879 has a recommended operating voltage range of 4V to 10.5V,
and the CDP1879C-1 has a recommended operating voltage range of
4V to 6.5V. The CDP1879 and the CDP1879C-1 are supplied in 24 lead
hermetic dual-in-line side-brazed ceramic packages (D suffix) and 24
lead dual-in-line plastic packages (E suffix).
• Addressable in Memory Space or CDP1800 Series I/O
Mode
• Low Standby (Timekeeping) Voltage with External Clock
• Related Literature
- AN7275, Guide to the Use of CD1879 and
CDP1879C1 Real Time Clock
Ordering Information
TEMP
RANGE
PKG.
NO.
PACKAGE
5V
10V
o
Pinout
PDIP
-40 C to
CDP1879CE1 CDP1879E
E24.6
o
+85 C
CDP1879, CDP1879C-1 (PDIP, SBDIP)
o
SBDIP
Burn-In
-40 C to
CDP1879CD1
-
-
D24.6
D24.6
TOP VIEW
o
+85 C
CDP1879CD1X
INT
RESET
POWER DOWN
RD
1
2
3
4
5
6
7
8
9
24
V
DD
23 XTAL
CDP1879 Modes of Operation
22 XTAL
CLK
21
OPERATION
FUNCTION
OUT
Read
1. Seconds, minutes, hours, date and month counters
2. Status register to identify interrupt source
IO/MEM
TPB/WR
TPA
20 DB7
19 DB6
18 DB5
17 DB4
16 DB3
15 DB2
14 DB1
13 DB0
Write
1. Control register to set device operation
2. Seconds, minutes, hours, date and month counters
3. Alarm latches for alarm time
CS
A2
Power Down
Interrupt
1. Three-state interrupt output with active alarm or
clock out circuitry for wake-up control
2. Data bus and address inputs are “DON’T CARE”
A1 10
A0 11
1. Clock out as source
V
12
SS
2. Alarm time as source
3. Either interrupt can occur during normal or power
down mode
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1360.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19949-104
CDP1879, CDP1879C-1
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, V
DD
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
(Voltage referenced to V Terminal)
CDP1879 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1879C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . .±10mA
SS
PDIP Package . . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
60
50
N/A
12
Operating Temperature Range (T )
A
o
o
+0.5V
DD
Package Type D, H . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40 C to +85 C
o
o
o
o
Device Dissipation Per Output Transistor . . . . . . . . . . . . . . . . 40mW
Storage Temperature Range (T
). . . . . . . . . . . .-65 C to +150 C
STG
o
For T = Full Package Temperature Range
A
Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ±1/32 in. (1.59 ± 0.79mm) From Case for 10s Max
(All Package Types)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions at T = FuIl Package-Temperature Range, Unless Otherwise specified. For maximum reliability, operating con-
A
ditions should be selected so that operation Is always within the following ranges:
LIMITS
CDP1879
CDPl879C-1
PARAMETER
DC Operating Voltage Range
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
V
Input Voltage Range
V
V
V
V
SS
DD
SS
DD
DC Standby (Timekeeping) Voltage (Note 1),
V
STBY
o
o
T = -40 C to +85 C (Note 2)
3
-
-
3
-
V
V
A
o
o
T = 0 to +70 C
2.5
2.5
A
Clock Input Rise or Fall Time, t , t
R
F
V
V
= 5V
-
-
10
1
-
-
10
-
µs
µs
DD
DD
= 10V
NOTES:
1. Timekeeping function only, no READ/WRITE accesses, 32kHz external frequency source only, no crystal operation.
2. See Standby (Timekeeping) Voltage Operation.
4-105
CDP1879, CDP1879C-1
AM - PM
AND
HOUR LOGIC
CALENDAR
LOGIC
FREEZE
CIRCUIT
XTAL
XTAL
OSCILLATOR
PRESCALE
SECOND
MINUTE
HOUR
DAY
MONTH
PRESCALE
SELECT
CLOCK
SELECT
CONTROL
REGISTER
8-BIT DATA BUS
CLOCK OUT
INT
CLOCK AND
INT. LOGIC
COMPARATOR
RESET
SECOND
LATCH
MINUTE
LATCH
HOUR
LATCH
V
DD
SS
V
INT. STATUS
REGISTER
I/O
INTERFACE
DB0-DB7
A0
A1
A2
TPA
ADDRESS DECODE
AND
CONTROL LOGIC
I-O MEM
TPB/WR
RD
CS
POWER DOWN
FIGURE 1. REAL-TIME CLOCK FUNCTIONAL DIAGRAM
TABLE 1.
CONTROL REGISTER BIT ASSIGNMENT
TABLE 2.
ADDRESSES
Latch, Counter Seconds
Latch, Counter Minutes
Latch, Counter Hours
Counter, Day
A2
0
A1
1
A0
0
Bit 1, 0
Frequency 00
32768Hz
0
1
1
Select 01
1.048576MHz
2.097152MHz
4.194304MHz
10
11
1
0
0
1
0
1
Bit 2
Start/Stop
1 = Start
0 = Stop
Counter, Month
1
1
0
Control, Register
1
1
1
Bit 3
Status Register
1
1
1
Counter/Latch Control
“0” = Write to Counter and disable alarm
“1” = Write to and enable alarm Clock Select
MSB of Hours Counters (Bit 7) is an AM-PM Bit. 0 = AM; 1 = PM
Bit 6 of Hours Counter Controls 12/24 hr. 1 = 12 Hr: 0 = 24 Hr.
Bit 7, 6, 5, 4
Status Register: Bit 7 MSB = Alarm
Interrupt Source: Bit 6 = Clock.
0000 - disableµs
0001 - 488.2µs
0010 - 976.5µs
0011 - 1953.1µs
0100 - 3906.2µs
0101 - 7812.5µs
0110 - 15.625ms
0111 - 31.25ms
1000 - 62.5ms
1001 - 125ms
1010 - 250ms
1011 - 500ms
1100 - sec.
1101 - min.
1110 - hour
1111 - day
MSB of Month Counter (Bit 7) is a Leap Year Bit 0 = No, 1 = Yes.
4-106
CDP1879, CDP1879C-1
o
o
Static Electrical Specifications at T -40 C to +85 C V ± 5%, Unless Otherwise Specified
A
DD
CONDITIONS
LIMITS
CDP1879
CDPl879C-1
V
(V)
V
V
DD
(V)
(NOTE 1)
TYP
(NOTE 1)
TYP
O
IN
PARAMETER
(V)
0, 5
0, 10
0, 5
0,10
0, 5
0,10
0, 5
0,10
0, 5
0,10
0, 5
0,10
0, 5
0,10
0, 5
0,10
MIN
-
MAX
MIN
MAX UNITS
Ouiescent Device Current
I
5
0.01
1
50
-
0.02
200
µA
DD
10
5
-
200
-
-
-
Output Low Drive (Sink)
0.4
0.5
4.6
9.5
0.4
0.5
4.6
9.5
0.4
0.5
4.6
9.5
-
1.8
3.6
-1.1
-2.6
0.6
1.2
-1.1
-2.6
0.2
0.4
-0.15
-0.3
-
4
-
-
-
-
Current, Data Bus and INT
l
OL
10
5
7
-
-
-
-
Output High Drive (Source)
Current, Data Bus and INT
-2.3
-4.4
1.4
3
-
-1.1
-2.3
-
I
OH
OL
10
5
-
-
-
-
Output Low Drive (Sink)
Current, Clock Out
-
0.6
1.4
-
l
10
5
-
-
-
-
mA
Output High Drive (Source)
Current, Clock Out
-2.3
-4.4
0.9
2
-
-1.1
-2.3
-
I
OH
10
5
-
-
-
-
Output Low Drive (Sink)
Current, XTAL Out
-
-
0.2
0.9
-
l
OL
10
5
-
-
-
Output High Drive (Source)
Current, XTAL Out
-0.4
-0.7
0
-
-0.15
-0.4
-
-
I
OH
10
5
-
-
-
-
-
0
-
Output Voltage
Low-Level
(Note 2)
0.1
0.1
0.1
-
V
OL
-
10
-
0
Output Voltage
High Level
(Note 2)
-
-
0, 5
5
4.9
9.9
5
-
-
4.9
-
5
-
-
-
V
OH
0, 10
10
10
V
Input Low Voltage
Input High Voltage
Input Leakage Current
V
V
0.5, 4.5
0.5, 9.5
-
-
5
10
-
-
-
-
1.5
3
-
-
-
-
1.5
-
IL
0.5, 4.5
0.5, 9.5
-
-
5
10
3.5
7
-
-
-
-
3.5
-
-
-
-
-
IH
I
Any
Input
0, 5
0, 10
5
10
-
-
-
-
±1
±2
-
-
-
-
±1
-
IN
µA
Three-State Output
Leakage Current
0, 5
0,5
5
-
-
-
-
±1
±1
-
-
-
-
±1
I
OUT
0,10
0,10
10
-
Operating Current (Note 3)
External Clock
32kHz
1MHz
2MHz
4MHz
32kHz
1MHz
2MHz
4MHz
32kHz
1MHz
2MHz
4MHz
1MHz
2MHz
4MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.01
0.2
0.35
0.7
0.03
0.4
0.8
1.6
0.1
0.3
0.4
0.6
1.6
1.8
2
0.15
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.01
0.2
0.35
0.7
-
0.15
External Clock
1
1.5
2
External Clock
5
1.5
2
External Clock
5
External Clock
10
10
10
10
5
0.25
2
-
External Clock
-
-
External Clock
3
-
-
External Clock
4.5
0.25
0.5
0.6
0.8
3
-
mA
XTAL Oscillator (Note 4)
XTAL Oscillator (Note 4)
XTAL Oscillator (Note 4)
XTAL Oscillator (Note 4)
XTAL Oscillator (Note 4)
XTAL Oscillator (Note 4)
XTAL Oscillator (Note 4)
0.1
0.3
0.4
0.6
-
0.25
0.5
0.6
0.8
-
5
5
5
10
10
10
3.5
5
-
-
-
-
4-107
CDP1879, CDP1879C-1
o
o
Static Electrical Specifications at T -40 C to +85 C V ± 5%, Unless Otherwise Specified (Continued)
A
DD
CONDITIONS
LIMITS
CDP1879
CDPl879C-1
V
(V)
V
(V)
V
DD
(V)
(NOTE 1)
TYP
(NOTE 1)
TYP
O
IN
PARAMETER
Input Capacitance
MIN
MAX
MIN
MAX UNITS
C
C
-
-
-
-
-
-
-
-
-
-
-
-
-
5
10
-
7.5
15
10
1
-
-
-
-
5
10
-
7.5
15
10
-
pF
IN
Output Capacitance
-
OUT
Maximum Clock Rise
and Fall Times
t , t
5
µs
R
F
10
-
-
NOTES:
o
1. Typical values are for T = 25 C and nominal V
.
A
DD
2. I = I
OL
= 1µA.
OH
3. Operating current measured with clockout = 488.2µs and no load.
4. See Table 3 and Figure 6 for oscillator circuit information.
Programming Model
WRITE AND READ REGISTERS
WRITE ONLY REGISTERS
BCD FORMAT
DB7
DB0
0
DB7
DB0
DB0
7
6
5
4
3
2
1
TENS 0-5
UNITS 0-9
UNITS 0-9
CONTROL REGISTER
SECONDS COUNTER (00-59)
DB7
DB0-DB1 - FREQUENCY SELECT
DB2 - START/STOP
DB3 - COUNTER/ALARM LATCH CONTROL
DB4-DB7 - CLOCK OUTPUT SELECT
TENS 0-5
DB7
DB0
DB0
DB0
MINUTES COUNTER (00-59)
TENS 0-5
SECONDS ALARM LATCH (00-59)
DB7
UNITS 0-9
UNITS 0-9
UNITS 0-9
DB7
X
DB6
X
DB0
TENS 0-2
UNITS 0-9
HOURS COUNTER (01 - 12 OR 00-23)
DB7 0=AM, 1=PM
DB6 0=24 HR, 1=12 HR
TENS 0-5
MINUTES ALARM LATCH (00-59)
DB7
DB0
DB0
DB7
X
DB6
X
TENS 0-3
UNITS 0-9
UNITS 0-9
TENS 0-2
DAY OF MONTH COUNTER
(01-28, 29, 30, 31)
HOURS ALARM LATCH (01-12 OR 00-23
12 HR, DB7=0 AM, 1=PM
24 HR, DB7=X
DB7
X
TENS 0 OR 1
READ ONLY REGISTER
MONTH COUNTER
(JAN=1 DEC=12)
DB7 0=NO LEAP YEAR
1=LEAP YEAR
DB7
DB6
X
DB0
0
X
0
0
0
0
0
INTERRUPT STATUS REGISTER
DB7=1 ALARM CIRCUIT ACTIVATED INT.
DB6=1 CLOCK OUTPUT ACTIVATED INT.
4-108
CDP1879, CDP1879C-1
REGISTER TRUTH TABLE
ACTIVE SIGNAL
ADDRESS
BIT 3 CONTROL
A2
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
A1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
AO
0
TPB/WR
RD
-
REGISTER
REGISTER OPERATION
Write Seconds Counter
Read Seconds Counter
Write Minutes Counter
Read Minutes Counter
Write Hours Counter
X
-
0
0
0
0
0
0
0
0
0
0
1
1
1
-
0
X
-
1
X
-
1
X
-
0
X
-
0
X
-
Read Hours Counter
1
X
-
Write Date Counter
1
X
-
Read Date Counter
0
X
-
Write Month Counter
0
X
-
Read Month Counter
Write Seconds Alarm Latch
Write Minutes Alarm Latch
Write Hours Alarm Latch
Write Control Register
Read Int. Status Register
0
X
X
X
X
-
1
-
0
-
1
-
1
X
-
General Operation
The real-time clock contains seconds, minutes, and hours, Operational control of the real-time clock is determined by
date and month counters that hold time of day/calendar the byte in a write-only control register. The 8-bit value in this
information (see Figure 2). The frequency of an intrinsic register determines the correct divisor for the prescaler, a
oscillator is divided down to supply a once-a-second signal data direction and alarm enable bit, clock output select, and
to the counter series string. The counters are separately start/stop control (see Figure 4).
addressable and can be written to or read from.
Data transfer and addressing are accomplished in two
The real-time clock contains seconds, minutes and hour modes of operation, memory mapping and I/O mapping
write-only alarm latches that store the alarm time (see Fig- using the CDP1800-series microprocessors. The mode is
ure 3). When the value of the alarm latches and counters are selected by the level on an input pin. (IO/MEM). Memory
equal, the interrupt output is activated. The interrupt output mapping implies use of the address lines as chip selects and
can also be activated by a clock output transition. The clock address inputs during linear selection or partial or full decod-
output is derived from the prescaler and counters and can ing methods. I/O mapping with the CDP1800-series micro-
be one of 15 square-wave signals. The value in the read- processors involves use of the N line outputs in conjunction
only interrupt status register identifies the interrupt source.
with input and output instructions to transfer data to and from
memory.
4-109
CDP1879, CDP1879C-1
AM - PM
AND
HOUR LOGIC
CALENDAR
LOGIC
FREEZE
CIRCUIT
XTAL
XTAL
OSCILLATOR
PRESCALE
SECOND
MINUTE
HOUR
DAY
MONTH
PRESCALE
SELECT
CLOCK
SELECT
CONTROL
REGISTER
8-BIT DATA BUS
CLOCK OUT
INT
CLOCK AND
INT. LOGIC
COMPARATOR
RESET
SECOND
LATCH
MINUTE
LATCH
HOUR
LATCH
V
DD
SS
V
INT. STATUS
REGISTER
I/O
INTERFACE
DB0-DB7
A0
A1
A2
TPA
ADDRESS DECODE
AND
CONTROL LOGIC
IO/MEM
TPB/WR
RD
CS
POWER DOWN
FIGURE 2. FUNCTIONAL DIAGRAM - TIME COUNTERS HIGHLIGHTED
4-110
CDP1879, CDP1879C-1
AM - PM
AND
HOUR LOGIC
CALENDAR
LOGIC
FREEZE
CIRCUIT
XTAL
XTAL
OSCILLATOR
PRESCALE
SECOND
MINUTE
HOUR
DAY
MONTH
PRESCALE
SELECT
CLOCK
SELECT
CONTROL
REGISTER
8-BIT DATA BUS
CLOCK OUT
INT
CLOCK AND
INT. LOGIC
COMPARATOR
RESET
SECOND
LATCH
MINUTE
LATCH
HOUR
LATCH
V
DD
SS
V
INT. STATUS
REGISTER
I/O
INTERFACE
DB0-DB7
A0
A1
A2
TPA
ADDRESS DECODE
AND
CONTROL LOGIC
IO/MEM
TPB/WR
RD
CS
POWER DOWN
FIGURE 3. FUNCTIONAL DIAGRAM - ALARM CIRCUIT, CLOCK OUTPUT, INTERRUPT, AND STATUS REGISTERS HIGHLIGHTED
Operational Sequence
Power is applied and the real-time clock is reset. This sets If one of the 15 sub second-to-day clock outputs is selected
the interrupt output pin high. After the CS pin is set high and by the byte in the control register, the clock output pin tog-
with address 7 on the address input lines, the control register gles at that frequency (50% duty cycle) The interrupt output
is loaded via the data bus to configure the clock.
will also be set low on the first clock out negative transition.
The interrupt source (alarm or clock out) can be determined
by reading the interrupt status register. The clock output can
be deselected by placing zero in the upper nibble of the con-
trol register if the alarm function is selected as the only inter-
rupt source.
With selective addressing, the seconds through month
counters are then written to and loaded to set the current time.
The real-time clock will now hold the current “wall clock” time,
with an accuracy determined by the crystal or external clock
used. If the alarm function is desired, the control register is
accessed and loaded again. This new byte will allow subse-
quent time data to be entered into the seconds, minutes and
hours alarm latches. This sequence is also used when select-
ing one of the 15 available clock-out signals.
Counters
The counter section consists of an on-board oscillator, a
prescaler and 5 counters that hold the time of day/calendar
information (see Figure 2).
If the alarm function was selected, the interrupt output pin
will be set low when the values in the seconds, minutes and
hour alarm latches match those in the seconds, minutes and
hour counters.
1 of 4 possible external crystals determine the frequency of the
on-board oscillator (32,768Hz, 1.048576MHz, 2.097152MHz,
4.194304MHz). The oscillator output is divided down by a pres-
4-111
CDP1879, CDP1879C-1
caler that supplies a once-a-second pulse to the counters. The indicate AM or PM and will be inverted every 12th hour. (0=AM,
seconds counter divide the pulse by 60 and its output clocks 1=PM). Bit 6 of the hours counter is user programmed to
the minute counter every 60 seconds Further division by the enable the hours counter for 12 or 24 hour operation.
minutes, hours, day of month and month counters result in 5 (0=24,1=12). If 24-hour operation is selected, the AM-PM bit is
counters holding data that reflect the time/calendar from sec- “don't care”, but still toggles every 12th hour. Writing to the sec-
onds to months. The counters are addressed separately and onds counter resets the last 7 stages of the prescaler, allowing
BCD data is transferred to and from via the data bus. The most time accuracy to approximately 1/100 of a second.
significant bit of the hours counter (Bit 7) is user programmed to
AM - PM
CALENDAR
LOGIC
FREEZE
CIRCUIT
AND
HOUR LOGIC
XTAL
XTAL
OSCILLATOR
PRESCALE
SECOND
MINUTE
HOUR
DAY
MONTH
PRESCALE
SELECT
CLOCK
SELECT
CONTROL
REGISTER
8-BIT DATA BUS
CLOCK OUT
INT
CLOCK AND
INT. LOGIC
COMPARATOR
RESET
SECOND
LATCH
MINUTE
LATCH
HOUR
LATCH
V
DD
SS
V
INT. STATUS
REGISTER
I/O
INTERFACE
DB0-DB7
A0
A1
A2
TPA
ADDRESS DECODE
AND
CONTROL LOGIC
IO/MEM
TPB/WR
RD
CS
POWER DOWN
FIGURE 4. FUNCTIONAL DIAGRAM - CONTROL REGISTER HIGHLIGHTED
The most significant bit of the month counter is a Leap Year The write-only alarm latches have the same addresses as
bit. If it is set to “1”, the counter will count to February 29, their comparable counters. Bit 3 in the control register deter-
then roll to March 1. If set to “0” it will go to March 1st after mines data direction to the latches or counters and alarm
February 28th.
enabling. For example, during a write cycle, if bit-3 in the
control register is a “1”, addressing the seconds counter or
alarm latch will load the seconds alarm latch from the data
bus and will enable the alarm function. Conversely, if bit-3 in
the control register is a “0”, addressing the seconds counter
or alarm latch during a write cycle will place the value on the
data bus into the seconds counter and will disable the alarm
function. The interrupt output can be activated by the alarm
circuit or the clock output. When an interrupt occurs, the
Alarm And Interrupt Status Register
The alarm circuit consists of 1) seconds, minutes and hour
alarm latches that hold the alarm time, 2) the outputs of the
seconds, minutes and hour counters, and 3) a comparator
that drives an interrupt output. The comparator senses the
counter and alarm latch values and activates the interrupt
output (active low) when they are equal (see Figure 3).
4-112
CDP1879, CDP1879C-1
upper two bits of the interrupt status register identify the
1) A “0” in bit-3 will direct subsequent data to or from
the counter selected and the alarm function will be
disabled.
interrupt source. The interrupt status register has the same
address as the control register. Addressing the interrupt sta-
tus register with the RD line active will place these register
bits on the data bus. Bits 0-5 are held low. A “1” in bit-6 rep-
resents a clock output transition as the interrupt source. A
“1” in bit-7 will identify the alarm circuit as the interrupt
source.
2) A “1” in bit-3 will direct subsequent data to or from
the alarm latch and will enable the alarm.
4. Bits 4 to 7 - Clock Select - These bits select one of 15
square-wave signals that will be present at the “clock-
out” pin. If bit-4 to bit-7 are zero's, the clock output pin will
be high. If a clock is selected, the first high-to-low clock
out transition will activate the interrupt pin (active low) and
place a “1” in bit-6 of the status register. Writing to the
control register or activating the reset pin will set the inter-
rupt pin high and reset the interrupt status register.
Activating the reset pin (active low) resets the hour latch to
“30” which prevents a match between alarm and time regis-
ters during an initialization procedure. Activating the reset
pin or writing to the control register resets the interrupt out-
put (high) and clears the interrupt status register
Normal operation requires the control register to be written
to and loaded first with a control word. However, subsequent
writing to a counter if a “clock out” is selected may cause an
interrupt out signal. Therefore, “clock-out” should be dese-
lected by writing zero's into bit-4 through bit-7 if the interrupt
is used. When the counters are loaded, the control register
is again written to with the value in the upper nibble selecting
the “clock out” signal. See Table 1.
Clock Output
One of 15 counter and prescaler overflows can be selected
as a 50% duty cycle output signal that is available at the
“clock out” pin. The frequency is selected by the upper nibble
in the control register. For example, selecting a one-second
clock output will result in a repetitive signal that will be high
for 500ms and low for the same period. The high-to-low tran-
sition of the output signal will set the clock bit in the status
register and activate the interrupt output. The level of the
“clock out” signal is derived from the value in the counter.
Read And Write Signals
Example - if hours clock is selected and the minutes counter When the IO/MEM pin is low, the real-time clock is enabled
holds 4 minutes, the clock out will be low for 26 minutes and for memory mapped operation. Data on the bus is placed in,
high for 30 minutes Thereafter, the clock out will toggle at a or read from a counter, alarm latch or register by 1) placing
50% duty cycle rate (see Table 1 and Figure 3).
the CS pin high, 2) selective addressing, 3) placing the
TPB/WR pin low during a write cycle with the RD pin high or
4) setting the RD pin low during a read cycle with this
TPB/WR pin high.
CONTROL REGISTER (SEE TABLE 1 AND FIGURE 4)
BIT
7
BIT
The I/O mapping mode used with the CDP1800 series
microprocessor is selected by setting the IO/MEM pin high.
The TPB/WR pin on the real-time clock is connected to the
TPB output pin of the microprocessor. Data on that bus is
written to or read from the counters, latches and registers by
1) placing the CS pin high, 2) selective addressing utilizing
the microprocessor N lines and I/O instructions, 3) placing
the TPB/WR pin high with the RD pin low during an output or
write operation (data is latched on TPB's trailing edge), 4)
setting the RD line high during an input or read operation.
Data is placed on the bus by the real-time clock between the
trailing edges of TPA and TPB.
6
5
4
3
2
1
0
CONTROL REGISTER BYTE
The 8-bit value in the control register determines the follow-
ing:
1. Bit 0 and 1 - Frequency Select - Since there are one of 4
possible crystals the oscillator in the real-time clock can
operate with, these bit levels determine the prescaler divi-
sor so that an accurate one second pulse is supplied to
the counter series string.
BIT 1
BIT 0
FREQUENCY
32,768Hz
0
0
1
1
0
1
0
1
Freeze Circuit
1.048576MHz
2.097152MHz
4.194304MHz
Since writing to or reading from the counters or alarm
latches is performed asynchronously, the once-a-second
signal from the prescaler may pulse the counter series string
during these operations. This can result in erroneous data.
To avoid this occurring, a transparent “freeze” circuit' is incor-
porated into the real-time clock. This circuit is designed to
trap and hold the one-second input clock transition if it
occurs during access times. When the operations are com-
pleted, it is inserted into the counter series string. To utilize
the “freeze” circuit, address “1” (A0 = 1, A1 = 0, A2 = 0) is
selected first while performing a write operation. Read or
write accesses may now be performed with assurance the
data is stable. All operations must be concluded within
2. Bit 2 - Start-Stop Control - Counter enabling is controlled
by the value at this location. A “1” will allow the counters
to function and a “0” in this location will disable the
counters.
3 Bit 3 - Counter/Latch Control - The level at this location
controls two functions. It is required since the counters
and alarm latches have the same addresses.
4-113
CDP1879, CDP1879C-1
250ms of the address “1” access. In memory mapping any Microprocessor Real-Time Clock
dummy write operation after selecting address “1” will set the
MRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RD
“freeze” circuit. If using the I/O mode, a 61 output instruction
will perform the same function. There is no time restriction
on subsequent accesses as long as the read or write opera-
tions are preceded by selecting address “1”.
TPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPB/WR
TPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPA
N LINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADDRESS LINES
Power Down
IO/MEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
Power down operation is initiated with a low signal on the
"POWER DOWN” input pin. In conjunction with the interrupt
output, it is used to supply external control circuits with a 3
level control signal. The operating current is not appreciably
reduced during “POWER DOWN” operation. When power
down is initiated, any inputs on the address or data bus are
ignored. The clock output is set low. The interrupt output is
three-stated. If enabled previously, the alarm circuitry is
active and will set the interrupt output pin low when alarm
time occurs. The interrupt output will also go low if a clock
was selected and an internal high-to-low transition occurs
during power down. The clock output pin will remain low. If
power down is initiated in the middle of a read or write
sequence, it will not become activated until the read or write
cycle is completed.
CS - CHIP SELECT - Used to enable or disable the inputs
and outputs. TPA is used to strobe and latch a positive level
on this pin to enable the device.
XTAL AND XTAL - The frequency of the internal oscillator is
determined by the value of the crystal connected to these
pins. “XTAL” may be driven directly by an external frequency
source.
Clock Out - 1 of 15 square wave frequencies will appear at
this pin when selected. During power down, this pin will be
placed low, and will be high during normal operation when
the clock is deselected.
Power Down - Power Down Control - A low on this pin will
place the device in the power down mode.
INT - Interrupt Output - A low on this pin indicates an active
alarm time or high-to-low transition of the “clock out” signal.
Pin Functions
V
, V - Power and ground for device.
DD SS
RESET - A low on this pin clears the status register and
places the interrupt output pin high.
DB0 - DB7 - DATA BUS - 8-bit bidirectional bus that trans-
fers BCD data to and from the counters, latches and regis-
ters.
Frequency Input Requirements
A0, A1, A2 - Address inputs that select a counter, latch or
register to read from or write to.
The Real-Time Clock operates with the following frequency
input sources:
TPA - Strobe input used to latch the value on the chip select
pin. CS is latched on the trailing edge of TPA. During mem-
ory mapping, it is used to latch the high order address bit
used for the chip select. When the real-time clock is used
with other microprocessors, or when the high order address
of the CDP1800 series microprocessor is externally latched,
1. An external crystal that is used with the on-board oscilla-
tor. The oscillator is biased by a large feedback resistor
and oscillates at the crystal frequency (see Figure 6,
Table 3).
2. An external frequency input that is supplied at the XTAL
input. XTAL is left open (see Figure 5). A typical external
oscillator circuit is shown in Figure 7 in section, “Standby
(Timekeeping) Voltage Operation”.
it is connected to V . In the input/output mode, it is used to
DD
gate the N lines.
IO/MEM - Tied low during memory mapping and high when
the input/output mode of the CDP1800 series microproces-
sor is used.
RD, TPB/WR - Direction Signals - Active signals that deter-
mine data direction flow. In the memory mapped mode, data
is placed on the bus from the counters or status register
when RD pin is active.
Data is transferred to a counter, latch or the control register
when RD is high and TPB/WR is active and latched on the
trailing edge (low to high) of the TPB/WR signal.
In the input/output mode, data is placed on the bus from a
counter or status register when RD is not active between the
trailing edges of TPA and TPB. Data on the bus is written to a
counter, latch, or the control register during TPB when RD is
active and latched on TPB's trailing edge. The following con-
nections are required between the microprocessor and real-
time clock in the CDP1800 series I/O mode.
4-114
CDP1879, CDP1879C-1
TABLE 3. TYPICAL OSCILLATOR CIRCUIT PARAMETERS FOR SUGGESTED OSCILLATOR CIRCUIT, SEE FIGURE 6
PARAMETER
4.197MHz
2.097MHz
1.049MHz
32768Hz (NOTE)
UNITS
MΩ
pF
R
C
C
22
39
5
22
39
5
22
39
5
22
F
0
1
S
39
5
200
pF
R
-
-
-
kΩ
C
-
-
-
91
pF
L
Crystal Impedance
73
200
200
50K (max.)
Ω
NOTE: CDP1879C-1 only.
Design Considerations for Stable Crystal Oscillation
CDP1879
1. Stray capacitances should be minimized for best oscilla-
tor performance. Circuit board traces should be kept to a
maximum of 1 inch, and there should be no parallel
traces.
XTAL PIN 23
PARALLEL
R
C
F
RESONANT
CRYSTAL
2. A signal line or power source line must not cross or go
near the oscillator circuit line.
PIN 22
XTAL
R
S
3. It is advisable to put a 0.1µF capacitor between V
DD
and
C
C
I
L
O
V
of the CDP1879.
SS
FIGURE 6. SUGGESTED OSCILLATOR CIRCUIT APPLIED TO
REAL-TIME CLOCK (SEE TABLE 3)
CDP1879
XTAL PIN 23
EXTERNAL
FREQUENCY
SOURCE
Standby (Timekeeping) Voltage Operation
When any one of the four specified crystals is used with the
on-board oscillator, the Real-Time Clock can operate at a
PIN 22
XTAL
minimum of 4V V . However, at 32kHz the clock will run
DD
(timekeeping only, no device READ/WRITE accesses) down
o
o
o
o
to 3V at -40 C to +85 C and 2.5V at 0 to +70 C.
To achieve this low voltage operation, an external 32kHz clock
source must be supplied at the XTAL input (see Figure 7). The
standby requirements for CHIP SELECT/DESELECT are
listed in Table 4, and Figure 8 indicates the timing waveforms.
Figure 9 illustrates the typical timekeeping curve over the full
temperature range.
FIGURE 5. CONNECTIONS FOR AN EXTERNAL FREQUENCY
SOURCE APPLIED TO REAL-TIME CLOCK
+3V
14
24
23
22 MEG.
1
R
F
200K
L
2
3
5 F
P
22
39 F
R
P
4
1/3 CD54/74HC04
CDP1879
FIGURE 7. TYPICAL EXTERNAL CLOCK-SOURCE CIRCUIT
4-115
CDP1879, CDP1879C-1
STANDBY (TIMEKEEPING) CHARACTERISTICS AT FULL TEMPERATURE RANGE
LIMITS
CDP1879
CDP1879C-1
V
(V)
V
DD
STBY
(V)
PARAMETER
Chip Deselect to Standby
MIN
MAX
MIN
MAX
UNITS
t
t
5
10
2.5, 3
2.5, 3
2
1
-
-
2
-
-
-
CSTBY
(Timekeeping) Voltage Time
µs
Recovery to Normal
Operation Time
5
10
2.5, 3
2.5, 3
2
1
-
-
2
-
-
-
RC
EXTERNAL CLOCK SOURCE OF 32kHz
TYPICAL STANDBY (TIMEKEEPING) VOLTAGE
o
o
3V (-40 C ≤ T ≤ +85 C)
o
o
2.5V (-0 C ≤ T ≤ +70 C
5
4
3
STANDBY
VOLTAGE MODE
0.95 V
DD
0.95 V
DD
V
DD
V
STBY
2
1
t
t
R (NOTE 1)
F (NOTE 1)
t
t
STBY
RC
V
V
V
IH
IH
IL
CS
V
IL
0
NOTE:
-40
-20
0
20
40
60
80
100
o
1. t , t ≥ 1µs
FULL TEMPERATURE RANGE -
C
R
F
FIGURE 9. TYPICAL STANDBY (TIMEKEEPING) VOLTAGE vs
FULL TEMPERATURE RANGE
FIGURE 8. STANDBY (TIMEKEEPING) VOLTAGE AND TIMING
WAVEFORMS
Applications
A typical application for this real-time clock is as a wake-up 4. This Q output signal is received by the CDP1879 as a
control to a CPU to reduce total system power in intermit-
tent-use systems. A hookup diagram illustrating this feature
is shown in Figure 10. In this configuration, the alarm and
power-down features of the CDP1879 are utilized in the con-
trol of the sleep and wake-up states of the CPU. A typical
shut-down/start-up sequence for this system could proceed
as follows:
power-down signal.
5. The CDP1879 three-states the interrupt output pin.
6. The CDP1879 eventually times out, and sets an alarm by
driving the INT output low.
7. The alarm signal resets the CPU (to avoid oscillator start-
up problems) and flags the processor for a warm-start
routine.
1. The CPU has finished a current task and will be inactive
for the next six hours.
8. The CPU, once into its normal software sequence, writes
to the CDP1879 control register to reset the interrupt
request.
2. The CPU loads the CDP1879 alarm registers with the
desired wake-up time.
3. The CDP1800 Q output is set high, which stops the CPU
oscillator (as an alternative, in an NMOS system, power
to all components except the clock chip could be shut off).
4-116
CDP1879, CDP1879C-1
XTAL XTAL
A0
N0
N1
N2
A1
A2
V
XTAL
DD
IO/MEM
CDP1879
PD
XTAL
1/2
CDP1800
CD40107
V
DD
Q
V
DD
1/2
CD40107
V
DD
CLEAR
EFI
INT
FIGURE 10. CPU WAKE-UP CIRCUIT USING THE CDP1879 REAL-TIME CLOCK
XTAL
XTAL
CLEAR
MWR
RESET
TPB/WR
RD
CLOCK
OUT
MRD
TPA
TPA
INTERRUPT
MA0
INTERRUPT
A0
ADDRESS
LINES
MA1
A1
MA2
A2
MA7
CS
IO/MEM
V
SS
CDP1879
DB0 - DB7
MEMORY
CDP1802
DATA BUS
FIGURE 11. TYPICAL CDP1802 MEMORY MAPPED SYSTEM
4-117
CDP1879, CDP1879C-1
LATCH HIGH-ORDER
ADDRESS FOR CS
TPA
HIGH BYTE
LOW BYTE
ADDRESS
TPB/WR
DATA LATCHED
DATA FROM CPU
TO REAL TIME CLOCK
VALID DATA
FIGURE 12. CDP1800 SERIES MEMORY MAPPED WRITE CYCLE TIMING WAVEFORMS
TPA
ADDRESS
RD
HIGH BYTE
LOW BYTE
OUTPUT DRIVERS
ENABLED
DISABLED
DATA FROM
REAL TIME CLOCK
TO CPU
VALID DATA
FIGURE 13. CDP1800 SERIES MEMORY MAPPED READ CYCLE TIMING WAVEFORMS
XTAL
XTAL
CLEAR
RESET
TPA
CLOCK
OUT
TPA
MRD
RD
TPB
TPB/WR
INTERRUPT
A0
INTERRUPT
N0
N1
N2
ADDRESS
LINES
A1
A2
IO/MEM
CS
V
DD
CDP1879
DB0 - DB7
MEMORY
CDP1802
FIGURE 14. TYPICAL CDP1802 INPUT/OUTPUT MAPPED SYSTEM
4-118
CDP1879, CDP1879C-1
TPA
RD
N LINES
TPB/WR
DATA LATCHED
DATA FROM MEMORY
TO REAL-TIME CLOCK
VALID DATA
FIGURE 15. CDP1800 SERIES INPUT/OUTPUT MAPPING TIMING WAVEFORMS WITH OUTPUT INSTRUCTION
OUTPUT DRIVERS ENABLED
TPA
RD
OUTPUT DRIVERS
DISABLED
TPB/WR
N LINES
DATA FROM
REAL-TIME CLOCK
TO MEMORY
VALID DATA
FIGURE 16. CDP1800 SERIES INPUT/OUTPUT MAPPING TIMING WAVEFORMS WITH INPUT INSTRUCTION
o
o
Dynamic Electrical Specifications at T -40 C to +85 C, Input t , t = 10ns, C = 50pF
A
R
F
L
LIMITS
CDP1879
(NOTE 1)
CDP1879C-1
(NOTE 1)
V
DD
PARAMETER
Read Cycle Times (See Figure 17)
Data Access from Address
(V)
MIN
MAX
MIN
MAX
UNITS
t
t
t
t
t
t
5
10
5
-
-
400
-
400
DA
RD
DR
RH
DH
CS
190
-
-
Read Pulse Width
Data Access from Read
Address Hold after Read
Output Hold after Read
Chip Select Setup to TPA
NOTE:
270
160
-
-
270
-
10
5
-
375
170
-
-
-
-
375
10
5
-
-
-
ns
0
0
-
-
10
5
0
-
-
50
40
50
30
230
130
-
50
-
230
10
5
-
-
-
50
-
10
-
1. Time required by a limit device to allow for the indicated function.
4-119
CDP1879, CDP1879C-1
TPA
t
CS
t
RH
ADDRESS/CHIP SELECT
t
RD
READ
DATA TO CPU
t
DR
t
t
DA
DH
FIGURE 17. READ CYCLE TIMING WAVEFORMS
o
o
Dynamic Electrical Specifications at T -40 C to +85 C, Input t , t = 10ns, C = 50 pF
A
R
F
L
LIMITS
CDP1879
(NOTE 1)
CDP1879C-1
(NOTE 1)
V
DD
PARAMETER
Write Cycle Times (See Figure 18)
Address Setup to Write
(V)
MIN
MAX
MIN
MAX
UNITS
t
t
t
t
t
t
5
10
225
110
-
-
225
-
-
-
AS
Write Pulse Width
Data Setup to Write
Address Hold after Write
Data Hold after Write
Chip Select Setup to TPA
NOTE:
5
10
150
70
-
-
150
-
-
-
WR
DS
AH
WH
CS
5
10
65
30
-
-
65
-
-
-
ns
5
10
0
0
-
-
0
-
-
-
5
10
150
80
-
-
150
-
-
-
5
10
50
30
-
-
50
-
-
-
1. Time required by a limit device to allow for the indicated function.
4-120
CDP1879, CDP1879C-1
TPA
t
CS
t
AH
ADDRESS/CHIP SELECT
t
t
WR
AS
WRITE
DATA TO REAL-TIME CLOCK
t
t
WH
DS
FIGURE 18. WRITE CYCLE TIMING WAVEFORM
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
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