D2-92634-LR_技术文档

Intelligent Digital Amplifier and Sound Processor

D2-926xx

Features

The D2-926xx family of the DAE-3™ and DAE-3HT™ Digital

Audio Engine™ devices are complete System-on Chip (SoC)

multi-channel digital sound processors and Class-D amplifier

controllers.

• Advanced DAE-3™ Digital Audio Engine™ IC Family

- DAE-3™ Pin Compatible and Function/Feature

Compatible with the D2Audio™ DAE-6™ Device Family

- DAE-3HT™ - Identical DAE-3 performance, in

72-QFN package

The integrated DSP provides efficient and configurable audio

signal path processing including equalization, dynamic range

compression, mixing, and filtering that is completely

• Integrated DSP Digital Sound Processing

- Customizable audio path sound processing

configurable via the Audio Canvas™ III high level programming

interface. The integrated PWM engine supports programmable

and dynamic control of audio output, enabling a variety of

multi-channel output configurations and output power

capacity. Internal noise shaping, an embedded asynchronous

sample rate converter, dynamic level-dependent timing, and

high resolution operation supports power stage audio

performances with SNR >110dB and THD+N < 0.01%.

- Fully configurable and routable audio signal paths and

hardware function assignment

- Fully Supported with Audio Canvas™ III Design Tool

• Flexible Audio Input and Output Configurations

- 12 Independent PWM Engine Channels

2

- 4 Independent Asynchronous I S Digital Inputs

- Integrated high-performance stereo ADC (DAE-3 only)

The D2-926xx devices are provided in two package and feature

configurations which include the 128-pin DAE-3, and the72-pin

DAE-3HT. Both the DAE-3 and DAE-3HT provide identical

performance and enable an extremely flexible platform for

feature rich and cost-affordable quality audio solutions, which

benefit from the addition of Class-D amplifiers and DSP audio

processing.

- S/PDIF™ Digital Audio Inputs supporting

Linear IEC-61958 PCM or Compressed IEC-61937 Audio

- S/PDIF Digital Audio PCM Output

• Embedded 8-Channel Sample Rate Converter

• Real-Time Amplifier Control and Monitoring

- Supports Bridged, Half-Bridged, and Bridge-Tied Load (BTL)

Topologies, Using Discrete or Integrated Power Stages

The 12 integrated digital PWM controllers can be used in a

variety of multi-channel audio system configurations,

supporting powered as well as line outputs. Fully protected

amplifier control provides efficient and clean Class-D power

output support.

- Complete Fault Protection with Automatic Recovery

• D2Audio™ SoundSuite™ Enhancement and Virtualization

• Enhanced Audio Processing Decoders And Virtualization

- Dolby^®Digital/AC3

- Dolby^®Pro Logic IIx

Applications

• DTV and Blu-ray Soundbar

- Dolby^®Virtual Speaker

• DVD and Blu-ray Home Theater Systems

• Home Theater in a Box (HTiB)

• Audio Video Receiver (AVR)

- SRS TruSurround HD4™ , SRS WOW HD™,

SRS TruVolume™

• Multi-Channel Multi-Media (MM) Systems

• Multi-Room Distributed Audio (MRDA)

• Powered Speaker Systems

• Automotive Trunk/Amplified Solutions

July 12, 2012

FN6787.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

1

Dolby is a registered trademark of Dolby Laboratories. All other trademarks mentioned are the property of their respective owners.

D2-926xx

Ordering Information

PART

NUMBER

(Note 2)

AUDIO PROCESSING

FEATURE SET SUPPORT

(Note 1)

DAE DEVICE

FAMILY

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

D2-92633-LR

D2-92634-LR

D2-92683-QR

D2-92684-QR

DAE-3

D2-92633-LR

D2-92634-LR

D2-92683-QR

D2-92684-QR

Refer to Table 1

-10 to +85

128 Ld LQFP

72 Ld QFN

Q128.14x14

L72.10x10F

DAE-3HT

72 Ld QFN

NOTES:

1. The D2-926xx devices support multiple audio processing algorithms and decoders, and support is device-dependent. Refer to Table 1 for the

supported features for each device part number.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN6787.2

July 12, 2012

2

D2-926xx

DAE-3 Device Feature Set Offering

The D2-926xx family has specific part numbers to specify the features and algorithms supported in the device. All devices of the DAE-3

family include 8 audio input processing channels, up to 12 PWM output channels, an embedded 8-channel Sample Rate Converter

(SRC), and are fully supported with the Audio Canvas III™ design tool software. Additional features within each DAE-3 family part

number are shown in Table 1.

TABLE 1. DAE-3 DEVICE PART NUMBERS AND FEATURES

PART NUMBER

D2-92633-LR

DAE FAMILY

DAE-3

FEATURES

8 Channels of I S or Left Justified Serial Digital Audio Inputs

LICENSED ALGORITHM SUPPORT (Note 3)

2

D2Audio™ SoundSuite™

SRS TruSurround HD4™,

SRS WOWHD4™,

2

128-Pin Package 8 Channels of I S or Left Justified Serial Digital Audio Outputs

2 S/PDIF Digital Inputs

1 S/PDIF Digital Output

SRS TruVolume™

2 ADC Analog Audio Inputs

2

®

D2-92634-LR

D2-92683-QR

D2-92684-QR

DAE-3

8 Channels of I S or Left Justified Serial Digital Audio Inputs

Dolby Digital/AC3 Decode Processing

2

®

128-Pin Package 8 Channels of I S or Left Justified Serial Digital Audio Outputs

2 S/PDIF Digital Inputs

Dolby Pro Logic IIx Surround Processing

®

Dolby Virtual Speaker Processing

1 S/PDIF Digital Output

2 ADC Analog Audio Inputs

2

DAE-3HT

8 Channels of I S or Left Justified Serial Digital Audio Inputs, or

D2Audio™ SoundSuite™

72-Pin Package 6 Channels of I S or Left Justified Serial Digital Audio Inputs plus SRS TruSurround HD4™,

2

2 Channels of I S or Left Justified Serial Digital Audio Outputs

1 S/PDIF Digital Input

SRS WOWHD4™,

SRS TruVolume™

1 S/PDIF Digital Output

2

®

DAE-3HT

8 Channels of I S or Left Justified Serial Digital Audio Inputs, or 6 Dolby Digital/AC3 Decode Processing

2

®

72-Pin Package Channels of I S or Left Justified Serial Digital Audio Inputs plus 2 Dolby Pro Logic IIx Surround Processing

2

®

Channels of I S or Left Justified Serial Digital Audio Outputs

Dolby Virtual Speaker Processing

1 S/PDIF Digital Input

1 S/PDIF Digital Output

NOTE:

3. All DAE-3 family devices support D2Audio™ SoundSuite™ Audio Processing algorithms, and with license agreements executed with SRS Labs, also

support SRS TruSurround HD4™, SRS WOW HD™, and SRS TruVolume™

Device Designations

This datasheet applies to all of the DAE-3 device family, which includes both the DAE-3 and DAE-3HT. Functional specifications apply to

both designations of this family unless otherwise indicated.

Throughout this document the device names apply to all part numbers of their respective names as follows:

DAE DEVICE NAME

DAE-3

DAE DEVICE PART NUMBERS

D2-92633-LR, D2-92634-LR

D2-92683-QR, D2-92684-QR

PACKAGE PINS

128-Pin Package

72-Pin Package

DAE-3HT

FN6787.2

July 12, 2012

3

D2-926xx

Table of Contents

DAE-3 Device Feature Set Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Device Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Audio Interface Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2

Two-Wire (I C) Interface Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SPI™ Interface Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Configuration DAE-3 (128-Pin Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin Configuration DAE-3HT (72-Pin Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Pin Description, DAE-3 (128-Pin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Pin Description DAE-3HT (72-Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Functional Block Diagram - DAE-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Functional Block Diagram - DAE-3HT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

DAE-3 Device Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Audio Canvas III Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Sample Rate Converters (SRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Serial Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Serial Digital Audio Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Serial Digital Audio Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

S/PDIF Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

S/PDIF Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

S/PDIF Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

ADC input (DAE-3 Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

PWM Audio Amplifier Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Amplifier Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Graceful Overcurrent And Short Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Hardware I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

General-purpose I/O And Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Power Supply Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clocks And PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Booting and Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Control Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2

I C 2-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Serial Peripheral Interface (SPI™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reading and Writing Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Audio Processing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Input Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Shared Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Stereo A/B Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Tone Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

FN6787.2

July 12, 2012

4

D2-926xx

Parametric Equalizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Biquad Filter (Frequency Domain Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Biquad Filter (z-Domain Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Filter - Crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Excursion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Compressor/Expander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Envelope Voltage Controlled Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Reverb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chime Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

RMS Level Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Fade-Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Mono Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Dither Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Harmonics Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SoundSuite™ Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Third Party Virtualization and Enhancements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Audio Processing Block Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Dynamic Register Addressing Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Hardware Feature Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

AM Avoidance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

MCLK Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PSSYNC Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Audio I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Fault Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Decoder Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Format Change Notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Idle Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Master Volume Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PWM Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PWM Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Power Down Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Temperature Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DAE-3 And DAE-3HT Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Pin Function Mapping Between Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

I/O Pin Function Assignment Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

PWM Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

I2S Digital Inputs And Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Protection Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Q128.14x14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

L72.10x10F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FN6787.2

July 12, 2012

5

D2-926xx

Absolute Maximum Ratings (Note 8)

Thermal Information

Supply Voltage

Thermal Resistance (Typical)

128 Ld LQFP Package (Notes 4, 6) . . . . . .

72 Ld QFN Package (Notes 5, 7) . . . . . . . .

Maximum Storage Temperature. . . . . . . . . . . . . . . . . . . . -55°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

θ

(°C/W)

39

22

θ

(°C/W)

6.5

0.80

JA

JC

RVDD, PWMVDD, ADCVDD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V

CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V

Input Voltage

Any Input but XTALI . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to RVDD +0.3V

XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V

Input Current, Any Pin but Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA

ESD Rating

Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2000V

Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 200V

Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . 750V

Latch-up

(Pins 2, 4, 6, 7, 8, 9, 37 (72 Ld Package only) Tested per JESD78D

Class II, Level B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA

(All Other pins Tested per JESD78D Class II, Level A) . . . . . . . . . 100mA

Recommended Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C

Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3V

Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V

Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

5. θ is measured with the component mounted on a high effective thermal conductivity test board with direct attach of exposed pad to PCB.

JA

6. For θ , the “case temp” location is taken at the package top center.

JC

7. For θ , the “case temp” is measured on bottom of exposed pad.

JC

8. Absolute Maximum parameters are not tested in production.

Electrical Specifications

T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages

A

referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are

measured in full power down configuration.

TEST

MIN

MAX

SYMBOL

PARAMETER

Digital Input High Logic Level (Note 9)

Digital Input Low Logic Level (Note 9)

High Level Output Drive Voltage

CONDITIONS

(Note 12)

TYP

(Note 12)

UNIT

V

Relative to RVDD

2.0

-

0.8

-

V

IH

V

-

IL

V

RVDD - 0.4

OH

I

at - Pin Drive Strength Current. See “Pin Description, DAE-3 (128-

OUT

Pin)” on page 13, and “Pin Description DAE-3HT (72-Pin)” on page 18

V

Low Level Output Drive Voltage

-

0.4

V

OL

I

at + Pin Drive Strength Current. See “Pin Description, DAE-3 (128-

OUT

Pin)” on page 13, and “Pin Description DAE-3HT (72-Pin)” on page 18

High Level Input Drive Voltage XTALI Pin

Low Level Input Drive Voltage XTALI Pin

Input Leakage Current (Note 10)

VIHX

VILX

0.7

-

PLLVDD

V

-

0.3

I

-

±10

µA

pF

V

IN

C

Input Capacitance

-

9

-

IN

VOHO

VOLO

High Level Output Drive Voltage OSCOUT Pin

Low Level Output Drive Voltage OSCOUT Pin

Output Capacitance

PLLVDD - 0.3

-

0.3

V

C

-

9

-

pF

ns

V

OUT

t

nRESET Pulse Width

-

10

3.3

10

<1

3.3

5

-

RST

R

Typical Digital I/O Pad Ring Supply

(Voltage)

(Current, Active)

(Current, Power-down)

(Voltage)

3.0

3.6

VDD

-

mA

V

-

PWM

VDD

Typical PWM I/O Pad Ring Supply

3.0

3.6

(Current, Active)

(Current, Power-down)

-

mA

<1

FN6787.2

July 12, 2012

6

D2-926xx

Electrical Specifications

T

= +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages

A

referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are

measured in full power down configuration. (Continued)

TEST

MIN

MAX

SYMBOL

CVDD

PARAMETER

CONDITIONS

(Note 12)

TYP

1.8

300

15

(Note 12)

UNIT

V

Typical Core Supply

(Voltage)

(Current, Active)

(Current, Power-down)

(Voltage)

1.7

1.9

-

mA

V

-

PLLVDD Typical PLL Analog Supply

1.7

1.8

25

1.9

(Current, Active)

(Current, Power-down)

(Voltage)

-

mA

V

-

3.0

-

10

-

3.6

-

ADCVDD Typical ADC Analog Supply

CRYSTAL OSCILLATOR

3.3

12

(Current, Active, Power-Down)

mA

Xo

Crystal Frequency (Fundamental Mode Crystal)

20

24.576

24.822

MHz

(24.576 + 1%)

Dt

Duty Cycle

40

-

60

20

%

t

Start-up Time (Start-up Time is Oscillator Enabled

(with Valid Supply) to Stable Oscillation)

5

ms

START

PLL

F

VCO Frequency

80.00

20

294.912

-

297.86

MHz

VCO

F

Input Reference Frequency

24.822

IN

(24.576 + 1%)

Feedback Dividers (Integer)

4

-

12

2

15

-

PLL Lock Time from any Input Change

ms

1.8V POWER-ON RESET

V

Reset Enabled Voltage Level

0.9

1.1

150

5

1.4

500

-

V

EN

t

POR Pulse Width Rejection (Note 12)

POR Minimum Output Pulse Width

-

µs

REJ

t

DIS

1.8V BROWNOUT DETECTION

Detect Level

1.4

20

1.5

100

-

1.6

V

t

Pulse Width Rejection

-

ns

BOD1

t

Minimum Output Pulse Width

O1

3.3V BROWNOUT DETECTION

Detect Level

2.5

20

2.7

100

-

2.9

V

t

Pulse Width Rejection

-

ns

BOD3

t

Minimum Output Pulse Width

O3

ADC PERFORMANCE SPECIFICATIONS (DAE-3 only)

V

ADCREF DC Level

1.3

-

1.4

1.5

V

µA

V

REF

I

ADCREF Load Current

Analog Input Level

-

±20

REF

V

- 0.6

V

+ 0.6

REF

AIN

REF

ADC Dynamic Range & SNR (Note 13)

1.0 V

1kHz

-

94

-

dB

P-P

(ADC + ADC Decimator performance only, DSP inactive, no digital sine wave input

audio processing, PWM outputs off, no pPWM switching)

reference level,

using firmware

from Audio

Canvas III™ rev

3.1.4 or newer.

ADC Dynamic Range & SNR (Note 13)

-

83

-

dB

(DSP active and processing audio data, PWM active and driving

audio outputs, measurements using typical system-level amplifier

equivalent as measurement environment)

FN6787.2

July 12, 2012

7

D2-926xx

Electrical Specifications

T

= +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages

A

referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are

measured in full power down configuration. (Continued)

TEST

MIN

MAX

SYMBOL

PARAMETER

CONDITIONS

(Note 12)

TYP

-80

0.1

-80

-70

(Note 12)

UNIT

dB

THD+N

-

Gain Mismatch

Crosstalk

dB

Power Supply Rejection

dB

NOTES:

9. All input pins except XTALI.

10. Input leakage applies to all pins except XTALO.

11. Power-down is with device in reset and clocks stopped.

12. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

13. Analog performance is system-design dependent and is affected by factors that include PCB layout, shielding and routing of analog traces, additional

components within the analog input path, and power supply isolation.

Serial Audio Interface Port Timing (Figure 1) T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All

A

grounds at 0.0V. All voltages referenced to ground.

MIN

MAX

SYMBOL

tc

DESCRIPTION

SCKRx Frequency - SCKR0, SCKR1

(Note 12)

TYP

(Note 12)

UNIT

MHz

ns

12.5

SCLK

tw

SCKRx Pulse Width (High and Low) - SCKR0, SCKR1

LRCKRx Setup to SCLK Rising - LRCKR0, LRCKR1

LRCKRx Hold from SCLK Rising - LRCKR0, LRCKR1

SDINx Setup to SCLK Rising - SDIN0, SDIN1

SDINx Hold from SCLK Rising - SDIN0, SDIN1

SDOUTx Delay from SCLK Falling

40

20

SCLK

LRCLK

ts

ns

th

ns

ts

SDI

ns

th

SDI

ns

t

20

ns

dSDO

t SCLK

w

c

SCKRx

t LRCLK

t

SCLK

h

w

LRCLKRx

t LRCLK

t SDI

s

SDINx

t SDI

t SDO

h

d

SDOUTx

FIGURE 1. SERIAL AUDIO INTERFACE PORT TIMING

FN6787.2

July 12, 2012

8

D2-926xx

2

Two-Wire (I C) Interface Port Timing (Figure 2) T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All

A

grounds at 0.0V. All voltages referenced to ground.

MIN

MAX

SYMBOL

DESCRIPTION

(Note 12)

UNIT

kHz

µs

f

SCL Frequency

100

SCL

t

Bus Free Time Between Transmissions

SCL Clock Low

4.7

4.0

4.7

4.0

0

buf

tw

µs

lowSCLx

tw

SCL Clock High

µs

highSCLx

ts

Setup Time For a (Repeated) Start

Start Condition Hold Time

µs

STA

th

µs

STA

th

SDA Hold From SCL Falling (Note 14)

SDA Setup Time to SCL Rising

SDA Output Delay Time From SCL Falling

Rise Time of Both SDA and SCL

Fall Time of Both SDA and SCL

Setup Time For a Stop Condition

µs

SDAx

ts

250

ns

td

3.5

1

µs

t

µs

r

f

t

300

ns

ts

STO

4.7

µs

NOTE:

14. Data must be held sufficient time to bridge the 300ns transition time of SCL.

t

SCLx

whigh

t

R

F

t

SCLx

wlow

SCLx

t STA

s

t SDAx

t STO

h

s

t

tsSDAx

BUF

SDAx (INPUT)

t STAx

h

SDAx (OUTPUT)

t SDAx

d

2

FIGURE 2. I C INTERFACE TIMING

FN6787.2

July 12, 2012

9

D2-926xx

SPI™ Interface Port Timing (Figure 3) T = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V.

A

All voltages referenced to ground.

MIN

MAX

SYMBOL

DESCRIPTION

(Note 12)

UNIT

SPI MASTER MODE TIMING

t

MOSI Valid From Clock Edge

MISO Setup to Clock Edge

MISO Hold From Clock Edge

nCS Minimum Width

8

ns

V

S

H

t

2

3

t

3 system clocks

+ 2ns

WI

SPI SLAVE MODE TIMING

t

MISO Valid From Clock Edge

MOSI Setup to Clock Edge

MOSI Hold From Clock Edge

nCS Minimum Width

8

ns

V

S

H

t

2

3

t

3 system clocks

+ 2ns

WI

SCK (CPHA = 1, CPOL = 0

SCK (CPHA = 0, CPOL = 0

t

V

MOSI

t

H

t

S

MISO (CPHA = 0

nCS

t

WI

FIGURE 3. SPI TIMING

FN6787.2

July 12, 2012

10

D2-926xx

Pin Configuration DAE-3 (128-Pin Package)

D2-92633, D2-92634

(128 LD LQFP)

TOP VIEW

SC20

SRD2

SC21

SCK2

STD2

SC22

MCLK

SCK3

STD3

SC32

SC30

SC31

SRD3

STD0

SCK0

CVDD

CGND

RGND

RVDD

SRD0

SC00

SC01

SC02

SCK

1

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

PWMVDD

PWM0

2

3

PWM1

4

PWM2

5

PWM3

6

PWMGND

PWMVDD

PWM4

7

8

9

PWM5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

PWM6

PWM7

PWMGND

PWMVDD

PWM8

PWM9

PWM10

PWM11

PWM12

PWM13

PWMGND

PWMVDD

PWM14

PWM15

PWM16

PWM17

PWMGND

CVDD

TIO1

MISO

MOSI

GPIO7

GPIO3

GPIO2

CGND

RGND

RVDD

GPIO1

PROTECT2

FN6787.2

July 12, 2012

11

D2-926xx

Pin Configuration DAE-3HT (72-Pin Package)

D2-92683, D2-92684

(72 LD QFN)

TOP VIEW

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

1

2

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

SCLK3 (SC20)

SDIN3 (SRD2)

LRCK3 (SC21)

SCLK4 (SCK2)

SDIO4 (STD2)

LRCK4 (SC22)

SCLK12 (SCK3)

SDIN2 (STD3)

LRCK12 (SC32)

SDIN1 (SRD3)

CVDD

PWM0

PWM1

PWM2

PWM3

PWMGND

PWM4

PWM5

PWM6

PWM7

PWM8

PWM9

PWM10

PWM11

CVDD

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

CGND

RGND

RVDD

SCK

CGND

TIO1/NTC

MISO

RGND

RVDD

MOSI

PROTECT2

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

NOTE:

15. All pins pass Jedec II 100mA @ +85°C, with exception of pins 2, 4, 6, 7, 8, 9, 37, which pass 50mA @ +85°C

FN6787.2

July 12, 2012

12

D2-926xx

Pin Description, DAE-3 (128-Pin)

NAME

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

PIN (Note 16) TYPE

DESCRIPTION

2

1

2

3

4

5

6

7

SC20

SRD2

SC21

SCK2

STD2

SC22

MCLK

I/O

O

3.3

8

4

Serial Audio Interface 2, I S0 SCLK

2

Serial Audio Interface 2, I S0 SDIN

2

8

Serial Audio Interface 2, I S0 LRCK

2

8

Serial Audio Interface 2, I S1 SCLK

2

8

Serial Audio Interface 2, I S1 SDIN

2

4

Serial Audio Interface 2, I S1 LRCK

2

16

I S Serial Audio Master Clock output for external ADC/DAC components, drives low on reset and

is enabled by firmware assignment.

2

8

SCK3

STD3

SC32

SC30

SC31

SRD3

STD0

SCK0

CVDD

CGND

RGND

RVDD

I/O

P

3.3

8

4

8

Serial Audio Interface 3, I S3 SCLK

2

9

Serial Audio Interface 3, I S3 SDIN

2

10

11

12

13

14

15

16

17

18

19

20

21

Serial Audio Interface 3, I S3 LRCK

2

Serial Audio Interface 3, I S2 SCLK

2

Serial Audio Interface 3, I S2 LRCK

2

Serial Audio Interface 3, I S2 SDIN

2

Serial Audio Interface 0, I S SDAT0

2

Serial Audio Interface 0, I S LRCK0

Core power, 1.8V

P

Core power, 1.8V

P

Core ground

P

Core ground

P

Digital pad ring ground. Internally connected to PWMGND.

P

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. Internally connected to PWMVDD.

22

23

24

25

26

27

SRD0

SC00

SC01

SC02

SCK

I/O

3.3

4

8

Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware.

2

8

Serial Audio Interface 0, I S SDAT1

2

8

Serial Audio Interface 0, I S LRCK1

4

SPI clock I/O with hysteresis input.

TIO1

16

Timer I/O port 1. Operation and assignment is controlled by firmware. Leave unconnected when

not in use.

28

29

30

MISO

MOSI

GPIO7

I/O

3.3

4

SPI master input, slave output data signal.

SPI master output, slave input data signal.

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

31

32

33

GPIO3

GPIO2

GPIO4

I/O

3.3

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

FN6787.2

July 12, 2012

13

D2-926xx

Pin Description, DAE-3 (128-Pin)(Continued)

NAME

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

PIN (Note 16) TYPE

DESCRIPTION

34

35

36

37

GPIO5

GPIO6

SDA1

SCL1

I/O

3.3

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

8 - OD

4

Two-Wire Serial data port 1. Bidirectional signal used by both the master and slave controllers for

data transport.

Two-Wire Serial clock port 1. Bidirectional signal is used by both the master and slave controllers

for clock signaling.

38 PROTECT9 I/O

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

39 SPDIFRX1

40 SPDIFRX0

I

3.3

S/PDIF Digital audio data input 1

S/PDIF Digital audio data input 0

41

SPDIFTX

O

4

S/PDIF Digital audio output. (Audio content and audio processing signal flow is dependent upon

firmware, driving stereo output up to 192kHz.)

42

43

TEST

IRQA

I

3.3

Factory test use only. Must be tied low.

Interrupt request port A, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to

ground and High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

44

45

46

47

IRQB

IRQC

IRQD

TIO2

I

3.3

Interrupt request port B, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to

ground and High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

I

Interrupt request port C, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to

ground and High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

Interrupt request port D, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to

ground and High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

I/O

16

Timer I/O port 2. Operation and assignment is controlled by firmware. Leave unconnected when

not in use.

48

49

50

51

52

53

CVDD

CGND

RGND

RVDD

P

3.3

Core power, 1.8V

Core ground

Digital pad ring ground. Internally connected to PWMGND.

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. Internally connected to PWMVDD.

54

55

56

PUMPHI

PUMPLO

PSSYNC

I/O

3.3

16

Assignable I/O. Function and operation defined by firmware.

Synchronizing output signal to switching power supply. (Operates under specification of firmware

and resets to high impedance inactive state when not used.)

57

58

PSTEMP

PSCURR

I/O

3.3

4

Assignable I/O. Function and operation defined by firmware.

PWM synchronization port. (Function and operation is defined by firmware.)

59 PWMSYNC I/O

60 PROTECT3 I/O

16

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

FN6787.2

July 12, 2012

14

D2-926xx

Pin Description, DAE-3 (128-Pin)(Continued)

NAME

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

PIN (Note 16) TYPE

DESCRIPTION

61 PROTECT4 I/O

62 PROTECT5 I/O

63 PROTECT6 I/O

64 PROTECT7 I/O

65 PROTECT2 I/O

3.3

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

66

67

GPIO1

RVDD

I/O

P

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. Internally connected to PWMVDD.

68

69

70

71

72

RGND

CGND

P

3.3

Digital pad ring ground. Internally connected to PWMGND.

Core ground

CVDD

P

Core power, 1.8V

PWMGND

PWM17

P

PWM output pin ground. Internally connected to RGND.

I/O

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

73

74

75

76

PWM16

PWM15

PWM14

PWMVDD

I/O

P

3.3

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to

RVDD.

77

78

PWMGND

PWM13

P

3.3

PWM output pin ground. Internally connected to RGND.

I/O

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

79

80

81

82

83

84

PWM12

PWM11

PWM10

PWM9

I/O

P

3.3

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM8

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWMVDD

PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to

RVDD.

85

86

PWMGND

PWM7

P

3.3

PWM output pin ground. Internally connected to RGND.

I/O

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

FN6787.2

July 12, 2012

15

D2-926xx

Pin Description, DAE-3 (128-Pin)(Continued)

NAME

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

PIN (Note 16) TYPE

DESCRIPTION

87

88

89

90

PWM6

I/O

P

3.3

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM5

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM4

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWMVDD

PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected

to RVDD.

91

92

PWMGND

PWM3

P

3.3

PWM output pin ground. Internally connected to RGND.

I/O

8 or 16

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

93

94

95

96

97

PWM2

PWM1

I/O

P

3.3

1.8

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM0

PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWMVDD

OSCOUT

PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to

RVDD.

P

Analog oscillator output to slave D2-926xx devices. OSCOUT drives a buffered version of the

crystal oscillator signal from the XTALI pin.

98

99

PLLAGND

PLLTESTB

P

O

P

1.8

PLL Analog ground

Factory test use only. Must be tied low.

100 PLLTESTA

101

XTALI

Crystal oscillator analog input port. An external clock source would be driven into the this port. In

multi-D2-926xx systems, the OSCOUT from the master D2-926xx would drive the XTALI pin.

102

XTALO

P

1.8

Crystal oscillator analog output port. When using an external clock source, this pin must be open.

XTALO does not have a drive strength specification.

103 PLLAVDD

P

I

1.8

3.3

PLL Analog power, 1.8V

104

105

106

107

ADCVDD

AIN1

Analog power for internal ADC, 3.3V

Analog input 1 to internal ADC

ADCREF

AIN0

O

I

Analog voltage reference output. Must be de-coupled to analog ground with 1µF capacitor.

Analog input 0 to internal ADC

108 ADCGND

P

I

Analog ground for internal ADC

109

110

111

nTRST

nCS

Factory test only. Must be tied high at all times.

SPI slave select I/O.

I/O

P

4

RVDD

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. Internally connected to PWMVDD.

112

113

114

115

116

RGND

CGND

CVDD

SC12

SC11

P

3.3

Digital pad ring ground. Internally connected to PWMGND.

Core ground

P

Core power, 1.8V

I/O

8

Serial Audio Interface 1, LRCK

Serial Audio Interface 1, SDAT3

FN6787.2

July 12, 2012

16

D2-926xx

Pin Description, DAE-3 (128-Pin)(Continued)

NAME

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

PIN (Note 16) TYPE

DESCRIPTION

Serial Audio Interface 1, data (Assignment by firmware control.)

Serial Audio Interface 1, SDAT2

117

118

119

120

SC10

STD1

SCK1

SRD1

I/O

O

3.3

8

4

Serial Audio Interface 1, SCK

Serial Audio Interface 1, data (Assignment by firmware control.)

121 nRSTOUT

16 - OD

Active low open drain reset output. Pin drives low from POR generator, 3.3V brownout detector

going active, or from 1.8V brownout detector going active. This output should be used to initiate a

system reset to the nRESET pin upon brownout event detection.

122

123

nRESET

TIO0

I

3.3

Active low reset input with hysteresis. Activates system level reset when pulled low, initializing all

internal logic and program operations. System latches boot mode selection of the IRQ input pins

on the rising edge.

I/O

3.3

16

4

Timer I/O port 0. Operation and assignment is controlled by firmware. Leave unconnected when

not in use.

124 PROTECT1 I/O

125 PROTECT0 I/O

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

4

PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and channel

assignment is defined by firmware.)

126

127

GPIO0

SDA0

SCL0

I/O

16

General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and

assignment is defined by product application's firmware.)

8 - OD

Two-Wire Serial data port 0. Bidirectional signal used by both the master and slave controllers for

data transport.

128

Two-Wire Serial clock port 0. Bidirectional signal is used by both the master and slave controllers

for clock signaling.

NOTES:

16. Unless otherwise specified, all pin names are active high. Those that are active low have an “n” prefix.

17. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be tied together, CGND pins

to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) CGND and RGND are to be tied together on board. RGND and

PWMGND pins are also internally connected and are to be tied together.

FN6787.2

July 12, 2012

17

D2-926xx

Pin Description DAE-3HT (72-Pin)

NAME

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

PIN (Note 16) TYPE

DESCRIPTION

2

1

2

3

4

SCLK3

(SC20)

In

3.3

8

4

8

Bit clock, I S port 3, audio input channels 5-6. (I S port 3 is 1 of 3 input-only ports, providing

channels 5-6 input audio content.)

2

SDIN3

(SRD2)

Audio data, I S port 3, audio input channels 5-6 (I S port 3 is 1 of 3 input-only ports, providing

channels 5-6 input audio content.)

2

LRCK3

(SC21)

L/R clock, I S port 3, audio input channels 5-6 (I S port 3 is 1 of 3 input-only ports, providing

channels 5-6 input audio content.)

2

SCLK4

(SCK2)

Bit clock, I S port 4, audio input channels 7-8, or audio output channels 1-2. (I S port 4 is either

an I S input port, or and I S output port. Selection of input or output is defined by firmware. When

used as input, port 4 provides channel 7-8 input audio content. When used as an output, port 4

2

provides the 2 channels of I S output audio.)

2

5

6

SDIO4

(STD2)

I/O

In

3.3

8

4

Audio data, I S port 4, input channels 7-8, or output channels 1-2. (I S port 4 is either an I S input

2

port, or and I S output port. Selection of input or output is defined by firmware. When used as

input, port 4 provides channel 7-8 input audio content. When used as an output, port 4 provides

the 2 channels of I S output audio.)

2

LRCK4

(SC22)

L/R clock, I S port 4, audio input channels 7-8, or audio output channels 1-2. (I S port 4 is either

2

an I S input port, or and I S output port. Selection of input or output is defined by firmware. When

used as input, port 4 provides channel 7-8 input audio content. When used as an output, port 4

provides the 2 channels of I S output audio.)

2

7

8

SCLK12

(SCK3)

In

3.3

8

Bit clock, I S ports 1 & 2, audio input channels 1-4 (I S ports 1 & 2 are 2 of the 3 input-only ports,

providing channels 1-4 input audio content.)

2

SDIN2

(STD3)

Audio data, I S port 2, audio input channels 3-4 (I S ports 1 & 2 are 2 of the 3 input-only ports,

providing channels 1-4 input audio content.)

2

9

LRCK12

(SC32)

L/R clock, I S ports 1 & 2, audio input channels 1-4 (I S ports 1 & 2 are 2 of the 3 input-only ports,

providing channels 1-4 input audio content.)

2

10

SDIN1

(SRD3)

Audio data, I S port 1, audio input channels 1-2 (I S ports 1 & 2 are 2 of the 3 input-only ports,

providing channels 1-4 input audio content.)

11

12

13

14

CVDD

CGND

RGND

RVDD

P

G

P

3.3

Core power, 1.8V

Core ground

Digital pad ring ground. Internally connected to PWMGND.

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers, except for the analog pads. Internally connected to PWMVDD.

15

16

SCK

I/O

3.3

4

SPI clock I/O with hysteresis input.

TIO1/NTC

16

Timer I/O port 1, or assignable NTC temperature sensing common I/O. Operation and assignment

is controlled by firmware. Leave unconnected when not in use.

17

18

19

MISO

MOSI

SDA1

I/O

3.3

4

SPI master input, slave output data signal.

SPI master output, slave input data signal.

2

8 - OD

Two-Wire Serial (I C) data port 1. Primary control interface data signal used for device boot and

control. Bidirectional port for both master and slave controllers operation.

2

20

SCL1

I/O

3.3

8 - OD

Two-Wire Serial (I C) clock port 1. Primary control interface clock signal used for device boot and

control. Bidirectional port for both master and slave controllers operation.

21

22

SPDIFRX

SPDIFTX

In

O

3.3

S/PDIF Digital audio data input

S/PDIF Digital audio output. (Audio content and audio processing signal flow is dependent upon

firmware, driving stereo output up to 192kHz.)

23

24

TEST

IRQA

In

3.3

Factory test use only. Must be tied low.

Interrupt request port A, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to

ground and High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

FN6787.2

July 12, 2012

18

D2-926xx

Pin Description DAE-3HT (72-Pin)(Continued)

NAME

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

PIN (Note 16) TYPE

DESCRIPTION

25

26

27

IRQB

IRQC

IRQD

In

3.3

Interrupt request port B, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to

ground and High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

Interrupt request port C, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to

ground and High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

Interrupt request port D, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to

ground and High/Low logic status establishes boot mode selection upon de-assertion of reset

(nRESET) cycle.

28

29

30

31

CVDD

CGND

RGND

RVDD

P

G

3.3

Core power, 1.8V

Core ground

G

Digital pad ring ground. Internally connected to PWMGND.

P

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers. Internally connected to PWMVDD.

32 PROTECT3

33 PROTECT4

34 PROTECT5

In

4

PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel

assignment, & optional GPIO is defined by firmware.)

PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel

assignment, & optional GPIO is defined by firmware.)

PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel

assignment, & optional GPIO is defined by firmware.)

35 PROTECT6 I/O

/nMUTE

PWM protection input with hysteresis, or optional mute output. (One of 8 protection inputs.

Specific function, channel assignment, and/or optional GPIO is defined by firmware.)

36 PROTECT7

/nOVRT

In

PWM protection input with hysteresis, or optional over-temperature monitor input. (One of 8

protection inputs. Specific function, channel assignment, and/or optional GPIO is defined by

firmware.)

37 PROTECT2

In

P

3.3

4

PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel

assignment, & optional GPIO is defined by firmware.)

38

RVDD

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers. Internally connected to PWMVDD.

39

40

RGND

CGND

G

3.3

Digital pad ring ground. Internally connected to PWMGND.

Core ground

41

42

43

44

45

46

CVDD

PWM11

PWM10

PWM9

PWM8

PWM7

P

O

3.3

Core power, 1.8V

8 or 16

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

FN6787.2

July 12, 2012

19

D2-926xx

Pin Description DAE-3HT (72-Pin)(Continued)

NAME

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

PIN (Note 16) TYPE

DESCRIPTION

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

PWM6

PWM5

PWM4

PWMGND

PWM3

PWM2

PWM1

PWM0

PWMVDD

PLLAGND

XTALI

O

P

3.3

1.8

3.3

8 or 16

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin power ground

8 or 16

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 12 PWM output pins. Channel and operation assignment is defined by

firmware.)

PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to

RVDD.

G

In

O

P

PLL Analog ground

Crystal oscillator analog input port. When using an external clock source, the external clock is

driven into the this port.

XTALO

Crystal oscillator analog output port. When using an external clock source, this pin must be open.

XTALO does not have a drive strength specification.

PLLAVDD

nSS

PLL Analog power, 1.8V

O

P

4

SPI slave select I/O.

RVDD

Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and

receivers. Internally connected to PWMVDD.

RGND

G

P

Digital pad ring ground. Internally connected to PWMGND.

CGND

Core ground

CVDD

Core power, 1.8V

SCK1

/MCLK

I/O

O

8

Assignable general purpose I/O, or MCLK output. Operation and assignment is controlled by

firmware. Assigns as default output for MCLK when enabled through firmware.

nRSTOUT

16 - OD

Active low open drain reset output. Pin drives low from POR generator, 3.3V brownout detector

going active, or from 1.8V brownout detector going active. This output should be used to initiate a

system reset to the nRESET pin upon brownout event detection.

67

68

nRESET

In

3.3

Active low reset input with hysteresis. Activates system level reset when pulled low, initializing all

internal logic and program operations. System latches boot mode selection of the IRQ input pins

on the rising edge.

TIO0

/PSSYNC

I/O

16

Timer I/O port 0, or power supply sync output. Operation and assignment is controlled by

firmware. Leave unconnected when not in use.

FN6787.2

July 12, 2012

20

D2-926xx

Pin Description DAE-3HT (72-Pin)(Continued)

NAME

VOLTAGE

LEVEL

(V)

DRIVE

STRENGTH

(mA)

PIN (Note 16) TYPE

DESCRIPTION

69 PROTECT1

In

3.3

4

PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel

assignment, & optional GPIO is defined by firmware.)

70 PROTECT0

In

4

PWM protection input with hysteresis. (One of 8 protection inputs. Specific function, channel

assignment, & optional GPIO is defined by firmware.)

71

72

SDA0

/TEMPREF

I/O

8 - OD

Two-Wire Serial data port 0, or assignable I/O. Available for NTC temperature sensing reference

as assignable I/O. Function is assigned by firmware.

SCL0

Two-Wire Serial clock port 0, assignable I/O. Available for NTC temperature sensing reference as

assignable I/O. Function is assigned by firmware.

/TEMPNTC

NOTES:

18. Unless otherwise specified, all pin names are active high. Those that are active low have an “n” prefix.

19. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be tied together, CGND pins

to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) CGND and RGND are to be tied together on board. RGND and

PWMGND pins are also internally connected and are to be tied together.

FN6787.2

July 12, 2012

21

D2-926xx

Functional Block Diagram - DAE-3

FIGURE 4. DAE-3 IC FUNCTIONAL BLOCK DIAGRAM

FN6787.2

July 12, 2012

22

D2-926xx

Functional Block Diagram - DAE-3HT

FIGURE 5. DAE-3HT IC FUNCTIONAL BLOCK DIAGRAM

FN6787.2

July 12, 2012

23

D2-926xx

The DAE-3 supports a Class-D amplifier system built around

internal audio processing blocks and amplifier system hardware

functions.

Functional Description

Introduction

The DAE-3 family of ICs provide the core functionality, amplifier

control, and complete audio signal processing for D2Audio

Class-D amplifier solutions. The devices are highly

programmable with all system features and functionality totally

defined by firmware, that includes complete definition of audio

processing, signal flow, digital audio I/O, and amplifier hardware

interface control.

In addition to audio processing blocks and signal flow that are

user-selectable, system functions of hardware are configurable

that include PWM timing control, channel configuration and

assignment, protection and monitoring features, clock

configurations, and other audio system features. Choices and

settings are defined using the Audio Canvas III design tool

software which builds the unique DAE firmware for each

particular system design.

The Audio Canvas III software design tool supports building of the

firmware for the DAE-3 family devices. Using Audio Canvas III, the

designer is able to fully define audio processing and hardware

function features with I/O assignments, and build complete

production-ready firmware for the DAE-3 devices.

DSP

The majority of the audio processing functions and hardware

feature implementations operate through firmware running

within the DSP core. The core is a 24-bit fixed-point Digital Signal

Processor, with its own DMA, interrupt control, memory spaces,

and control interfaces.

DAE-3 DEVICE DESIGNATIONS

The DAE-3 device family includes both the DAE-3 and DAE-3HT

ICs. Functional specifications are identical to both designations

of this family unless otherwise indicated.

Sample Rate Converters (SRC)

DAE-3 family supports internal asynchronous sample rate

conversion to align input audio streams to a single rate

compatible with the DSP processing rate and PWM switch rate.

The family has 4 independent rate estimators, allowing up to 4

asynchronous stereo inputs (8 channels) to be sample rate

converted and processed simultaneously. The sample rate

converter has a measured SNR that exceeds 140dB and a

THD+N that exceeds -125dB.

The family device names apply to these part numbers:

DAE FAMILY

DEVICE NAME

DAE PART

NUMBERS

PACKAGE

PINS

DAE-3

D2-92633-LR

D2-92634-LR

128-Pin Package

DAE-3HT

D2-92683-QR

D2-92684-QR

72-Pin Package

Serial Digital Audio Interface

SERIAL DIGITAL AUDIO INPUTS

The DAE-3 devices are completely pin-compatible with the DAE-6

devices, allowing full flexibility for function vs cost trade-off,

providing cost-effective solutions for applications of varying

end-user features and capabilities.

The DAE-3 families include 4 Serial Audio Interface (SAI) digital

audio input ports supporting up to 8 audio channels.

• The DAE-3 supports four independent SAI ports. All 4 ports

operate asynchronously to receive audio from 4 independent

audio sources, and each of the 4 ports has its own clock and

frame inputs. SAI port 3 (the 4th port) of the DAE-3 has

multiplexed inputs to select that port’s audio from the SAI

input or from the on-chip ADC.

The DAE-3HT devices are identical to the DAE-3 but are provided

in a smaller 72-pin package with features and I/O mapped to

pins supported in that package.

AUDIO CANVAS III SUPPORT

Audio Canvas III is a powerful design tool that lets the designer

define audio processing and build a signal flow customized to the

user’s specifications. It fully supports the DAE-3 family including

configuring the DAE family hardware I/O features and pin

assignments. The designer can define the entire audio signal

flow and architecture without signal flow limitations to any

specific system. Capabilities include drag-and-drop of individual

audio processing blocks that can be inserted into the signal flow,

ability to connect and re-route signal flow, and live update

capability to build and download the new audio architecture

directly into the operating amplifier.

• The DAE-3HT devices support either 4 SAI input ports, or when

its fourth port is used as an audio output, support 3 SAI input

ports.

2

Each SAI port supports the digital audio industry I S standard

which is capable of carrying up to 24-bit Linear PCM audio words

per subframe IEC60958, or compressed digital audio (Dolby®

Digital, AAC, MPEG, etc.) packing per the IEC61937 specification.

The SAI port also supports Left-Justified formatted Linear PCM or

compressed digital audio. These ports support sample rates from

32kHz to 192kHz.

The DAE-3 family of ICs supports a wide variety of signal flows

and audio processing options that are fully programmable and

are completely defined by the system firmware and system

architecture.

SAI data formats are shown in Figure 6. For I2S format, the left

channel data is read when LRCK is low. For the Left-Justified

format, the left channel data is read when LRCK is high. Either

format requires data to be valid on the rising edge of SCLK and

sent MSB-first on SDIN with 32 bits of data per channel. Each set

of digital inputs runs asynchronously to the others and may

accept different sample rates and formats.

The firmware is built by the Audio Canvas III software, enabling

full audio processing and amplifier hardware feature definition

by the designer.

FN6787.2

July 12, 2012

24

D2-926xx

Input audio may be received from the S/PDIF input for 2 audio

SERIAL DIGITAL AUDIO OUTPUTS

input channels, concurrent with and asynchronous from audio

that is also being presented to SAI inputs for other audio input

channels. Routing through the SRC synchronizes this audio from

multiple sources for synchronous audio processing within the

DAE audio processing paths.

Up to 4 SAI ports (up to 8 channels) are supported in the DAE-3

families.

2

• The DAE-3 supports 4 independent I S output ports for a total

of 8 channels of audio.

2

• the DAE-3HT supports 1 I S output port (2 channels) and that

port is configured to operate as either an input port or as an

output port.

Use and channel assignment to the SAI outputs is configured

using the Audio Canvas III software. Any of the DAE device’s 12

audio processing channels may be assigned to any of the

available SAI output channels. Audio Canvas III also assigns use

of the 4th SAI port as in input or output for the DAE-3HT.

Left Channel

LRCLKx

SCLKx

Right Channel

Serial

Data

-1

-2

-1

-2

-3

+3

+2

+1

LSB

+3

+2

+1

LSB

-3

MSB

I²S Format

Right Channel

LRCLKx

SCLKx

Left Channel

Serial

Data

-1

-2

-1

-2

-4

+3

+2

+1

LSB

-3

+3

+2

+1

LSB

-3

MSB

-4

MSB

-1

Left-Justified

FIGURE 6. SAI PORT SUPPORTED DATA FORMATS FOR DELIVERY OF LINEAR PCM OR COMPRESSED AUDIO DATA

FN6787.2

July 12, 2012

25

D2-926xx

S/PDIF Digital Audio Interface

ADC input (DAE-3 Devices Only)

The device families include a S/PDIF Digital receiver and

transmitter.

The DAE-3 devices contains a high-performance Analog-to-Digital

Converter (ADC) that connects to input analog sources with a

minimum of interface circuitry. The ADC is included in the DAE-3

devices only. It is not supported in the DAE-3HT devices.

• The DAE-3 devices (128 pin packaged devices) include an on-

chip multiplexer supporting switching of input from 2 different

S/PDIF input pins. Input selection determines which pin routes

to the S/PDIF receiver.

At a bandwidth of 20kHz at nominal voltage and temperature,

the ADC input of the DAE-3 provides a typical THD+N

(unweighted) value of -81dB and a typical SNR/Dynamic Range

• The DAE-3HT devices (72 pin packaged devices) support one

input pin only and do not use multiplex switching.

of 83dB. These typical performances are based on a 1.0V

1

P-P

kHz sine wave input reference level, using a representative

system-level amplifier environment processing digital audio data

and producing PWM amplifier outputs.

All of the devices in the family include a S/PDIF Digital

transmitter.

S/PDIF RECEIVER

Analog performance is affected by factors that include PCB

layout, shielding and routing of analog traces, additional

components within the analog input path, and proper power

supply isolation techniques.

The S/PDIF receiver input pins are 3.3V CMOS input level

compatible, requiring external circuitry to condition the serial

input. The receiver contains an input transition detector, digital

PLL clock recovery, and a decoder to separate audio, channel

status, and user data. Only the first 24-Channel status bits are

supported. The receiver constantly monitors the incoming data

stream to detect the IEC61937-1 packet headers, and if found,

captures the Pc and Pd data words into registers. The receiver

meets the jitter tolerance specified in IEC60958-4.

The ADC master clock is supplied from the low jitter PLL of the

D2-926xx. The ADC operates synchronous to the DSP processing

which minimizes noise pickup.

PWM Audio Amplifier Outputs

The DAE-3 family devices include an integrated 12-channel PWM

engine. Each engine is independently programmable for timing,

output pin assignment and audio processing path source.

S/PDIF is typically used for receiving compressed (IEC61937-

compliant) as well as stereo PCM (IEC60958-compliant) audio

data. This interface also supports receipt of compressed audio

data that is not compliant with the IEC61937 specification, but

instead meets the IEC60958 specification.

PWM operation is defined by firmware. The Audio Canvas III

design tool provides the selection for audio channel assignment

routing, protection enabling, timing, and PWM output pin

mapping, then uses these selections to build the firmware that

controls the PWM outputs. Some features such as dead-band

timing are also adjustable in real-time through the control

interface.

S/PDIF receive data is routed through the SRC, providing a time

synchronized audio input stream for use within any of the DAE

audio processing channels. Audio may be presented on the

S/PDIF input asynchronous to audio also being presented to the

2

I S Serial Digital inputs such that after routing through the SRC,

Programmability enable use of multiple PWM output topologies,

which supporting system designs of a broad range of output

stages. Output topologies include integrated power stages, or

discrete implementations using N+N or P+N for half-bridge, full-

bridge or bridged-tied-load power stages. The PWM outputs may

be used for powered outputs, and may also be used for driving

line-level or headphone outputs.

are synchronous time aligned for internal DAE audio processing.

S/PDIF TRANSMITTER

The transmitter complies with the consumer applications defined

in IEC60958-3. The transmitter supports 24-bit audio data, 24-bit

user data, and 30-bit channel status data. S/PDIF output is linear

PCM only and is non-compressed. Routing of compressed audio

that is presented to the DAE inputs must be decoded by the DAE

and its firmware before the selected channels may be routed to

the S/PDIF outputs.

The 12 PWM channels are mapped to the PWM output pins by

firmware register assignment. Both DAE-3 and DAE-3HT include

12 PWM engines, and their available pins are:

Audio routing to the S/PDIF transmitter is defined by the signal

flow built by the Audio Canvas III software. That software

supports assigning any of the audio processing channels to the 2

(L/R) channels of the S/PDIF output. Because all timing of the

internal audio processing is synchronous to the internal DSP and

processing channels, the S/PDIF audio output is also

synchronous to that internal timing.

• DAE-3 - 18 assignable and mappable pins

• DAE-3HT- 12 assignable and mappable pins

FN6787.2

July 12, 2012

26

D2-926xx

Timers provides programmed I/O control of features that are

Amplifier Protection

event or timing dependent. Their hardware pins are assigned to

system features, and operation is controlled through firmware.

Timer pins are configurable based on the features supported

within the system firmware. Choice and operation of their

assigned features is selected through the Audio Canvas III

software that builds the firmware for the specific system project.

The core firmware that operates the DAE-3 family devices

supports protection options to prevent damage from faults

present in class-D amplifier designs. This protection is also

effective against user-induced faults such as clipping, output

overload, or output shorts, including both shorted outputs or

short-to-ground faults.

POWER SUPPLY SYNCHRONIZATION

Protection features and their details are firmware dependent.

The Audio Canvas III program provides selection for assignment

and use of certain protection methods, using the selections for

building the system firmware.

The PSSYNC pin provides a power supply synchronization signal

for switching power supplies. This synchronizing of power supply

switching with the PWM switching rate eliminates audio output

tones generated if the switching power supply is not locked to the

amplifier switching.

GRACEFUL OVERCURRENT AND SHORT CIRCUIT

Per-channel PWM protection is supported through individual

protection input pins. These PROTECT pins are primarily intended

for protecting the PWM powered output stages and operation is

firmware controlled. The protection input signal is typically

generated by sensing circuits within power stages and can

include sensing for detecting current, temperature, or voltage

fault conditions.

Firmware settings configure PSSYNC to the desired frequency

needed by the system switching regulator. The Audio Canvas III

software supports selection of use and frequency of this output.

Clocks And PLL

The PLL block operation is completely managed by the system

firmware. The clock generation contains a low jitter PLL critical

for low noise PWM output and a precise master clock source for

the ADC, sample rate conversion, and the audio data paths.

Overcurrent sensing requires a current sensor in the power

device to be protected, usually a powered PWM output. The

typical sensor asserts its fault signal that is routed to the

PROTECT pins of the DAE device.

The PLL block includes a low noise crystal oscillator, clock

multipliers clock generation for all internal device timing, PWM

engine timing, and clock reference for use with assignable clock

outputs that include MCLK and PSSYNC outputs.

The D2-926xx devices observe the overcurrent protection inputs

and provides graceful protection for the assigned output stages.

Hardware may be configured to provide immediate current

reduction, cycle-by-cycle output clipping, output signal control,

and output stage deactivation depending on the severity and

duration of high current events. The combination of hardware

features and firmware monitoring allows the system to

differentiate between an overcurrent situation or a more serious

short circuit condition, and supports the managed protection

within the DAE amplifier systems.

The system clock is provided by the crystal oscillator, using either

a fundamental mode crystal or a clock input to the XTALI pin. If

the clock input is used, it must be a 1.8V signal level. The input

signal on the XTALI pin is analog buffered and driven onto the

OSCOUT pin for use in driving the XTALI input of other D2-926xx

controllers, for supporting synchronous timing if multiple DAE

devices are used in a single application.

Reset and Initialization

THERMAL PROTECTION

The D2-926xx must be reset after power-up to begin proper

operation. In normal system hardware configurations, the reset

occurs automatically via the reset hardware circuitry. The chip

contains power rail sensors, brownout detectors, on the 3.3V and

1.8V power supplies. These brownout sensors will assert and hold

an internal Power-on Reset which will disable the device until the

power supplies are at a safe level for the DSP to start. These same

brownout sensors will detect a power supply voltage droop while

the system is active and provide a safe amplifier shutdown.

Temperature monitoring may be used to provide warning,

shutdown, or managed output level reduction to attempt to

reduce heating effects at high load power. Multiple thermal

protection methods are supported within the DAE family

firmware. User choice of method and operation is

programmable, using the Audio Canvas III software to configure

settings and options.

Hardware I/O Features

The DAE-3 and DAE-3HT provides programmable I/O pins used

for various hardware functions of the system design. Pin

functions are defined by the product firmware and configured

with the Audio Canvas III software.

Power Sequencing

The CVDD and RVDD (including PWMVDD) supplies should be

brought up together to avoid high current transients that could

fold back a power supply regulator. The ADCVDD and PLLVDD

may be brought up separately. Best practice would be for all

supplies to feed from regulators with a common power source.

Typically this can be achieved by using a single 5V power source

and regulating the 3.3V and 1.8V supplies from that 5V source.

GENERAL-PURPOSE I/O AND TIMERS

General Purpose I/O (GPIO) pins are available for system use

with the DAE-3 and are assignable by choice selection in the

Audio Canvas III software. The DAE-3 supports pins assignable to

various hardware features, while the DAE-3HT shares functions

of some of its available device pins providing feature choices in a

lower pin-count package.

FN6787.2

July 12, 2012

27

D2-926xx

memory. The boot ROM code is designed to handle both

encrypted and non-encrypted boot images from any of the boot

modes shown in Table 2.

Reset

D2-926xx has one reset input: the nRESET pin. The nRESET input

pin (active low, non-reset high) is effectively a power-on system

reset. All internal state logic is initialized by nRESET. While reset

is active the system is held in the reset condition which is defined

as all internal reset signals being active, the crystal oscillator is

running, and the PLL disabled. At the de-assertion of nRESET, the

chip will capture the boot mode selection from the IRQ[D:A] pins

and begin the boot process.

The specific boot mode is selected based on the state of the

IRQD, IRQC, IRQB, and IRQA pins at the time of reset

de-assertion. The mode is selected by a hardware pull-up or

pull-down connection to each of the four boot mode (IRQ[D:A])

pins. (Modes not listed are reserved.)

Control Interfaces

The nRSTOUT pin is an active low open drain reset output. This

pin drives low from the internal power-on-reset generator, 3.3V

brownout detector going active, or from 1.8V brownout detector

going active. This output should be used to initiate a system

reset, and to also connect to the nRESET pin to initiate a DAE

reset upon brownout event detection.

2

I C 2-WIRE INTERFACE

2

The D2-926xx family ICs have two separate I C 2-Wire

compatible ports. Port 1 is used as the external controller

interface, and Port 0 is used for booting from an external

2

EEPROMs or compatible chips. Both I C interfaces are

multi-master capable.

Booting and Boot Modes

D2-926xx includes a fully-programmable DSP with internal boot

ROM. The boot ROM’s primary function is to download a

second-stage boot image from one of several possible sources.

SERIAL PERIPHERAL INTERFACE (SPI™)

The Serial Peripheral Interface (SPI) is provides an alternate boot

source interface such as an SPI Flash. The SPI port is used only

for boot operation. Register control of the system firmware is not

implemented through the SPI interface.

The system requires external firmware to boot the internal DSP.

Internal ROM within the DAE-3 initiates the boot process to read

the boot records and firmware, to load into the internal DAE-3

TABLE 2. BOOT MODES

XTALI RANGE INTERFACE SPEED

MODE IRQ[D:A]

DAE M/S

Slave

Master

-

DESCRIPTION

I C port 1 slave to external master, boot @ address 88

2

0

1

0000

0001

0010

-

N/A

24.576MHz

-

per Master

400kb/s

1.53MHz

-

2

I C port 0 master to I C EEPROM slave

SPI port master to SPI Flash slave

Reserved

2

3-F

FN6787.2

July 12, 2012

28

D2-926xx

8. Transmit data lower byte

Reading and Writing Control Registers

DAE control is provided through the I C port, using registers and

2

9. I C STOP command

memory spaces that are defined within the firmware. After

booting and initialization, this control port provides continuous

read and write access for control and monitoring of the amplifier

system. Register addresses are dynamic based on the audio path

signal flow and hardware options selected for the particular

project. Address locations are generated for each system through

a header file from the Audio Canvas III design tool that maps the

address location to each parameter of the system.

All reads to registers require two steps. First, the master must

send a dummy write which consist of sending a Start, followed by

the device address with the write bit set, and three register

address bytes. Next, the master must send a repeated Start,

following with the device address with the read/write bit set to

read, and then read the next three data bytes. The master must

Acknowledge (ACK) the first two read bytes and send a Not

Acknowledge (NACK) on the third byte received and a Stop

condition to complete the transaction. The device's control

interface acknowledges each byte by pulling SDA low on the bit

immediately following each write byte. The device read function,

2

The I C port is used for reading and writing the control data. The

highest-order byte of the register address (bits 23:16) determines

the internal address space used for control read or write access,

and the remaining 16 bits (bits 15:0) describe the actual address

within that space.

2

as shown in Figure 8, executes the following 11 steps as the I C

bus master:

2

1. I C START command

All reads or writes to registers (shown in Figures 7 and 8) begin

with a Start Condition, followed by the Device Address byte, three

Register Address bytes, three Data bytes and a Stop Condition.

2

2. Transmit device I C address with W

3. Transmit mode byte

2

Register writes through the I C interface are initiated by setting

the read/write bit that is within the device address byte. The

device write function as, shown in Figure 7, executes the

following 9 steps as the I C bus master:

4. Transmit upper memory address byte

5. Transmit lower memory address byte

6. Repeat START command

2

1. I C START command

2

7. Transmit device I C address with R

2

2. Transmit device I C address with W

8. Receive data upper byte

9. Receive data middle byte

10. Receive data lower byte

3. Transmit mode byte

4. Transmit upper memory address byte

5. Transmit lower memory address byte

6. Transmit data upper byte

2

11. I C STOP command or NACK

7. Transmit data middle byte

ACK

DEVICE-ADDR

REGISTER [23:16]

REGISTER [15:8]

REGISTER [7:0]

START

R/W

ACK

Write Sequence

REGISTER [7:0]

DATA [23:16]

DATA [15:8]

DATA [7:0]

STOP

2

FIGURE 7. I C WRITE SEQUENCE OPERATION

Step 1

ACK

DEVICE-ADDR

REGISTER [23:16]

REGISTER [15:8]

REGISTER [7:0]

REPEAT

START

R/W

MASTER

ACK

MASTER

ACK

NACK

Read Sequence

DEVICE-ADDR

DATA [23:16]

DATA [15:8]

DATA [7:0]

REPEAT

START

R/W

STOP

Step 2

2

FIGURE 8. I C READ SEQUENCE OPERATION

FN6787.2

July 12, 2012

29

D2-926xx

STEREO A/B SWITCH

Audio Processing

The A/B Switch provides stereo routing selection to switching

either of 2 pairs of stereo inputs to its output. It operates as a

double-pole, double-throw type of switch to the audio flow.

Audio processing is totally defined by the system firmware and

signal flow. Audio processing blocks are implemented using the

Audio Canvas III design tool software. This tool includes an

extensive library of audio processing functions that are

developed for operating in the DAE-3 and DAE-3HT device

families.

TONE CONTROL

Tone Controls are shelving filters providing independent of gain

and frequency adjustment for bass and treble tone settings.

Frequency and gain are continuously and independently

adjustable for both the bass and treble settings, supporting gain

ranges of -14 to +14 dB.

The Audio Canvas III software provides the interface to define

and build a complete audio sound processing system. Drag-and-

drop inserting of its included audio processing blocks enables

building a customized signal flow, by placing audio algorithms

into customized firmware for executing on the DAE devices.

PARAMETRIC EQUALIZERS

Parametric Equalizer (EQ) blocks provide an adjustable bandpass

or band-reject frequency response. With frequency-domain

parameter settings of frequency, gain, and bandwidth or Q,

parameters are continuously and independently adjustable. EQs

are provided as individual audio blocks, and as blocks with

groups of 3-Band and 5-Band EQs.

Audio Processing Algorithms

Audio processing algorithms include all of these following

functions. Multiples of each are permitted, and there is no limit

to the order or interconnect of the algorithm blocks. Upon

completion of defining the audio processing path, the Audio

Canvas III software incorporates the blocks and builds the final

system firmware for loading onto and running the DAE devices.

BIQUAD FILTER (FREQUENCY DOMAIN

CONFIGURATION)

Details and equations for each parameter are provided in the

Audio Canvas III User’s Manual.

The Biquad block is a frequency-domain-parameter-entry biquad

filter implemented as a second-order biquad algorithm, providing

configurable high-pass, low-pass, and all-pass filtering functions.

First or second filter order may be selected, and parameter

setting entries of frequency and damping coefficient are

continuously adjustable. Bypass and polarity phase inversion is

also supported.

INPUT SOURCE SELECTION

A source selection register defines input channel assignment of

audio presented to the DAE device’s audio input ports.

VOLUME

Volume control blocks provide level and trim adjustments within

the signal flow. Continuous adjustment through programmable

gain ranges supports attenuation to -100dB and gain to +24dB. A

single 24-bit register value provides gain setting and also

supports selectable audio phase inversion.

BIQUAD FILTER (Z-DOMAIN CONFIGURATION)

The z-Domain Biquad is a second order biquad digital algorithm

that operates from direct entry of z-transform coefficients. The

filter supports individual user entry coefficients enabling nearly

any second order filter synthesis per cascadable block.

SHARED VOLUME

FILTER - CROSSOVER

Shared Volume blocks implement multiple channels of level

attenuation. The number of channels is configurable and a single

24-bit register value equally controls all channel levels. Volume is

continuously adjustable from unity gain to -100dB.

The Crossover Filter blocks provide high-pass or low-pass filtering

using frequency domain adjustment settings. Blocks are

implemented from 2 cascaded second-order biquad elements,

with selections that directly implement Linkwitz-Riley,

Butterworth, or Bessel filter presets. Slope setting is adjustable

from 6, 12, 18 or 24dB per octave, frequency and damping

coefficients are continuously adjustable, and bypass, active or

mute functions are supported.

MIXERS

Mixers provide individually-adjustable inputs that are summed

together and passed to their output. Each input mixing level is

controlled with its own 24-bit register that provides continuous

adjustment from unity gain to -100dB, along with full audio path

cut-off and optional input phase inversion supporting sum and

difference mixers. Audio block choices include 2-input, 4-input,

and configurable N-input mixers accommodating as many inputs

as desired.

FIR FILTER

The FIR filter is a configurable n-tap finite impulse response filter

implementation. The number of taps and their coefficient values

are defined in the audio signal flow simply through a user-

generated list of tap coefficients for the FIR structure.

ROUTER

EXCURSION CONTROL

Routers perform independent channel routing assignment,

connecting any input to any output. Number of channels is

configurable with up to 64 inputs and 12 outputs.

Excursion Control is a specialized algorithm that dynamically

controls audio based on frequency and level. Excursion Control

boosts the low frequency response to compensate for physically-

limited low-frequency capabilities of small loudspeakers and

subwoofers at low listening levels. As listening levels rise, it

dynamically adjusts its boost enabling an optimum sub-woofer

listening experience at all loudness levels.

FN6787.2

July 12, 2012

30

D2-926xx

DELAY

MONO MIXER

Delay Blocks introduce an adjustable delay of a channel's audio

data. Buffer size is fully user-configurable, supporting adjustment

over a range as small as milliseconds, to over 1 second.

A Mono Mixer is a threshold-gating mixer that routes the sum of

either or both of its 2 inputs into its output, based on a control

level input. This threshold-controlled mixing supports processing

of input audio that may be mono on both Left and Right, or

containing content on only one of Left or Right. This summed

audio then passes equally to stereo processing and output

system channels.

COMPRESSOR

Compressors provide threshold-dependent level adjustments,

implementing dynamic attenuation at configurable rates as the

control signal level increases. Headroom level is configurable,

supporting adjustable threshold ranges. Ratio, threshold, and

attack/release times are also fully adjustable. Compressors

incorporate a side chain input for algorithm control, supporting

compressing or limiting operation from inputs independent of

the processed channel audio signal flow.

DITHER GENERATOR

The Dither Block generates a random noise (dither) pattern at a

shaped-spectrum low level. This noise is available to sum into the

audio path using a mixer, pushing up low-order bits of low-level

audio. This process enables improved uniform audio quality

when digital bit depth truncation is required because of

interfacing equipment. Audio signal flow data is normally

processed and output in digital format as 24 bits from the

channels assigned to the SAI digital outputs.

COMPRESSOR/EXPANDER

The Expander Compressor implements dynamic low level signal

expansion, or an upward compression to audio levels. The

Expander Compressor implements dynamic low level signal

expansion for an upward compression to audio levels. Adjustable

settings include gate threshold and ratio, expansion threshold,

ratio, and expansion gain limit, and attack and release times.

HARMONICS GENERATOR

The Harmonics Generator provides a harmonic spectrum content

from audio presented to its input. Harmonic order and amplitude

is programmable, supporting customized audio processing

features.

ENVELOPE VOLTAGE CONTROLLED AMPLIFIER

The Envelope VCA processes its control input to establish an

amplitude envelope signal representing the audio path input

level. The Envelope VCA uses its side chain input to establish an

amplitude envelope of the audio level. Controls are similar to

that of the Compressor Block.

SoundSuite™ Processing

The D2Audio SoundSuite™ audio processing provides a full set of

enhancements to audio that greatly add to the quality and

listening experience of sound in wide scopes of consumer

devices. The SoundSuite algorithms use psycho-acoustic

processing that create a rich-sounding environment from small

speakers, and synthesizes the sound and quality equivalent to

more complex systems. It is especially suited to consumer

products that include televisions, docking stations, and mini hi-fi

stereo products. SoundSuite Processing includes:

REVERB

The Reverb Block is a 2-channel stereo reverb processor. It

provides adjustable reverb time and damping settings, and its

built-in mixer includes adjustments for both dry and wet audio

levels.

• D2Audio™ WideSound™

• D2Audio™ WideSound™ x4

• D2Audio™ DeepBass™

• D2Audio™ Mono2Stereo™

CHIME GENERATOR

The Chime Generator contains 3 oscillators, each with adjustable

frequency and gain. When triggered, the oscillators initially

produce full programmed output levels that then decrease at

their programmable decay time rate.

D2Audio™ SoundSuite™ algorithms are completely supported

with all part numbers of the DAE-3 and DAE-3HT families.

RMS LEVEL METER

RMS Meters provide real-time indication of the signal levels

through the audio processing path. Visible in the Audio Canvas III

signal flow, they provide continuous level indication. Measured

data in the meter's registers may also be read by system

controllers for monitoring levels in a final production system.

FADE-PAN

The Fade-Pan control provides level adjustment of 4 input

channels to 4 output channels. Implementation includes a

Rear/Front fade adjustment, and a Left/Right balance

adjustment. Controls are continuously adjustable, providing unity

gain at mid-point settings, and attenuating output levels of its

channels as the respective control is adjusted away from that

channel's direction.

FN6787.2

July 12, 2012

31

D2-926xx

AM radio station, reducing possible station interference. The

algorithm is optional and selection is controlled through a

register setting that is created with the system firmware.

Third Party Virtualization and Enhancements

Enhancement processing and virtualization algorithms from

third-party technology providers are available to add to Audio

Canvas III. As permitted through license agreements from the

providers, these algorithms are supplied to the designer where

they integrate into the Audio Canvas III software, and appear as

additional audio block choices.

MCLK CLOCK OUTPUT

2

The MCLK output provides the I S clock to external digital audio

circuits or devices. The MCLK output is optional, and when

enables is selectable between 2 frequencies.

Depending on device part number and design-specific firmware

definitions, the DAE-3 device supports a variety of processing,

decoding, virtualization, and pre/post processing feature sets.

Features and processing support is shown in Table 1 on page 3.

PSSYNC CLOCK OUTPUT

The PSSYNC signal is used for synchronizing switching power

converters used in the amplifier. Providing a synchronizing

frequency that is a multiple or sub-multiple of the PWM switching

rate eliminates possibility of in-band audio frequency generation

from close but asynchronous clocks. The output is optional, and

when enabled supports 6 frequency multiple choices.

Audio Processing Block Controls

Each audio processing block is assigned its own registers

providing adjustment controls for the parameters associated

with its audio function. Some blocks use one register only, while

other blocks with multiple control settings may use multiple

registers for each control. The parameter equations for all of the

audio blocks are provided in the Audio Canvas III User’s Manual.

AUDIO I/O CONFIGURATION

This configuration allow choice selection of which audio

processing channels are assigned to the S/PDIF and I S digital

2

outputs. It also supports choice of input port assignments to the

audio input channels.

Dynamic Register Addressing Architecture

Audio Canvas III supports building of any signal flow with no

restriction of the order of occurrence of any audio block, or any

limit to repeated deleting or addition during signal flow editing.

As audio algorithm blocks are edited, added, or removed, the

user-space memory addresses for each register will change.

However, each instance of each block has its own unique label

identifier where that identifier is clearly known and visible on the

signal flow workspace.

FAULT INDICATION

An optional output may be assigned to provide a control signal to

a system controller or other hardware within the amplifier upon

detection of protection or fault conditions. The feature may be

enabled or disabled, and when enabled, allows choosing an

available I/O pin for providing this output.

DECODER SELECTION

Because each and every algorithm is assigned its own dedicated

register for its parameter settings, the Audio Canvas III generates

a variable-to-address mapping for each build of each project. This

mapping is provided as a text file in a header file format that can

be directly included within a system controller’s software build.

As multiple iterations of a signal flow are created during the

design process, a new header file is created matching each

revision. Simply including the header file within the system

controller compile automatically passes these new register

addresses without need for repeated system code editing.

Third party decoding of compressed formats is supported based

on the particular device part number. By default, when a device is

used that supports the licensed technology, its supported

decoding is enabled. Choices allow building of firmware to

selectively include or exclude the available decoding algorithms.

FORMAT CHANGE NOTIFICATION

The Format Change Notification feature allow assigning an I/O

pin to provide hardware indication when a change of decoded

format types is detected. This supports dynamic audio path

allocation by the system controller when audio content changes

to or from PCM and an encoded format. The feature is disabled

by default, but when enabled, allows assignment of the I/O pin to

signal this state. An additional setting allows choosing an audio

muting time delay between format changes.

Hardware Feature Functions

In addition to the core firmware that runs the DAE devices to

operate the amplifier, several feature-specific options are

supported for use in the amplifier system. These optional

features are configurable and may be chosen or bypassed.

Configuration is set using the Audio Canvas III software, where

based on chosen settings, the firmware will include each function

along with the hardware I/O assigned to its function.

IDLE POWER MANAGEMENT

The Idle Power Management feature allows controlled audio

PWM output shutdown after a time period has elapsed with no

audio detected above a threshold level. The feature is disabled by

default and when enabled allows choice of threshold time and

signal level, and assignment of an I/O pin that can be used to

signal other operations in the amplifier.

The DAE-3 supports pins assignable to various hardware

features, while the DAE-3HT shares choices between functions

with some of its available pins providing feature choices in a

lower pin-count package.

These hardware feature algorithms include:

AM AVOIDANCE MODE

AM Avoidance Mode allows selecting the PWM switching

frequency to move its harmonics away from the frequency of an

FN6787.2

July 12, 2012

32

D2-926xx

MASTER VOLUME ENCODER

The Master Volume Encoder fe a tu er allows assigning of I/O

pins to a quadrature-type encoder that can be used as a

mechanical volume control. The fe a tu er is disabled by default,

but when enabled allows choice of volume control algorithm

association in the audio signal flow, and choice of the I/O pins.

PWM OUTPUT CONFIGURATION

The PWM Output Configuration functions support assignment of

PWM output pins to each of the 12 PWM engines. It allows pin

polarity selection, and choice of enabling or disabling each PWM

engine.

PWM OUTPUT TIMING

The PWM Output Timing controls enable per-channel adjustment

of each PWM output timing. Controls included dead time,

minimum pulse width, and stagger settings between channels.

POWER DOWN OUTPUT

The Power Down Output feature supports setting an output pin

that can connect to power stages, for manually shutting down

power stages during fault detection and system startup. When

enabled, the algorithm supports specification entry of the I/O pin

to be used for the function.

TEMPERATURE SENSING

A thermal protection algorithm supports use of NTC resistors

placed in heat-sensitive areas of the amplifier. The algorithms

run and provide real-time temperature measurement.

Temperature values are available in firmware registers for

reading by a system controller, and set-points in the algorithm

can be used to trigger a controlled-attenuation level reduction or

fault shutdown.

THERMAL MANAGEMENT

An additional thermal protection algorithm supports a high

temperature warning input to trigger controlled-attenuation level

reduction. Rate of change and delay are programmable when the

feature is enabled.

FN6787.2

July 12, 2012

33

D2-926xx

Pin Function Mapping Between Devices

Table 3 lists the pin numbers, names and functions for both the

DAE-3 and DAE-3HT devices, and provides a mapping of the pin

functions between those devices.

DAE-3 And DAE-3HT Differences

The DAE-3 device family includes both the DAE-3 and DAE-3HT.

Functional specifications are identical to both designations of

this family. However, the DAE-3HT, provided in its smaller 72-pin

package supports system and assignable functions that are

mapped to the pins supported in that package. Complete pin

functions of all pins of both devices of the DAE-3 family are listed

in the Pin Description Tables.

TABLE 3. DAE-3 AND DAE-3HT PIN AND I/O COMPARISON TABLE

PIN NUMBERS

PIN NAMES

DESCRIPTION AND FUNCTION

DAE-3 DAE-3HT

DAE-3

DAE-3HT

DAE-3

DAE-3HT

2

1

SC20

SRD2

SC21

SCK2

STD2

SC22

SCK3

STD3

SC32

SRD3

SDA1

SCL1

SCK1

TIO0

SCLK3

(SC20)

I S Input Port 1 SCLK

I S Port 3 Input Channels 5-6 SCLK

2

SDIN3

(SRD2)

I S Data Port 1, Input Channels 1-2

I S Port 3 Input Channels 5-6 Audio Input Data

2

3

LRCK3

(SC21)

I S Input Port 1 LRCK

I S Port 3 Input Channels 5-6 LRCK

2

4

SCLK4

(SCK2)

I S Input Port 2 SCLK

I S Port 4 Input Channels 7-8, or Output Channels

1-2 SCLK

2

5

SDIO4

(STD2)

I S Data Port 2, Input Channels 3-4

I S Port 4 Input Channels 7-8, or Output Channels

1-2 Audio Data

2

6

LRCK4

(SC22)

I S Input Port 2 LRCK

I S Port 4 Input Channels 7-8, or Output Channels

1-2 LRCK

2

8

7

SCLK12 I S Input Port 3 SCLK

(SCK3)

I S Ports 1&2 Input Channels 1-4 SCLK

2

9

8

SDIN2

(STD3)

I S Data Port 4, Input Channels 7-8

I S Port 2 Input Channels 3-4 Audio Data

2

10

13

36

37

119

123

127

128

27

125

124

65

9

LRCK12 I S Input Port 4 LRCK

(SC32)

I S Ports 1&2 Input Channels 1-4 LRCK

2

10

19

20

65

68

71

72

16

70

69

37

SDIN1

(SRD3)

I S Data Port 3, Input Channels 5-6

I S Port 1 Input Channels 1-2 Audio Data

SDA1

2-Wire (I2C) Data Port (Controller Port)

2-Wire (I2C) Clock Port (Controller Port)

2-Wire (I2C) Data Port (Controller Port)

2-Wire (I2C) Clock Port (Controller Port)

Assignable GPIO or MCLK Output

SCL1

2

SCK1

/MCLK

I S Output Port SCLK

TIO0

/PSSYNC

Timer I/O port 0.

Timer I/O port 0, or Assignable Power Supply Sync

Output

SDA0

SCL0

TIO1

SDA0

/TEMPREF

2-Wire (I2C) Data Port

Assignable I/O, NTC Temp Sense Reference

Assignable I/O, NTC Temp Sense NTC

Assignable I/O, NTC Temp Sense Common

PWM Channel 0 Protect Input

SCL0

/TEMPNTC

2-Wire (I2C) Clock Port

TIO1

/NTC

Timer I/O port 1, NTC Temp Sense Common

PROTECT0 PROTECT0 PWM Channel 0 Protect Input

PROTECT1 PROTECT1 PWM Channel 1 Protect Input

PROTECT2 PROTECT2 PWM Channel 2 Protect Input

PWM Channel 1 Protect Input

PWM Channel 2 Protect Input

FN6787.2

July 12, 2012

34

D2-926xx

TABLE 3. DAE-3 AND DAE-3HT PIN AND I/O COMPARISON TABLE (Continued)

PIN NUMBERS

PIN NAMES

DAE-3 DAE-3HT

DESCRIPTION AND FUNCTION

DAE-3 DAE-3HT

DAE-3

DAE-3HT

60

61

62

63

64

95

32

33

34

35

36

54

PROTECT3 PROTECT3 PWM Channel 3 Protect Input

PROTECT4 PROTECT4 PWM Channel 4 Protect Input

PROTECT5 PROTECT5 PWM Channel 5 Protect Input

PWM Channel 3 Protect Input

PWM Channel 4 Protect Input

PWM Channel 5 Protect Input

PROTECT6 PROTECT6 PWM Channel 6 Protect Input

/nMUTE

Assignable PWM Protect Input, or Mute Output

PROTECT7 PROTECT7 PWM Channel 7 Protect Input

/nOVRT

Assignable PWM Protect Input, or Over-

Temperature Monitor Input

PWM0

PWM output pin. (One of 18 PWM output pins.

Channel and operation assignment is defined by

firmware.)

PWM output pin. (One of 12 PWM output pins.

Channel and operation assignment is defined by

firmware.)

I/O Pin Function Assignment Comparison

Pin I/O functions and their assignments are supported through

user selections of the Audio Canvas III software that builds the

DAE-3 or DAE-3HT firmware. The designer has the option of

choosing the offered features and allocating I/O pins to those

features based on individual system design needs.

MCLK

• The DAE-3 utilizes a dedicated pin for the MCLK output. That

pin is available only for MCLK. User selection determines if

MCLK is present on this pin or if its output is off.

• The DAE-3HT provides a user selection to choose whether to

enable the MCLK output. This pin (the SCK1/MCLK pin)

becomes assigned to MCLK when MCLK is enabled. When

MCLK is disabled, the SDK1/MCLK pin becomes available for

assignment to other hardware I/O functions.

The differences of pin functions are shown in the preceding table,

but the following provides additional detail to certain of these

pins and functions as to their available features and assignment.

PWM OUTPUT PINS

PROTECTION INPUT PINS

• The DAE-3 has 18 PWM pins that are assignable to any of the

DAE-3’s 12 PWM channels.

• The DAE-3 provides 9 protect input pins, where the first 8 are

allocated to the first 8 PWM engines. The last of the 9 is a

dedicated input for monitoring an over-temperature warning

control signal from power stages or other monitoring switches.

• The DAE-3HT has 12 PWM pins that are assignable to any of

the DAE-3’s 12 PWM channels.

2

I S DIGITAL INPUTS AND OUTPUTS

• The DAE-3HT provides 8 protect input pins. These pins are all

assignable to be used as the protect input for their default

PWM engine, or when not used for that protection become

available for use with other pin-assignable hardware I/O

functions. All selection is established through the user

interface of the Audio Canvas III design tool program.

2

• The DAE-3 supports 8 audio INPUT channels through 4 I S

serial digital audio input ports. Port assignments are

established with the firmware built with the Audio Canvas III

software for the DAE-3 devices.

2

• The DAE-3 supports 8 audio OUTPUT channels through 4 I S

serial digital audio output ports. Port and channel assignments

are established through user selection with the firmware built

with the Audio Canvas III software for the DAE-3 devices.

• The DAE-3HT supports a user choice of either:

2

- 8 audio INPUT channels through 4 I S serial digital audio

2

input ports, and no I S OUTPUTS, or

2

- 6 INPUT channels through 3 I S ports with 1 I S OUTPUT

supporting 2 audio channels.

FN6787.2

July 12, 2012

35

D2-926xx

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE

REVISION

FN6787.2

CHANGE

July 3, 2012

Complete datasheet rewrite to add DAE-3HT devices to the DAE-3 family.

- Revisions and additions to accommodate additions for DAE-3HT to DAE-3/DAE-3HT family.

- Complete rewrite of page 1 description and features, and complete rewrite of all functional description content.

(Rewrites do not change function of DAE-3 devices, but provide more accurate explanation of device use.)

- No changes to DAE-3 specifications other than: Addition and revision of ADC specifications and updates of

supporting detail for ADC. All other DAE-3 specifications unless noted by DAE-3HT specific designations are

identical to those of DAE-3.

- Updates to DAE-3 high-level and detail block diagrams, and addition of diagrams for DAE-3HT.

- Removal of ADC and DSD plots.

- Removal of all HDA interface, HDMI interface, DSD, and SCI references and descriptions.

- Removal of D2-92613-LR and D2-92625-LR part numbers which are being discontinued. (Their features are

fully supported in the D2-92633-LR part number and the removed part numbers are not needed.)

POD Q128.14x14 updated to latest revision - Changed title from “Thin Plastic Quad Flatpack Package (LQFP)”

to “Low Plastic Quad Flatpack Package (LQFP)”

POD L72.10x10F updated to latest revision - Changed bottom view to reflect correct pin 1 corner and pin

numbering. Also cleaned up details Y & Z

May 3, 2011

FN6787.1

Rewrite of datasheet. Fixes to incorrect (pin 109) connection description, removal of unnecessary descriptive

content and structure.

-Updated datasheet to latest corporate document format and applied standards as follows:

Ordering information added audio processing column, added device support note, numbered notes, lead finish

matching intrepid.

Added Tjc to Thermal Information and corresponding note on page 5

Added Compliance note on page 6 referencing MIN and MAX columns of Electrical Spec Tables

-Updated Block Diagram on page 1 - complete re-draw.

-Removed D2-92643 part number from DAE-3 Device Feature Set Offering Table 1 on page 2 (this is not an

available ordering part number)

-Corrected pin 109 (nTRST) description error on page 14 to indicate that it must be pulled high at all times.

(internally-requested error correction). Changed from: "Hardware test mode control. For D2Audio use only. Must

be tied high or low." To: "Factory test only. Must be tied high at all times."

-Removed outdated high level system diagrams,

-Removed all (outdated and non-applicable) reference design examples,

-Removed unnecessary HDA connection diagrams

-Removed trademarks section/paragraph. Explicit listing not required/sufficiently covered through other

means.

April 1, 2010

FN6787.0

Initial Release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6787.2

July 12, 2012

36

D2-926xx

Low Plastic Quad Flatpack Packages (LQFP)

Q128.14x14

128 LEAD LOW PLASTIC QUAD FLATPACK PACKAGE .4

MM PITCH

4X

0.2 Y T-U Z

D

MILLIMETERS

PIN 1

97

128

Z

SYMBOL

MIN

-

NOM

MAX

1.60

0.15

1.45

0.23

0.19

0.20

0.16

NOTES

A

A1

A2

b

-

1

96

0.05

1.35

0.13

0.09

-

1.40

-

0.16

4

b1

c

-

U

T

c1

D

-

16 BSC

14 BSC

16 BSC

14 BSC

0.60

-

E

E1

-

D1

E

3

-

E1

L

3

0.45

0.75

-

65

32

L1

R1

R2

S

1.00 REF

-

0.08

0.20

0°

-

0.20

-

33

64

-

D1

0.2 H T-U Z

0

3.5°

7°

-

4X

01

02

03

N

0°

-

11°

12°

13°

-

12°

-

DETAIL

0.080 Y

F

128

-

H

Y

e

0.40 BSC

-

Rev. 1 7/11

NOTES:

128X b

1. Dimensions are in millimeters. Dimensions in ( ) for Refer-

ence Only.

e

124X

SEATING PLANE

0.07

b1

Y T-U

c1

M

2. Dimensions and tolerances per AMSEY14.5M-1994.

3. Dimensions D1 and E1 are excluding mold protrusion. Al-

lowable protrusion is 0.25 per side. Dimensions D1 and E1

are exclusive of mold mismatch and determined by datum

plane H.

c

0.05

b

PLATING

02

4. Dimension bdoesnotincludedambarprotrusion. Allowable

dambar protrusion shall not cause the lead width to exceed

the maximum b dimension by more than 0.08mm. Dambar

cannot be located at the lower radius or the foot. Minimum

space between protrusion and an adjacent lead is 0.07 mm.

01

R1

A2

A

R2

0 3

0

A1

S

L

0.25 GAUGE

PLANE

(L1)

DETAIL

F

FN6787.2

July 12, 2012

37

D2-926xx

Package Outline Drawing

L72.10x10F

72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 4/12

A

10.00

6

4X 8.50

6

PIN 1

INDEX AREA

B

PIN 1

INDEX AREA

55

72

1

54

68X 0.50

EXP. DAP

7.70 SQ.

10.00

37

18

(4X)

0.15

36

19

72X 0.25

4

TOP VIEW

0.10 M C A B

SEE DETAIL "Z"

BOTTOM VIEW

SEE DETAIL "X"

0.90 MAX

C

0.10 C

0.08 C

SEATING PLANE

68X 0.50

(0.75)

72X 0.25

9.80 SQ

5

C

0 . 2 REF

37

7.70 SQ

(0.40)

0 . 00 MIN.

0 . 05 MAX.

36

(0.271)

DETAIL “Y”

72X 0.60

DETAIL "Z"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

3.

4.

Unless otherwise specified, tolerance : Decimal ± 0.05

Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Package outline compliant to JESD-MO220.

FN6787.2

July 12, 2012

38


型号：	D2-92634-LR
厂家：	Intersil
描述：	Intelligent Digital Amplifier and Sound Processor 外围集成电路
文件：	总38页 (文件大小：888K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

D2-92634-LR [INTERSIL]

相关型号：

D2-92643

D2-92683-QR

D2-92684-QR

D2-D5

D20

D200

D200-400FR

D2001UK

D2002

D2002AL

D2002BL

D2002UK