DG201A [INTERSIL]
Quad SPST, CMOS Analog Switches; 四通道SPST ， CMOS模拟开关
| 型号： | DG201A |
| 厂家： | 
Intersil |
| 描述： | Quad SPST, CMOS Analog Switches |
| 文件： | 总7页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DG201A, DG202
Data Sheet
June 1999
File Number 3117.2
Quad SPST, CMOS Analog Switches
Features
The DG201A and DG202 quad SPST analog switches are
designed using Intersil’s 44V CMOS process. These
bidirectional switches are latch-proof and feature break-
before-make switching. Designed to block signals up to
• Input Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Low r (Max). . . . . . . . . . . . . . . . . . . . . . . . . . 175Ω
DS(ON)
• TTL, CMOS Compatible
30V
in the OFF state, the DG201A and DG202 offer the
P-P
• Latch-Up Proof
advantages of low ON resistance (≤175Ω), wide input signal
range (±15V) and provide both TTL and CMOS compatibility.
• True Second Source
• Maximum Supply Ratings. . . . . . . . . . . . . . . . . . . . . . 44V
• Logic Inputs Accept Negative Voltages
The DG201A and DG202 are specification and pinout
compatible with the industry standard devices.
Ordering Information
Functional Block Diagrams
DG201A
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
S
1
DG201AAK
DG201ABK
DG201ACJ
DG201ACY
DG202AK
DG202CJ
-55 to 125 16 Ld CERDIP
F16.3
IN
IN
IN
1
D
1
-25 to 85
0 to 70
0 to 70
16 Ld CERDIP
16 Ld PDIP
F16.3
E16.3
M16.3
F16.3
E16.3
S
2
2
3
D
2
16 Ld SOIC
S
3
-55 to 125 16 Ld CERDIP
0 to 70 16 Ld PDIP
D
3
S
4
IN
4
Pinout
D
4
DG201A, DG202
(CERDIP, PDIP, SOIC)
TOP VIEW
DG202
S
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
IN
D
IN
2
1
1
1
IN
IN
IN
IN
1
2
3
4
D
2
D
1
S
S
2
S
2
V+ (SUB-
V-
-
STRATE)
GND
NC
D
S
2
S
4
S
3
3
D
3
D
4
D
3
IN
3
IN
4
S
4
D
4
SWITCHES SHOWN FOR LOGIC “1” INPUT
TRUTH TABLE
LOGIC
DG201A
ON
DG202
OFF
0
1
OFF
ON
Logic “0” ≤0.8V, Logic “1” ≥ 2.4V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-1
DG201A, DG202
Absolute Maximum Ratings
Thermal Information
o
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V
Thermal Resistance (Typical, Note 2)
θ
( C/W)
θ
( C/W)
JA
JC
CERDIP Package. . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
75
100
100
20
N/A
N/A
V
V
V
to Ground (Note 1) . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
IN
S
or V to V+ (Note 1). . . . . . . . . . . . . . . . . . . . . . . . +2 to (V-) -2V
D
or V to V- (Note 1) . . . . . . . . . . . . . . . . . . . . . . . -2 to (V+) +2V
S
D
o
Current, any Terminal Except S or D . . . . . . . . . . . . . . . . . . . . 30mA
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 70mA
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
o
o
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range
“A” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
“B” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 C to 85 C
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
o
o
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on V , V , or V exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
IN
S
D
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications V+ = 15V, V- = -15V, GND = 0V, T = 25 C
A
“A” SUFFIX
“B” AND “C” SUFFIX
(NOTE 3)
(NOTE 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX MIN
TYP
MAX UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
ON
See Figure 1
See Figure 1
-
-
-
-
-
-
-
-
480
370
20
600
-
-
-
-
-
-
-
-
480
370
20
-
-
-
-
-
-
-
-
ns
ns
Turn-OFF Time, t
OFF
450
Charge Injection, Q
C
= 1nF, R = 0, V = 0V
-
-
-
-
-
-
pC
dB
dB
pF
pF
pF
L
S
S
OFF Isolation, OIRR
V
= 5V, R = 75Ω, V = 2.0V,
70
70
IN
L
S
f = 100kHz
Crosstalk (Channel to Channel), CCRR
-90
5.0
5.0
16
-90
5.0
5.0
16
Source OFF Capacitance, C
f = 140kHz, V = 5V, V = V = 0V
IN
S(OFF)
S
D
Drain OFF Capacitance, C
Channel ON Capacitance,
D(OFF)
C
+ C
S(ON)
D(ON)
DIGITAL INPUT CHARACTERISTICS
Input Current with Voltage High, I
IH
V
V
V
= 2.4V
= 15V
= 0V
-1.0
-
-0.0004
0.003
-
1.0
-
-1.0
-
-0.0004
0.003
-
1.0
-
µA
µA
µA
IN
IN
IN
Input Current with Voltage Low, I
-1.0
-0.0004
-1.0
-0.0004
IL
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
-15
-
-
15
-15
-
-
15
V
Drain-Source ON Resistance, r
V
= ±10V, V = 0.8V (DG201A)
IN
115
175
115
200
Ω
DS(ON)
D
I
= 1mA, V = 2.4V (DG202)
S
IN
Source OFF Leakage Current, I
V
= 2.4V
V
V
V
V
= 14V, V = -14V
-
0.01
-0.02
0.01
1.0
-
-
0.01
-0.02
0.01
5.0
-
nA
nA
nA
nA
S(OFF)
D(OFF)
IN
(DG201A)
= 0.8V
S
S
S
S
D
= -14V, V = 14V
-1.0
-
-5.0
-
D
V
IN
(DG202)
Drain OFF Leakage Current, I
= -14V, V = 14V
1.0
-
5.0
-
D
= 14V, V = -14V
-1.0
-0.02
-5.0
-0.02
D
4-2
DG201A, DG202
o
Electrical Specifications V+ = 15V, V- = -15V, GND = 0V, T = 25 C (Continued)
A
“A” SUFFIX
“B” AND “C” SUFFIX
(NOTE 3)
(NOTE 3)
PARAMETER
TEST CONDITIONS
MIN
-
TYP
MAX MIN
TYP
MAX UNITS
Drain ON Leakage Current, I
(Note 5)
V
= 0.8V
V
V
= V = 14V
0.1
1.0
-
-
0.1
5.0
-
µA
µA
D(ON)
IN
(DG201A)
= 2.4V
D
D
S
= V = -14V
-1.0
-0.15
-5.0
-0.15
S
V
IN
(DG202)
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
All Channels ON or OFF
-
0.9
2
-
-
0.9
2
-
mA
mA
Negative Supply Current, I-
-1
-0.3
-1
-0.3
Electrical Specifications V+ = 15V, V- = -15V, GND = 0V, T Over Operating Temperature Range
A
“A” SUFFIX
(NOTE 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUT CHARACTERISTICS
Input Current with Voltage High, I
IH
V
V
V
= 2.4V
= 15V
= 0V
-10
-
-
-
-
-
10
-
µA
µA
µA
IN
IN
IN
Input Current with Voltage Low, I
-10
IL
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
-15
-
-
-
15
V
Drain-Source ON Resistance, r
V
= ±10V, V = 0.8V (DG201A)
IN
250
Ω
DS(ON)
D
I
= 1mA, V = 2.4V (DG202)
S
IN
Source OFF Leakage Current, I
V
V
= 2.4V (DG201A)
= 0.8V (DG202)
V
V
V
V
V
V
= 14V, V = -14V
-
-
-
-
-
-
-
100
nA
nA
nA
nA
µA
µA
S(OFF)
IN
IN
S
S
S
S
D
D
D
= -14V, V = 14V
-100
-
-
100
-
D
Drain OFF Leakage Current, I
= -14V, V = 14V
D
D(OFF)
= 14V, V = -14V
-100
-
D
Drain ON Leakage Current, I
(Note 5)
V
V
= 0.8V (DG201A)
= 2.4V (DG202)
= V = 14V
200
-
D(ON)
IN
IN
S
= V = -14V
-200
S
NOTES:
3. Typical values are for design aid only, not guaranteed and not subject to production testing.
4. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet.
5. I is leakage from driver into ON switch.
D(ON)
4-3
DG201A, DG202
Test Circuits and Waveforms
R
L
V
= V
S
O
LOGIC “0” = SWITCH ON
R
+ r
DS(ON)
L
15V
LOGIC†
3V
V+
INPUT
50%
SWITCH
INPUT
t < 20ns
r
SWITCH
OUTPUT
V
t < 20ns
f
S
D
1
1
V
= 2V
O
S
SWITCH
INPUT
V
R
1kΩ
C
L
35pF
S
L
IN
1
90%
90%
LOGIC
INPUT
SWITCH
OUTPUT
t
t
OFF
(REPEAT TEST FOR
IN , IN AND IN )
GND
ON
V-
-15V
2
3
4
†Logic shown for DG201A, invert for DG202.
FIGURE 1. t
ON
AND t
SWITCHING TEST CIRCUIT AND MEASUREMENT POINTS
OFF
∆V
O
R
S
S
D
X
X
V
O
SWITCH
OUTPUT
IN
X
C
L
= 1nF
V
S
IN
X
ON
ON
OFF
NOTES:
6. ∆V = Measured voltage error due to charge injection.
O
7. The error in coulombs is Q = C x ∆V .
L
O
FIGURE 2. CHARGE INJECTION TEST CIRCUIT AND MEASUREMENT POINTS
+15V
+15V
C
3
C
V+
V+
SIGNAL
GENERATOR
SIGNAL
GENERATOR
50Ω
V
V
S1
V
D1
S
V
S
V
S
IN
X
IN
0V,
2.4V
1
0V, 2.4V
NC
V
IN
IN
2
ANALYZER
CHAN A
ANALYZER
CHAN A
V
V
V
D2
S2
D
CHAN B
CHAN B
V-
GND
V-
GND
R
R
L
C
L
C
-15V
-15V
C = 0.001µF||0.1µF
Chip Capacitors
C = 0.001µF||0.1µF
Chip Capacitors
V
V
S
S1
OIRR = 20 Log
CCRR = 20 Log
-------
-----------
V
D
V
D2
FIGURE 3. OFF ISOLATION TEST CIRCUIT
FIGURE 4. CHANNEL TO CHANNEL CROSSTALK TEST
CIRCUIT
4-4
DG201A, DG202
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INDEX
INCHES MILLIMETERS
1 2
3
N/2
AREA
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
A2
A
-
SEATING
PLANE
B1
C
8, 10
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
5
eC
C
B
D1
E
5
eB
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in JE-
N
16
16
DEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
4-5
DG201A, DG202
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES MILLIMETERS
MIN
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.840
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
21.34
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
16
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
4-6
DG201A, DG202
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
10.50
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.3977
0.2914
-
-A-
o
0.4133 10.10
3
h x 45
D
0.2992
7.40
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
16
16
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
4-7
相关型号：
DG201ABJ-2
SPST, 4 Func, 1 Channel, CMOS, PDIP16, 0.300 INCH, PLASTIC, MO-058AB, MS-001AA, DIP-16
MAXIM
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