EL1509_07 [INTERSIL]
Medium Power Differential Line Driver; 中功率差动线路驱动器
| 型号： | EL1509_07 |
| 厂家： | 
Intersil |
| 描述： | Medium Power Differential Line Driver |
| 文件： | 总10页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL1509
®
Data Sheet
March 26, 2007
FN7015.2
Medium Power Differential Line Driver
Features
The EL1509 is a dual operational amplifier designed for
customer premise line driving in DMT ADSL solutions. This
device features a high drive capability of 250mA while
consuming only 7.1mA of supply current per amplifier and
operating from a single 5V to 12V supply. This driver
achieves a typical distortion of less than -85dBc, at 150kHz
into a 25Ω load. The EL1509 is available in the industry
standard 8 Ld SOIC as well as the thermally-enhanced 8 Ld
DFN package. Both are specified for operation over the full
-40°C to +85°C temperature range.
• Drives up to 250mA from a +12V supply
• 20V differential output drive into 100Ω
P-P
• -85dBc typical driver output distortion at full output at
150kHz
• Low quiescent current of 7.5mA per amplifier
• Pb-free plus anneal available (RoHS compliant)
Applications
• ADSL G.lite CO line driving
• ADSL full rate CPE line driving
• G.SHDSL, HDSL2 line driver
• Video distribution amplifier
• Video twisted-pair line driver
The EL1509 is ideal for ADSL, SDSL, HDSL2 and VDSL line
driving applications.
Ordering Information
PART
TAPE&
PKG.
PART NUMBER MARKING
REEL PACKAGE DWG. #
EL1509CS
1509CS
1509CS
-
7”
13"
-
8 Ld SOIC MDP0027
8 Ld SOIC MDP0027
8 Ld SOIC MDP0027
Pinouts
EL1509CS-T7
EL1509
(8 LD SOIC)
TOP VIEW
EL1509CS-T13 1509CS
EL1509CSZ
(See Note)
1509CSZ
8 Ld SOIC MDP0027
(Pb-Free)
OUTA
INA-
VS
1
2
3
4
8
7
6
5
EL1509CSZ-T7 1509CSZ
(See Note)
7”
8 Ld SOIC MDP0027
(Pb-Free)
-
OUTB
INB-
INB+
+
EL1509CSZ-T13 1509CSZ
(See Note)
13"
8 Ld SOIC MDP0027
(Pb-Free)
INA+
GND
-
EL1509CL
1509CL
1509CL
1509CL
-
8 Ld DFN
8 Ld DFN
8 Ld DFN
MDP0047
MDP0047
MDP0047
+
EL1509CL-T7
EL1509CL-T13
7"
13"
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
EL1509
(8 LD DFN)
TOP VIEW
VS
8
7
6
5
OUTA
1
2
3
4
INA-
OUTB
INB-
INB+
-
+
INA+
GND
-
AMP A
+
AMP B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004, 2007. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
EL1509
Absolute Maximum Ratings (T = +25°C)
A
V + Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . -0.3V to +14.6V
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-60°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
S
V
+ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V +
IN
S
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 75mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications
V = +12V, R = 1.5kΩ, R = 100Ω connected to mid supply, T = 25°C, unless otherwise specified.
S F L A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
HD
dG
dθ
-3dB Bandwidth
A
= +4
70
-85
MHz
dBc
%
V
Total Harmonic Distortion
Differential Gain
Differential Phase
Slewrate
f = 150kHz, V = 16V , R = 25Ω
P-P
O
L
A
= +2, R = 37.5Ω
0.15
0.1
V
L
A
= +2, R = 37.5Ω
°
V
L
SR
V
from -3V to +3V
350
500
V/µs
OUT
OUT
DC PERFORMANCE
V
Offset Voltage
-20
-10
0.7
20
10
mV
mV
MΩ
OS
ΔV
V
Mismatch
OS
OS
R
Transimpedance
V
from -4.5V to +4.5V
1.4
2.5
OL
INPUT CHARACTERISTICS
I +
Non-Inverting Input Bias Current
Inverting Input Bias Current
-5
5
µA
µA
µA
B
I -
-30
-30
30
30
B
ΔI -
I - Mismatch
B
B
e
Input Noise Voltage
-Input Noise Current
2.8
19
nV/ Hz
√
N
i
pA/ Hz
√
N
OUTPUT CHARACTERISTICS
V
Loaded Output Swing (single ended)
Output Current
V
V
= ±6V, R = 100Ω to GND
±4.8
±4.4
±5
V
V
OUT
S
S
L
= ±6V, R = 25Ω to GND
±4.7
450
L
I
R
= 0Ω
mA
OUT
L
SUPPLY
V
Supply Voltage
Supply Current
Single Supply
5
12
18
V
S
I
All Outputs at Mid Supply
14.2
mA
S
FN7015.2
March 26, 2007
2
EL1509
Typical Performance Curves
28
28
24
20
16
12
8
A =10
A =10
V
V
V =±6V
V =±6V
S
S
R =100Ω
R =100Ω
24
20
16
12
8
L
L
R =1kΩ
F
R =1.5kΩ
F
R =1.5kΩ
F
R =1kΩ
F
R =2kΩ
F
R =2kΩ
F
100K
1M
10M
100M
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. DIFFERENTIAL FREQUENCY RESPONSE vs R
(EL1509CS)
FIGURE 2. DIFFERENTIAL FREQUENCY RESPONSE vs R
(EL1509CL)
F
F
L
F
F
L
22
22
A =5
A =5
V
V
V =±6V
V =±6V
S
S
R =1kΩ
F
R =100Ω
R =100Ω
18
14
10
6
18
14
10
6
L
L
R =1kΩ
F
R =1.5kΩ
F
R =1.5kΩ
F
R =2kΩ
F
R =2kΩ
F
2
2
100K
1M
10M
100M
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE vs R
(EL1509CS)
FIGURE 4. DIFFERENTIAL FREQUENCY RESPONSE vs R
(EL1509CL)
22
22
A =5
A =5
V
V
C =22pF
L
V =±6V
V =±6V
S
S
C =22pF
L
18 R =100Ω
18 R =100Ω
L
L
R =1.5kΩ
R =1.5kΩ
F
F
C =10pF
L
C =10pF
L
14
10
6
14
10
6
C =0pF
L
C =0pF
L
2
2
100K
1M
10M
100M
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. DIFFERENTIAL FREQUENCY RESPONSE vs C
(EL1509CS)
FIGURE 6. DIFFERENTIAL FREQUENCY RESPONSE vs C
(EL1509CL)
FN7015.2
March 26, 2007
3
EL1509
Typical Performance Curves
55
-45
-50
-55
-60
-65
-70
-75
-80
-85
V =±2.5V
S
A =5
V
53
A =5
R =1.5kΩ
V
F
51
49
47
45
43
41
39
37
35
R =1.5kΩ
R =100Ω
F
L
R =100Ω
EL1509CL
L
f=1MHz
EL1509CS
HD3
HD2
5
2.5
3
3.5
4
4.5
5
5.5
6
1
1.5
2
2.5
3
3.5
(V)
4
4.5
5.5
±V (V)
V
S
OP-P
FIGURE 7. DIFFERENTIAL BANDWIDTH vs SUPPLY VOLTAGE
FIGURE 8. DIFFERENTIAL HARMONIC DISTORTION vs
DIFFERENTIAL OUTPUT VOLTAGE (ALL
PACKAGES)
-45
4
3
V =±6V
S
A =5
V
-50
A =5
V
R =1.5kΩ
F
R =1.5kΩ
R =100Ω
F
L
-55
R =100Ω
L
EL1509CS
2
f=1MHz
-60
-65
-70
-75
-80
-85
-90
1
HD3
0
EL1509CL
HD2
-1
-2
1
3
5
7
9
11 13 15 17 19
(V)
2.5
3
3.5
4
4.5
5
5.5
6
V
±V (V)
OP-P
S
FIGURE 9. DIFFERENTIAL PEAKING vs SUPPLY VOLTAGE
FIGURE 10. DIFFERENTIAL HARMONIC DISTORTION vs
DIFFERENTIAL OUTPUT VOLTAGE (ALL
PACKAGES)
-45
-45
A =5
A =5V
V
V
-50
-55
-60
-65
-70
-75
-80
-85
-90
R =1.5kΩ
R =1.5kΩ
F
F
-50
-55
-60
-65
-70
-75
-80
R =100Ω
R =100Ω
L
L
f=150kHz
f=1MHz
V =±2.5V
S
V =±2.5V
V =±6V
S
S
V =±6V
S
1
3
5
7
9
11 13 15 17 19 21
1
3
5
7
9
11 13 15 17 19
(V)
V
(V)
V
OP-P
OP-P
FIGURE 11. DIFFERENTIAL TOTAL HARMONIC DISTORTION
vs DIFFERENTIAL OUTPUT VOLTAGE (ALL
PACKAGES)
FIGURE 12. DIFFERENTIAL TOTAL HARMONIC DISTORTION
vs DIFFERENTIAL OUTPUT (ALL PACKAGES)
FN7015.2
March 26, 2007
4
EL1509
Typical Performance Curves
-10
-20
-30
-40
-50
100
10
1
IB-
B → A
-60
-70
A → B
-80
-90
E
N
IB+
-100
-110
10K
100K
1M
10M
100M
10
100
1K
10K 100K 1M
FREQUENCY (Hz)
10M 100M
FREQUENCY (Hz)
FIGURE 13. CHANNEL ISOLATION vs FREQUENCY
FIGURE 14. VOLTAGE AND CURRENT NOISE vs FREQUENCY
30
20
10
0
100
V =±12V
S
A =1
V
R =1.5kΩ
10
1
F
-10
-20
-30
0.1
PSRR-
100K
-40
-50
-60
-70
0.01
PSRR+
0.001
10K
1M
FREQUENCY (Hz)
10M
100M
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 15. POWER SUPPLY REJECTION vs FREQUENCY
FIGURE 16. OUTPUT IMPEDANCE vs FREQUENCY
0.06
0.05
10M
1M
50
0
GAIN
-50
0.04
PHASE
GAIN
100K
10K
1K
-100
-150
-200
-250
-300
0.03
0.02
0.01
0
PHASE
100
100
0
1
2
3
4
5
1K
10K
100K
1M
10M
100M
NUMBER OF 150Ω LOADS
FREQUENCY (Hz)
FIGURE 17. TRANSIMEDANCE (ROL) vs FREQUENCY
FIGURE 18. DIFFERENTIAL GAIN & PHASE
FN7015.2
March 26, 2007
5
EL1509
Typical Performance Curves
14.5
14
10
8
6
IB-
4
2
13.5
13
0
-2
-4
-6
-8
-10
IB+
12.5
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 19. SUPPLY CURRENT vs TEMPERATURE
5.2
FIGURE 20. INPUT BIAS CURRENT vs TEMPERATURE
520
510
500
490
480
470
460
450
440
R =100Ω
L
5.15
5.1
50.5
5
4.95
4.9
4.85
4.8
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 21. OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 22. SLEW RATE vs TEMPERATURE
16
14
12
10
8
7
6
5
4
3
2
1
6
0
4
-1
-2
-3
2
0
0
1
2
3
4
5
6
7
-50 -25
0
25
50
75 100 125 150
±V (V)
TEMPERATURE (°C)
S
FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 24. OFFSET VOLTAGE vs TEMPERATURE
FN7015.2
March 26, 2007
6
EL1509
Typical Performance Curves
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE
LAYER) TEST BOARD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3
2.5
2
781mW
1.5
1
0.5
0
-50 -25
0
25
50
75 100 125 150
0
25
50
75 85 100
125
150
TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 25. TRANSIMEDANCE vs TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
CONDUCTIVITY (4-LAYER) TEST BOARD (DFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5)
3.5
3
2.907W
2.5
2
1.5
1
1.136W
0.5
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Power Supply Bypassing and Printed Circuit
Board Layout
Applications Information
Product Description
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended. Lead lengths
should be as short as possible, below ¼”. The power supply
pins must be well bypassed to reduce the risk of oscillation.
A 1.0µF tantalum capacitor in parallel with a 0.01µF ceramic
capacitor is adequate for each supply pin.
The EL1509 is a dual operational amplifier designed for
customer premise line driving in DMT ADSL solutions. It is a
dual current mode feedback amplifier with low distortion
while drawing moderately low supply current. It is built using
Elantec's proprietary complimentary bipolar process and is
offered in industry standard pin-outs. Due to the current
feedback architecture, the EL1509 closed-loop 3dB
For good AC performance, parasitic capacitances should be
kept to a minimum, especially at the inverting input. This
implies keeping the ground plane away from this pin. Carbon
resistors are acceptable, while use of wire-wound resistors
should not be used because of their parasitic inductance.
Similarly, capacitors should be low inductance for best
performance.
bandwidth is dependent on the value of the feedback
resistor. First the desired bandwidth is selected by choosing
the feedback resistor, R , and then the gain is set by picking
F
the gain resistor, R . The curves at the beginning of the
G
Typical Performance Curves section show the effect of
varying both R and R . The 3dB bandwidth is somewhat
F
G
dependent on the power supply voltage.
FN7015.2
March 26, 2007
7
EL1509
Capacitance at the Inverting Input
Supply Voltage Range
Due to the topology of the current feedback amplifier, stray
capacitance at the inverting input will affect the AC and
transient performance of the EL1509 when operating in the
non-inverting configuration.
The EL1509 has been designed to operate with supply
voltages from ±2.5V to ±6V. Optimum bandwidth, slew rate,
and video characteristics are obtained at higher supply
voltages. However, at ±2.5V supplies, the 3dB bandwidth at
A = +2 is a respectable 40MHz.
V
In the inverting gain mode, added capacitance at the
inverting input has little effect since this point is at a virtual
ground and stray capacitance is therefore not “seen” by the
amplifier.
Single Supply Operation
If a single supply is desired, values from +5V to +12V can be
used as long as the input common mode range is not
exceeded. When using a single supply, be sure to either 1)
DC bias the inputs at an appropriate common mode voltage
and AC couple the signal, or 2) ensure the driving signal is
within the common mode range of the EL1509.
Feedback Resistor Values
The EL1509 has been designed and specified with R =
F
1.5kΩ for A = +5. This value of feedback resistor yields
V
extremely flat frequency response with little to no peaking
out to 50MHz. As is the case with all current feedback
amplifiers, wider bandwidth, at the expense of slight
peaking, can be obtained by reducing the value of the
feedback resistor. Inversely, larger values of feedback
resistor will cause rolloff to occur at a lower frequency. See
the curves in the Typical Performance Curves section which
show 3dB bandwidth and peaking vs. frequency for various
feedback resistors and various supply voltages.
ADSL CPE Applications
The EL1509 is designed as a line driver for ADSL CPE
modems. It is capable of outputting 250mA of output current
with a typical supply voltage headroom of 1.3V. It can
achieve -85dBc of distortion at low 7.1mA of supply current
per amplifier.
The average line power requirement for the ADSL CPE
application is 13dBm (20mW) into a 100Ω line. The average
Bandwidth vs Temperature
line voltage is 1.41V
. The ADSL DMT peak to average
RMS
Whereas many amplifier's supply current and consequently
3dB bandwidth drop off at high temperature, the EL1509 was
designed to have little supply current variations with
temperature. An immediate benefit from this is that the 3dB
bandwidth does not drop off drastically with temperature.
ratio (crest factor) of 5.3 implies peak voltage of 7.5V into the
line. Using a differential drive configuration and transformer
coupling with standard back termination, a transformer ratio
of 1:2 is selected. The circuit configuration is as shown
below.
12.5
12.5
+
-
TX1
1.5k
AFE
100
464Ω
1:2
+
-
1.5k
FN7015.2
March 26, 2007
8
EL1509
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7015.2
March 26, 2007
9
EL1509
Dual Flat No-Lead Package Family (DFN)
MDP0047
A
DUAL FLAT NO-LEAD PACKAGE FAMILY (JEDEC REG: MO-229)
D
MILLIMETERS
N
N-1
0.075
2X
C
SYMBOL
DFN8
0.85
0.02
0.30
0.20
4.00
3.00
4.00
2.20
0.80
0.50
0.10
DFN10
0.90
0.02
0.25
0.20
3.00
2.25
3.00
1.50
0.50
0.50
0
TOLERANCE
±0.10
A
A1
b
PIN #1
I.D.
E
+0.03/-0.02
±0.05
c
Reference
Basic
1
2
D
0.075
2X
C
B
D2
E
Reference
Basic
TOP VIEW
E2
e
Reference
Basic
(D2)
N-1
4
L1
N
L
±0.10
(N LEADS)
L
L1
Maximum
Rev. 2 2/07
(E2)
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Exposed lead at side of package is a non-functional feature.
PIN #1 I.D.
3
3. Bottom-side pin #1 I.D. may be a diepad chamfer, an extended
tiebar tab, or a small square as shown.
2
1
5
e
4. Exposed leads may extend to the edge of the package or be
pulled back. See dimension “L1”.
0.10 M
C A B
b
BOTTOM VIEW
5. Inward end of lead may be square or circular in shape with radius
(b/2) as shown.
6. N is the total number of leads on the device.
0.10
C
C
SEATING
PLANE
0.08
C
SEE DETAIL "X"
(N LEADS
& EXPOSED PAD)
2
C
(c)
A
A1
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7015.2
March 26, 2007
10
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