EL4581 [INTERSIL]
Sync Separator, 50% Slice, S-H, Filter; 同步分离， 50％的切片， S-H ，过滤
| 型号： | EL4581 |
| 厂家： | 
Intersil |
| 描述： | Sync Separator, 50% Slice, S-H, Filter |
| 文件： | 总9页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL4581
®
Data Sheet
August 16, 2002
FN7172
Sync Separator, 50% Slice, S-H, Filter
Features
The EL4581 extracts timing informa-
tion from standard negative going
video sync found in NTSC, PAL, and
• NTSC, PAL and SECAM sync separation
• Single supply, +5V
• Precision 50% slicing, internal caps
• Built-in color burst filter
SECAM broadcast systems. It can also be used in non stan-
dard formats and with computer graphics systems at higher
scan rates, by adjusting a single external resistor. When the
input does not have correct serration pulses in the vertical
interval, a default vertical output is produced.
• Decodes non-standard verticals
• Pin compatible with LM1881
• Low power
Outputs are composite sync, vertical sync, burst/back porch
output, and odd/even output. The later operates only in inter-
laced scan formats.
• Typically 1.5mA supply current
• Resistor programmable scan rate
• Few external components
The EL4581 provides a reliable method of determining cor-
rect sync slide level by setting it to the mid-point between
sync tip and blanking level at the back porch. This 50% level
is determined by two internal self timing sample and hold cir-
cuits that track sync tip and back porch levels. This also
provides a degree of hum and noise rejection to the input sig-
• Available in 8-pin PDIP and SO packages
Applications
• Video special effects
• Video test equipment
• Video distribution
• Displays
nal, and compensates for varying input levels of 0.5
to
P-P
2.0V
.
P-P
A built in linear phase, third order, low pass filter attenuates
the chroma signal in color systems to prevent incorrectly set
color burst from disturbing the 50% sync slide.
• Imaging
This device may be used to replace the industry standard
LM1881, offering improved performance and reduced power
consumption.
• Video data capture
• Video triggers
The EL4581 video sync separator is manufactured using
Elantec’s high performance analog CMOS process.
Ordering Information
PART
NUMBER
TEMP.
RANGE
Pinout
EL4581
PACKAGE
8-Pin PDIP
8-Pin SO
PKG. NO.
MDP0031
MDP0027
(8-Pin SO, DIP)
TOP VIEW
EL4581CN
EL4581CS
-40°C to +85°C
-40°C to +85°C
COMPOSITE
SYNC OUT
1
2
3
4
8
7
6
5
VDD 5V
Demo Board
A dedicated demo board is not available. However, this
device can be placed on the EL4584/5 Demo Board.
COMPOSITE
VIDEO IN
ODD/EVEN OUTPUT
RSET
VERTICAL
SYNC OUT
BURST/BACK
PORCH OUTPUT
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
1
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303. Manufactured under License, U.S. Patents 5,486,869; 5,754,250.
EL4581
Absolute Maximum Ratings (T = 25 °C)
A
V
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CC
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V +0.5V
CC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
DC Electrical Specifications Unless otherwise state V = 5V, T = 25°C, R
= 680kΩ.
MIN
0.75
1.3
DD
A
SET
PARAMETER
DESCRIPTION
= 5V (Note 1)
DD
TEMP
TYP
1.7
1.5
10
MAX
3
UNIT
mA
V
I
V
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
DD
Clamp Voltage
Pin 2, Unloaded
Pin 2 = 2V
1.9
20
Discharge Current
Clamp Charge Current
Ref Voltage
6
µA
mA
V
Pin 2, V = 1V
IN
2
3
Pin 6, V
= 5V (Note 2)
1.5
1.8
2.1
DD
V
V
Output Low Voltage
Output High Voltage
I
I
I
= 1.6mA
= -40µA
= -1.6mA
800
mV
V
OL
OL
OH
OH
4
OH
2.4
V
NOTES:
1. No video signal, outputs unloaded.
2. Tested for V 5V ±5% which guarantees timing of output pulses over this range.
DD
Dynamic Specifications
V
= 5V, I pk-pk video, T = 25°C, C = 15pF, I
= -1.6mA, I = 1.6mA. Signal voltages are peak to peak.
OL
DD
V
A
L
OH
PARAMETER
DESCRIPTION
TEMP
MIN
190
2.5
40
TYP
230
3.5
55
MAX
300
4.5
UNIT
µs
Vertical Sync Width, t
(Note 1)
(Note 1)
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
VS
Burst/Back Porch Width, t
µs
B
Vertical Sync Default Delay t
70
µs
VSD
Filter Attenuation
F
= 3.4MHz (Note 2)
24
dB
ns
IN
Composite Sync Prop Delay
Input Dynamic Range
Slice Level
V
- Composite Sync (Note 1)
260
400
2
IN
p-p NTSC Signal (Note 3)
0.5
V
Input Voltage = 1V
(Note 4)
40%
40%
50%
50%
60%
60%
P-P
NOTES:
1. C/S, Vertical and Burst outputs are all active low - V
= 2.4V, V = 0.8V.
OL
OH
2. Attenuation is a function of R
(PIN6).
SET
3. Typical min. is 0.3V
.
P-P
4. Refers to threshold level of sync. tip to back porch amplitude.
2
EL4581
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
1
2
3
4
5
6
Composite Sync Out
Composite Video in
Vertical Sync Out
GND
Composite sync pulse output. Sync pulses start on a falling edge and end on a rising edge.
AC coupled composite video input. Sync tip must be at the lowest potential (Positive picture phase).
Vertical sync pulse output. The falling edge of Vert Sync is the start of the vertical period.
Supply ground.
Burst/Back Porch Output
Burst/Back porch output. Low during burst portion of composite video.
R
(Note 1)
An external resistor to ground sets all internal timing. 681k, 1% resistor will provide correct timing
for NTSC signals.
SET
7
Odd/Even Output
Odd/Even field output. Low during odd fields, high during even fields. Transitions occur at start of
Vert Sync pulse.
8
V
5V
Positive supply. (5V)
DD
NOTE 1. R
must be a 1% resistor.
SET
3
EL4581
Typical Performance Curves
R
vs Horizontal
Back Porch Clamp
Vertical Pulse Width
vs R
SET
Frequency
On Time vs R
SET
SET
Vertical Default Delay
Vertical Pulse Width
vs Temperature
Supply Current
vs Temperature
Time vs R
SET
Input Signal = 300mV
P-P
EL4581 Filter Characteristic
Constant Delay 240ns
Package Power Dissipation vs Ambient Temperature
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
JEDEC JESD51-7 High Effective Thermal Conductivity Test Board
1.8
1.6
2
1.8
1.6
1.4
1.2
1
1.471W
PDIP8
1.4
1.2
1
1.25W
PDIP8
θ
=85°C/W
JA
θ
=100°C/W
JA
781mW
1.136
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
SO8
SO8
θ
=110°C/W
JA
θ
=160°C/W
JA
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
Ambient Temperature (°C)
4
EL4581
Timing Diagrams
NOTES:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
d. Odd-even output is low for even field, and high for odd field.
e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts
on the rising edge of the serration pulse (with propagation delay).
FIGURE 1.
5
EL4581
Timing Diagrams (Continued)
FIGURE 2.
6
EL4581
Timing Diagrams (Continued)
FIGURE 3.
FIGURE 4. STANDARD (NTSC INPUT) H. SYNC DETAIL
7
EL4581
fixed level above the clamp voltage V . The output of C2
initiates the timing one-shots for gating the sample and hold
Description of Operation
R1
A simplified block schematic is shown in Figure 2. The follow-
ing description is intended to provide the user with sufficient
information to be able to understand the effects that the
external components and signal conditions have on the out-
puts of the integrated circuit.
circuits. The sample of the sync tip is delayed by 0.8µs to
enable the actual sample of 2µs to be taken on the optimum
section of the sync. pulse tip. The acquisition time of the cir-
cuit is about three horizontal lines. The double poly CMOS
technology enables long time constants to be achieved with
small high quality on-chip capacitors. The back porch voltage
is similarly derived from the trailing edge of sync, which also
serves to cut off the tip sample if the gate time exceeds the
tip period. Note that the sample and hold gating times will
The video signal is AC coupled to pin 2 via the capacitor C ,
1
nominally 0.1µF. The clamp circuit A1 will prevent the input
signal on pin 2 going any more negative than 1.5V, the value
of reference voltage V . Thus the sync tip, the most nega-
R1
tive part of the video waveform, will be clamped at 1.5V. The
track RSET through I
.
OT
The 50% level of the sync tip is derived, through the resistor
divider R1 and R2, from the sample and held voltages V
current source I , nominally 10µA, charges the coupling
1
capacitor during the remaining portion of the H line, approxi-
mately 58µs for a 15.75kHz timebase. From I • t = C • V, the
video time-constant can be calculated. It is important to note
that the charge taken from the capacitor during video must
be replaced during the sync tip time, which is much shorter,
(ratio of x 12.5). The corresponding current to restore the
charge during sync will therefore be an order of magnitude
TIP
and V , and applied to the plus input of comparator C1.
BP
This comparator has built in hysteresis to avoid false trigger-
ing. The output of C2 is a digital 5V signal which feeds the
C/S output buffer B1 and the other internal circuit blocks, the
vertical, back porch and odd/even functions.
higher, and any resistance in series with C will cause sync
The vertical circuit senses the C/S edges and initiates an
integrator which is reset by the shorter horizontal sync pulses
but times out the longer vertical sync. pulse widths. The
I
tip crushing. For this reason, the internal series resistance
has been minimized and external high resistance values in
series with the input coupling capacitor should be avoided.
The user can exercise some control over the value of the
input time constant by introducing an external pull-up resis-
tance from pin 2 to the 5V supply. The maximum voltage
internal timing circuits are referenced to I
and V , the
OT
R3
time-out period being inversely proportional to the timing cur-
rent. The vertical output pulse is started on the first serration
pulse in the vertical interval and is then self-timed out. In the
absence of a serration pulse, an internal timer will default the
start of vertical.
across the resistance will be V
less 1.5V, for black level.
DD
For a net discharge current greater than zero, the resistance
should be greater than 450k. This will have the effect of
increasing the time constant and reducing the degree of pic-
The back porch is triggered from the sync tip trailing edge
and initiates a one-shot pulse. The period of this pulse is
ture tilt. The current source I directly tracks reference
1
again a function of I
and will therefore track the scan rate
OT
current I and thus increases with scan rate adjustment, as
TR
set by R
.
SET
explained later.
The odd/even circuit (O/E) comprises of flip flops which track
the relationship of the horizontal pulses to the leading edge
of the vertical output, and will switch on every field at the start
of vertical. Pin 7 is high during the odd field.
The signal is processed through an active 3 pole filter (F1)
designed for minimum ripple with constant phase delay. The
filter attenuates the color burst by 24dB and eliminates fast
transient spikes without sync crushing. An external filter is
not necessary. The filter also amplifies the video signal by
6dB to improve the detection accuracy. Note that the filter
Loss of video signal can be detected by monitoring the C/S
output. The 50% level of the previous video signal will remain
held on the S/H capacitors after the input video signal has
gone and the input on pin 2 has defaulted to the clamp volt-
age. Consequently the C/S output will remain low longer than
the normal vertical pulse period. An external timing circuit
could be used to detect this condition.
cut-off frequency is a function of R
through I
and is
OT
SET
proportional to I
.
OT
Internal reference voltages (block V
) with high immunity
REF
to supply voltage variation are derived on the chip. Refer-
ence V with op-amp A2 forces pin 6 to a reference voltage
R4
of 1.7V nominal. Consequently, it can be seen that the exter-
nal resistance R
will determine the value of the reference
SET
current I . The internal resistance R3 is only about 6kΩ,
TR
much less than R
. All the internal timing functions on the
SET
chip are referenced to I and have excellent supply voltage
TR
rejection.
Comparator C2 on the input to the sample and hold block
(S/H) compares the leading and trailing edges of the sync.
pulse with a threshold voltage V which is referenced at a
R2
8
EL4581
Block Diagram
*Note:
RSET must be
a 1% resistor.
FIGURE 5. STANDARD (NTSC INPUT) H. SYNC DETAIL
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
相关型号：
©2020 ICPDF网 联系我们和版权申明