概述
数据手册EL5000A 概述
High Voltage TFT-LCD Logic Driver 高压TFT -LCD逻辑驱动器
EL5000A 数据手册
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PDF下载EL5000A
®
Data Sheet
July 28, 2005
FN6167.0
High Voltage TFT-LCD Logic Driver
Features
• 3.3V logic supply
The EL5000A is high voltage TFT-LCD logic driver with
+40V and -30V output swing capability. Manufactured using
the Intersil proprietary monolithic high voltage bipolar
process, it is capable of delivering 100mA output peak
current into 5nF of capacitive load. To simplify external
circuitry, the EL5000A integrates additional logic circuits.
• 40V V
ON
output high level
output low level
• -30V V
OFF
• 166kHz input logic frequency
• 100mA output peak current
• 10mA output continuous current
• TTL-compatible logic input
The EL5000A can operate on 3.3V logic supply and high
voltage -30V to +40V output supplies. The EL5000A is
available in TSSOP-16 package. It is specified for operation
over the -20°C to +85°C extended temperature range.
• Pb-free plus anneal available (RoHS compliant)
Ordering Information
Applications
• TFT-LCD panels
PART
TAPE &
REEL
NUMBER
PACKAGE
16-Pin TSSOP
16-Pin TSSOP
PKG. DWG. #
MDP0044
MDP0044
MDP0044
MDP0044
EL5000AER
-
7”
13”
-
Pinout
EL5000AER-T7
EL5000A
(16-PIN TSSOP)
TOP VIEW
EL5000AER-T13 16-Pin TSSOP
EL5000AERZ
(See Note)
16-Pin TSSOP
(Pb-Free)
VON1
CKV
1
2
3
4
5
6
7
8
16 VDD
15 DISH
14 OECON
13 GND
12 STV
11 OE
EL5000AERZ-T7 16-Pin TSSOP
7”
MDP0044
MDP0044
(See Note)
(Pb-Free)
CKVCS
NC
EL5000AERZ-
T13 (See Note)
16-Pin TSSOP
(Pb-Free)
13”
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CKVBCS
CKVB
STVP
10 CPV
VOFF
9 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5000A
Absolute Maximum Ratings (T = 25°C)
A
V
V
V
V
V
V
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44V
I
I
I
(peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
(continuos), CKV, CKVB, or STVP . . . . . . . . . . . . . . . . . 30mA
(continuous, total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
DD
ON
OFF
OUT
OUT
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -33V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V
T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20°C to +85°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20°C to +150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CL
AMBIENT
, V
, V
,
T
T
P
CKV CKVB STVP
JUNCTION
STORAGE
DISSIPATION
, V , V
. . . . . . . .V
+ 1 diode/V
- 1 diode
CKVCS CKVBCS STVP
ON
. . . . . . . V
OFF
+ 1 diode/GND - 1 diode
, V , V , V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CPV OE STV OECON
DD
. . . . . . . . . . . . . . . . . . . . . . . GND + 1 diode/V
- 1 diode
OFF
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . See Curves
DISH
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications
PARAMETER
V
= 20V, V
OFF
= -14V, V = 3.3V, 4.7nF Load on STV, CKV, CKVB, unless otherwise specified.
DD
ON
DESCRIPTION
Supply Current
CONDITION
MIN
TYP
1.1
1.5
0.25
0.45
0.25
-0.7
130
0
MAX
UNIT
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
I
I
I
I
I
I
V
V
V
All inputs low
VDD
DD
CPV = 3.1V, other inputs low
All inputs low
0.7
2.5
Supply Current
VON
VOFF
STV
CPV
OE
ON
OFF
CPV = 3.1V, other inputs low
All inputs low
0.2
0.9
Supply Current
CPV = 3.1V, other inputs low
STV = 3.1V
-1.25
25
-0.30
180
1
STV Input Current
CPV Input Current
OE Input Current
STV = 0.2V
-1
CPV = 3.1V
20
60
90
CPV = 0.2V
-1
0
1
OE = 0.2V
-1
0
1
OE = 3.1V, OECON = 0.2V
OE = 3.1V, OECON = 3.1V
OECON - 0.2V, OE = 3.1V
OECON - 0.2V, OE = 0.2V
200
-1
450
0
700
1
I
OECON Input Current
-40
-1
-25
0
-5
OECON
1
V
V
V
V
V
V
+
CKV Positive Output Swing
CKV Negative Output Swing
CKVB Positive Output Swing
CKVB Negative Output Swing
STVP Positive Output Swing
STVP Negative Output Swing
V
V
V
V
V
V
= +20V, 1mA output current
19.1
-13.1
19.1
-13.1
19.0
-13.1
19.3
-13.3
19.3
-13.3
19.2
-13.3
3
19.5
-13.5
19.5
-13.5
19.4
-13.5
CKV
CKV
ON
= -14V, 1mA output current
V
OFF
+
= +20V, 1mA output current
V
CKVB
ON
= -14V, 1mA output current
V
CKVB
OFF
+
= +20V, 1mA output current
V
STVP
ON
= -14V, 1mA output current
V
STVP
OFF
R
C
CPV, OE, STV Input Resistance
CPV, OE, STV Input Capacitance
CKV Rise Time
kΩ
pF
µs
µs
µs
µs
µs
µs
IN
1.5
0.5
0.75
0.5
0.75
1.6
1.6
IN
T -CKV
0.3
0.5
0.3
0.5
1.2
1.2
0.7
1
R
T -CKV
CKV Fall Time
F
T -CKVB
CKVB Rise Time
0.7
1
R
T -CKVB
CKVB Fall Time
F
T -STVP
STVP Rise Time
2.4
2.4
R
T -STVP
STVP Fall Time
F
FN6167.0
2
July 28, 2005
EL5000A
Electrical Specifications
V
= 20V, V
OFF
= -14V, V = 3.3V, 4.7nF Load on STV, CKV, CKVB, unless otherwise specified. (Continued)
ON
DD
PARAMETER
DESCRIPTION
CKV Rising Edge Delay Time
CKV Falling Edge Delay Time
CONDITION
MIN
0.5
0.7
0.5
0.7
1.3
1.2
1.6
3.4
1.6
3.4
TYP
0.9
1.1
0.9
1.1
1.75
1.7
2.3
4.1
2.3
4.1
MAX
1.3
1.5
1.3
1.5
2.2
2
UNIT
µs
T -CKV+
D
T -CKV-
µs
D
T -CKVB+
CKVB Rising Edge Delay Time
CKVB Falling Edge Delay Time
STVP Rising Edge Delay Time
STVP Falling Edge Delay Time
CKV_CS Rising Edge Delay Time
CKV_CS Falling Edge Delay Time
µs
D
T -CKVB-
µs
D
T -STVP+
µs
D
T -STVP-
µs
D
T -CKV_CS+
2.9
4.8
2.9
4.8
µs
D
T -CKV_CS-
µs
D
T -CKVB_CS+ CKVB_CS Rising Edge Delay Time
µs
D
T -CKVB_CS- CKVB_CS Falling Edge Delay Time
D
µs
Typical Performance Curves
1.5
500
V
V
=20V
V
=3.3V
CC
ON
OFF
=-14V
V
=-14V
OFF
1.25
1
400
300
200
100
0
CPV INPUT HIGH
ALL INPUTS LOW
0.75
0.5
0.25
0
0
1
2
3
4
5
0
10
20
30
(V)
40
50
V
(V)
V
ON
CC
FIGURE 1. V SUPPLY CURRENT vs V
SS
FIGURE 2. V
1.5
DC SUPPLY CURRENT vs V
ON
CC
ON
800
V
V
=20V
ON
=-14V
OFF
1.25
1
CPV INPUT HIGH
600
FALL
RISE
400
0.75
0.5
0.25
0
ALL INPUTS LOW
200
0
V
V
=3.3V
=20V
CC
ON
DELAY FROM CPV INPUT TO CKV OR
CKVB REACHING 50% OF FINAL VALUE
-35
-30
-25
-20
-15
(V)
-10
-5
0
0
1K
2K
3K
4K
5K
V
LOAD CAPACITANCE (pF)
OFF
FIGURE 3. V
DC SUPPLY CURRENT vs V
FIGURE 4. CLOCK DELAY vs LOAD CAPACITOR
OFF
OFF
FN6167.0
July 28, 2005
3
EL5000A
Typical Performance Curves (Continued)
1.5
1.5
1.25
1
V
V
=40V
V
=20V
ON
ON
OFF
=-20V
V
=-14V
OFF
1.25
1
FALL
RISE
FALL
RISE
0.75
0.5
0.25
0
0.75
0.5
0.25
0
DELAY FROM CPV INPUT TO CKV OR
CKVB REACHING 50% OF FINAL VALUE
4.7nF LOAD CAPACITORS
-25 25
AMBIENT TEMPERATURE (°C)
0
1K
2K
3K
4K
5K
75
125
LOAD CAPACITANCE (pF)
FIGURE 5. CLOCK DELAY vs LOAD CAPACITOR
1.4
FIGURE 6. CLOCK DELAY vs TEMPERATURE
1K
V
V
V
=3.3V
=20V
V
V
V
=3.3V
=20V
CC
CC
ON
OFF
ON
OFF
=-14V
=-14V
800
600
400
200
0
1.2
1
0.8
0.6
-25
25
75
125
-25
25
75
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 7. V
SUPPLY CURRENT vs TEMPERATURE
FIGURE 8. DC SUPPLY CURRENTS vs TEMPERATURE
750
CC
500
400
300
200
100
0
500
250
CKV, CKVB, AND STVP OUTPUTS
5mA LOAD
0
-100
-25
25
75
125
-25
25
75
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 9. INPUT BIAS CURRENTS vs TEMPERATURE
FIGURE 10. OUTPUT SWING HEADROOM vs TEMPERATURE
FN6167.0
4
July 28, 2005
EL5000A
Typical Performance Curves (Continued)
1400
800
600
400
200
0
V
V
=40V
V
=20V
ON
ON
=-20V
V
=-14V
OFF
OFF
1200
1000
800
600
400
200
0
R
=500Ω
R
=500Ω
CS
CS
4700pF
1000pF
4700pF
1000pF
220pF
220pF
0
0
100
150
200
0
0
100
150
200
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
FIGURE 11. POWER CONSUMPTION vs FREQUENCY AND
LOAD
FIGURE 12. POWER CONSUMPTION vs FREQUENCY AND
LOAD
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
CONDUCTIVITY TEST BOARD
1.2
1.8
1.6
1
1.4
1.2
1
1.289W
845mW
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN6167.0
July 28, 2005
5
EL5000A
Pin Descriptions
PIN NUMBER
PIN NAME
VON
PIN FUNCTION
1
2
Positive supply
CKV
High voltage output, scan clock out
Discharge switch input, CKV charge share
No connect
3
CKVCS
NC
4
5
CKVBCS
CKVB
STVP
VOFF
GND
Discharge switch input, CKVB charge share
High voltage output, scan clock even
High voltage output, scan start pulse
Negative supply
6
7
8
9
Ground
10
11
12
13
14
15
16
CPV
H sync timing, H sync clock 1
Writing timing, H sync clock 2
V sync timing, V sync
OE
VTS
GND
Ground, logic return
OECON
DISH
VDD
OE disable input, OE blank
Discharge function input, V
Logic power supply
discharge
OFF
FN6167.0
6
July 28, 2005
EL5000A
EL5000A
FIGURE 15. EL5000A SYSTEM BLOCK DIAGRAM
Application Information
General Description
C capacitors model the capacitive loading appeared at the
L
inputs of the TFT-LCD panel for the CKV and the CKVB
The EL5000A is a high performance 70V TFT-LCD row
driver. It level shifts TTL level timing signals from the video
source into 70V peak to peak output voltage. Its output is
capable of delivering 100mA peak current into 1nF of
capacitive load. It also incorporates logic to control the
output timings. The logic timing control circuit is powered
from 3.3V supply. Figure 15 shows the system block
diagram.
signals. The C is typically between 1nF and 5nF.
L
In addition to switches SW1, SW2, SW3, and SW4, a fifth
switch is added to reduce the power dissipation and shape
the output waveform. Figure 17 shows the location of the
additional SW5 switch.
Input Signals
SW1
SW2
The device performs beside of level transformation also logic
operation between the input signals:
CKV
CKVB
r
SW5
Rd
r
• STV - Vertical Sync Timing signal, frequency range around
60Hz
CL
CL
• CPV - Horizontal Sync Timing signal, frequency range up
to 166kHz
SW3
SW4
• OE - Output Enable Write Signal, frequency range up to
166kHz
FIGURE 17. SW5 SWITCH LOCATION
Output Signals
The output signals, CKV and CKVB are generated by
EL5000A internal switches. Figure 16 depicts the simplified
schematic of the output stage and interface.
In reality, each switch consists of two such switches, one for
the positive discharge and one for the negative discharge,
see Figure 18.
FIGURE 18. BI-DIRECTIONAL SWITCHES
Due to the actual solid-state construction of the switches, the
capacitors C does not get discharged entirely. The amount
L
of left over charges depends on the value of the voltages of
V
and V on the capacitors.
FIGURE 16. SIMPLIFIED SCHEMATIC OF OUTPUT STAGE
ON
OFF
FN6167.0
7
July 28, 2005
EL5000A
Internal Logic Block Diagram
Figures 19 and 20 show the internal block diagram. In order
to reduce power dissipation, most of the logic circuitry is
powered from 3.3V logic supply. The output of the 3.3V logic
is level-shifted to drive the output switches.
FIGURE 19. INTERNAL LOGIC BLOCK DIAGRAM
FIGURE 20. INTERNAL LOGIC BLOCK DIAGRAM AND OUTPUT SWITCHES
FN6167.0
8
July 28, 2005
EL5000A
Output Waveforms
Figure 21 shows a typical CKV and CKVB output
Figure 22 shows the delay time between the incoming
waveforms. The output droop rate depends on the external
discharge resistor value and the output capacitor load.
horizontal sync timing pulse CPV and the generated output
pulses. ∆t is dependent mainly on the value of C . Figure 23
L
shows the effect of STV.
CKV
CKV
CKVB
STV
CKVB
CPV
FIGURE 21. CKV AND CKVB OUTPUT WAVEFORMS
FIGURE 23. EFFECT OF STV
CKV
Auxiliary Functions
CKVB
DISH: It discharges V
when the logic power voltage level
OFF
drops out, when 'DISH' is < -0.6V (V
system power turns
CC
is connected to ground level by 1kΩ.
off), V
OFF
OECON: It provides continuos polarity changes to the
TFT-LCD panel during the vertical blanking.
CPV
FIGURE 22. CPV TO CKV/CKVB DELAY
FIGURE 24. TYPICAL APPLICATION CIRCUIT
FN6167.0
July 28, 2005
9
EL5000A
Power Dissipation
+40V
The dissipated power in R and R could calculated as
3
6
follows:
23V
We assume that:
+17 V
• V
• V
= 40V
ON
+3.3 V
0 V
23V
= -20V
OFF
• H sync timing frequency = 60kHz
• C = 5nF
L
-20V
FIGURE 25.
The value of V , the left over voltage in the capacitors in that
L
case is 23V for the positive discharge and 3.3V for the
negative discharge.
The voltage change across the capacitor is therefore 23V,
see Figure 25.
The stored energy in the capacitor is:
2
2
-9
1/2 × V C = 1/2 × 23 × 5 × 10 = 132µW
The energy which is stored in the capacitor will be
dissipated on the resistor see Figure 26. The switch will
close 2 x 60,000 in every second.
FIGURE 26.
For different values of V , V
, C and H sync timing
L
ON OFF
frequency, the worst case dissipation can be calculated in a
similar matter. The value of the R and R must be selected
Since the process will be repeated 2 times, for the CKV and
the CKVB. In 0,000 cycles per second the power dissipation
3
6
such that the capacitor C is discharged via R or R resistor
L
3
6
in R and R becomes:
3
6
in one half period of the H sync timing.
-6
3
2 × 1.32 × 10 × 60 = 160mW
Figures 11 and 12 show the total power dissipation over a
range of possible voltages, operating frequencies and loads.
Care should be taken to prevent the power from exceeding
the maximum rating of the package, as shown in Figure 13.
FN6167.0
10
July 28, 2005
EL5000A
Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil
website at http://www.intersil.com/design/packages
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6167.0
11
July 28, 2005
EL5000A 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| EL5000AER | INTERSIL | High Voltage TFT-LCD Logic Driver | 获取价格 |
|
| EL5000AER-T13 | INTERSIL | High Voltage TFT-LCD Logic Driver | 获取价格 |
|
| EL5000AER-T7 | INTERSIL | High Voltage TFT-LCD Logic Driver | 获取价格 |
|
| EL5000AERZ | INTERSIL | High Voltage TFT-LCD Logic Driver | 获取价格 |
|
| EL5000AERZ-T13 | INTERSIL | High Voltage TFT-LCD Logic Driver | 获取价格 |
|
| EL5000AERZ-T7 | INTERSIL | High Voltage TFT-LCD Logic Driver | 获取价格 |
|
| EL5000AERZT13 | INTERSIL | High Voltage TFT-LCD Logic Driver | 获取价格 |
|
| EL5000A_08 | INTERSIL | High Voltage TFT-LCD Logic Driver | 获取价格 |
|
| EL5001 | INTERSIL | 6-Channel Clock Driver | 获取价格 |
|
| EL5001IL | INTERSIL | 6-Channel Clock Driver | 获取价格 |
|
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