EL5103IWZ-T7A [INTERSIL]
400MHz Slew Enhanced VFAs; 400MHz的压摆增强的挥发性脂肪酸
| 型号： | EL5103IWZ-T7A |
| 厂家： | 
Intersil |
| 描述： | 400MHz Slew Enhanced VFAs |
| 文件： | 总17页 (文件大小：1735K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5102, EL5103, EL5202, EL5203, EL5302
®
Data Sheet
June 23, 2006
FN7331.6
400MHz Slew Enhanced VFAs
Features
The EL5x02 and EL5x03 families represent high-speed
VFAs based on a CFA amplifier architecture. This gives the
typical high slew rate benefits of a CFA family along with the
stability and ease of use associated with the VFA type
architecture. With slew rates of 3500V/µs, this family of
devices enables the use of voltage feedback amplifiers in a
space where the only alternative has been current feedback
amplifiers. This family will also be available in single, dual,
and triple versions, with 200MHz, 400MHz, and 750MHz
versions. These are all available in single, dual, and triple
versions.
• Operates off 3V, 5V, or ±5V applications
• Power-down to 0µA (EL5x02)
• -3dB bandwidth = 400MHz
• ±0.1dB bandwidth = 50MHz
• Low supply current = 5mA
• Slew rate = 3500V/µs
• Low offset voltage = 5mV max
• Output current = 140mA
• A
= 2000
• Diff gain/phase = 0.01%/0.01°
Both families operate on single 5V or ±5V supplies from
minimum supply current. EL5x02 also features an output
enable function, which can be used to put the output in to a
high-impedance mode. This enables the outputs of multiple
amplifiers to be tied together for use in multiplexing
applications.
VOL
• Pb-Free plus anneal available (RoHS compliant)
Applications
• Video amplifiers
• PCMCIA applications
• A/D drivers
Typical applications for these families will include cable
driving, filtering, A-to-D and D-to-A buffering, multiplexing
and summing within video, communications, and
instrumentation designs.
• Line drivers
• Portable computers
• High speed communications
• RGB applications
• Broadcast equipment
• Active filtering
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5102, EL5103, EL5202, EL5203, EL5302
Ordering Information (Continued)
Ordering Information
PART
TAPE &
REEL
PKG.
DWG. #
PART
TAPE &
REEL
PKG.
DWG. #
PART NUMBER MARKING PACKAGE
PART NUMBER MARKING PACKAGE
EL5203ISZ-T7
(See Note)
5203ISZ
8 Ld SOIC
(Pb-free)
7”
MDP0027
MDP0027
EL5102IS
5102IS
5102IS
5102IS
5102ISZ
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
-
7”
13”
-
MDP0027
MDP0027
MDP0027
MDP0027
EL5102IS-T7
EL5102IS-T13
EL5203ISZ-T13 5203ISZ
(See Note)
8 Ld SOIC
(Pb-free)
13”
EL5102ISZ
(See Note)
8 Ld SOIC
(Pb-free)
EL5203IY
BSAAA
BSAAA
BSAAA
BAAAE
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
-
7”
13”
-
MDP0043
MDP0043
MDP0043
MDP0043
EL5203IY-T7
EL5203IY-T13
EL5102ISZ-T7
(See Note)
5102ISZ
8 Ld SOIC
(Pb-free)
7”
MDP0027
MDP0027
MDP0038
MDP0038
MDP0038
MDP0038
P5.049
EL5203IYZ
(See Note)
8 Ld MSOP
(Pb-free)
EL5102ISZ-T13 5102ISZ
(See Note)
8 Ld SOIC
(Pb-free)
13”
EL5203IYZ-T7
(See Note)
BAAAE
8 Ld MSOP
(Pb-free)
7”
MDP0043
MDP0043
EL5102IW-T7
q
6 Ld SOT-23
7”
(3K pcs)
EL5203IYZ-T13 BAAAE
(See Note)
8 Ld MSOP
(Pb-free)
13”
EL5102IW-T7A
q
6 Ld SOT-23
7”
(250 pcs)
EL5302IU
5302IU
5302IU
5302IU
5302IUZ
16 Ld QSOP
16 Ld QSOP
16 Ld QSOP
-
7”
13”
-
MDP0040
MDP0040
MDP0040
MDP0040
EL5102IWZ-T7 BBSA
(See Note)
6 Ld SOT-23
(Pb-free)
7”
(3K pcs)
EL5302IU-T7
EL5302IU-T13
EL5102IWZ-T7A BBSA
(See Note)
6 Ld SOT-23
(Pb-free)
7”
(250 pcs)
EL5302IUZ
(See Note)
16 Ld QSOP
(Pb-free)
EL5103IC-T7
EL5103IC-T7A
EL5103IW-T7
B
B
g
5 Ld SC-70
5 Ld SC-70
5 Ld SOT-23
7”
(3K pcs)
EL5302IUZ-T7 5302IUZ
(See Note)
16 Ld QSOP
(Pb-free)
7”
MDP0040
MDP0040
7”
P5.049
(250 pcs)
EL5302IUZ-T13 5302IUZ
(See Note)
16 Ld QSOP
(Pb-free)
13”
7”
MDP0038
MDP0038
MDP0038
(3K pcs)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020
EL5103IWZ-T7 BBTA
EL5103IWZ-T7A BBTA
5 Ld SOT-23
(Pb-free)
7”
(3K pcs)
5 Ld SOT-23
(Pb-free)
7”
(250 pcs)
EL5202IY
BRAAA
BRAAA
BRAAA
BAAAD
10 Ld MSOP
10 Ld MSOP
10 Ld MSOP
-
7”
13”
-
MDP0043
MDP0043
MDP0043
MDP0043
EL5202IY-T7
EL5202IY-T13
EL5202IYZ
(See Note)
10 Ld MSOP
(Pb-free)
EL5202IYZ-T7
(See Note)
BAAAD
10 Ld MSOP
(Pb-free)
7”
MDP0043
MDP0043
EL5202IYZ-T13 BAAAD
(See Note)
10 Ld MSOP
(Pb-free)
13”
EL5203IS
5203IS
5203IS
5203IS
5203ISZ
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
-
7”
13”
-
MDP0027
MDP0027
MDP0027
MDP0027
EL5203IS-T7
EL5203IS-T13
EL5203ISZ
(See Note)
8 Ld SOIC
(Pb-free)
FN7331.6
June 23, 2006
2
EL5102, EL5103, EL5202, EL5203, EL5302
Pinouts
EL5102
(6 LD SOT-23)
TOP VIEW
EL5103
(5 LD SOT-23)
TOP VIEW
OUT
VS-
IN+
1
2
3
6
5
4
VS+
CE
OUT
VS-
IN+
1
2
3
5
4
VS+
IN-
+
-
+ -
IN-
EL5102
EL5203
(8 LD SOIC)
TOP VIEW
(8 LD SOIC, MSOP)
TOP VIEW
OUTA
INA-
INA+
VS-
NC 1
IN- 2
IN+ 3
VS- 4
8
7
6
5
CE
1
2
3
4
8
7
6
5
VS+
VS+
OUT
NC
-
+
OUTB
INB-
-
+
-
+
INB+
EL5202
(10 LD MSOP)
TOP VIEW
EL5302
(16 LD QSOP)
TOP VIEW
INA+
CEA
VS-
1
2
3
4
5
6
7
8
16 INA-
15 OUTA
14 VS+
OUT
IN-
1
2
3
4
5
10 VS+
-
+
9
8
7
6
OUT
IN-
-
+
IN+
VS-
CE
-
+
+
-
CEB
INB+
NC
13 OUTB
12 INB-
11 NC
IN+
CE
+
-
CEC
INC+
10 OUTC
9
INC-
FN7331.6
June 23, 2006
3
EL5102, EL5103, EL5202, EL5203, EL5302
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V + and GND . . . . . . . . . . . . . . . . . 13.2V
Maximum Current into I +, I -, CE . . . . . . . . . . . . . . . . . . . . . ±5mA
N N
S
Maximum Supply Slewrate between V + and V - . . . . . . . . . 1V/µs
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150°C
S
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 80mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
DC Electrical Specifications V + = +5V, V - = -5V, T = 25°C, R = 500Ω, V
= +5V, unless otherwise specified.
S
S
A
L
ENABLE
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
1
MAX
UNIT
mV
V
Offset Voltage
EL5102, EL5103, EL5202, EL5203
EL5302
5
8
OS
2
mV
TCV
OS
Offset Voltage Temperature Coefficient Measured from T
to T
10
2
µV/°C
µA
MIN
MAX
IB
Input Bias Current
Input Offset Current
V
V
= 0V
= 0V
-12
-8
12
8
IN
IN
I
1
µA
OS
TCI
Input Bias Current Temperature
Coefficient
Measured from T
to T
50
nA/°C
OS
MIN
MAX
PSRR
CMRR
CMIR
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Common Mode Input Range
Input Resistance
V
V
= ±4.75V to ±5.25V
-70
-60
-3
-80
-80
±3.3
400
1
dB
dB
V
S
= -3V to 3.0V
CM
Guaranteed by CMRR test
Common mode
3
R
200
kΩ
pF
mA
µA
µA
dB
dB
V
IN
IN
C
Input Capacitance
SO package
I
Supply Current - Enabled per amplifier
4.6
+1
5.2
0
5.8
+25
-1
S,ON
I
Supply Current - Shut-down per amplifier V +
S
S,OFF
V -
-25
58
7
S
AVOL
Open Loop Gain
V
V
= ±2.5V, R = 1kΩ to GND
66
OUT
OUT
L
= ±2.5V, R = 150Ω to GND
60
L
V
Output Voltage Swing
R = 1kΩ to GND
±3.5
±3.4
±80
±3.9
±3.7
±150
OUT
L
R = 150Ω to GND
V
L
I
Output Current
A
= 1, R = 10Ω to 0V
mA
V
OUT
V
L
V
-ON
CE
CE Pin Voltage for Power-up
CE Pin Voltage for Shut-down
Pin Current - Enabled
Pin Current - Disabled
(V +)-5
(V +)-3
S
S
V
-OFF
-ON
(V +)-1
S
V +
S
V
CE
I
CE = 0V
-1
1
0
+1
25
µA
µA
EN
I
-OFF
CE = +5V
14
EN
FN7331.6
June 23, 2006
4
EL5102, EL5103, EL5202, EL5203, EL5302
Closed Loop AC Electrical Specifications V + = +5V, V - = -5V, T = 25°C, V
= +5V, A = +1, R = 0Ω, R = 150Ω to
S
S
A
ENABLE
V
F
L
GND pin, unless otherwise specified. (Note 1)
PARAMETER
DESCRIPTION
-3dB Bandwidth (V = 400mV
CONDITIONS
MIN
TYP
400
2200
4000
2.8
MAX
UNIT
MHz
V/µs
V/µs
ns
BW
SR
)
A
A
= 1, R = 0Ω
F
OUT
P-P
V
V
Slew Rate
= +2, R = 100Ω, V
= -3V to +3V
1100
5000
L
OUT
= -3V to +3V
OUT
R = 500Ω, V
L
t ,t
Rise Time, Fall Time
Overshoot
±0.1V step
±0.1V step
R F
OS
10
%
t
0.1% Settling Time
Differential Gain (Note 2)
Differential Phase (Note 2)
Input Noise Voltage
Input Noise Current
Disable Time (Note 3)
Enable Time (Note 3)
V
A
A
= ±5V, R = 500Ω, A = 1, V = ±3V
OUT
20
ns
S
S
V
V
L
V
dG
dP
= 2, R = 1kΩ
0.01
0.01
12
%
F
= 2, R = 1kΩ
°
F
e
f = 10kHz
f = 10kHz
nV/√Hz
pA/√Hz
ns
N
i
11
N
t
50
DIS
t
25
ns
EN
NOTES:
1. All AC tests are performed on a “warmed up” part, except slew rate, which is pulse tested.
2. Standard NTSC signal = 286mV , f = 3.58MHz, as V is swept from 0.6V to 1.314V.R is DC coupled.
P-P IN
L
3. Disable/Enable time is defined as the time from when the logic signal is applied to the ENABLE pin to when the supply current has reached half
its final value.
FN7331.6
June 23, 2006
5
EL5102, EL5103, EL5202, EL5203, EL5302
Typical Performance Curves
5
4
240
180
120
60
V =±5V
S
V =±5V
S
A =+1
V
A =+1
V
R =0
R =0
F
F
3
R =500Ω
R =500Ω
L
L
2
C =+3.3pF
L
C =+3.3pF
L
1
0
0
-1
-2
-3
-4
-5
-60
-120
-180
-240
-3dB BW @ 438MHz
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 1. GAIN vs FREQUENCY (-3dB BANDWIDTH)
FIGURE 2. PHASE vs FREQUENCY
70
60
50
40
30
20
0.5
V =±5V
S
V =±5V
S
0.4
0.3
0.2
0.1
0
R =500Ω
L
A =+1
V
R =0
F
GAIN=40dB or 100
FREQ.=1.64 MHz
R =500Ω
L
0.1dB BW @ 35MHz
C =+3.3pF
L
GAIN BW PRODUCT=1.64x100=164MHz
-0.1
-0.2
-0.3
-0.4
-0.5
0
1
10
100
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
FIGURE 3. 0.1dB BANDWIDTH
FIGURE 4. GAIN BANDWIDTH PRODUCT
300
250
200
150
100
50
5
4
V =±5V
S
V =±5V
S
R =500Ω
R =500Ω
L
L
A =+2
C =+3.3pF
V
L
3
R =R =400Ω
F
G
2
A =+1
V
1
R =0
F
0
-1
-2
-3
-4
-5
A =+5
R =1.6K, R =400
V
F
G
0.1
1
10
100
1000
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGES (±V)
FREQUENCY (MHz)
FIGURE 5. GAIN BANDWIDTH PRODUCT vs SUPPLY
VOLTAGES
FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS +A
V
FN7331.6
June 23, 2006
6
EL5102, EL5103, EL5202, EL5203, EL5302
Typical Performance Curves (Continued)
5
4
5
4
A =+1
V
V =±5V
S
R =0
A =+1
V
F
R =500Ω
3
3
R =0
F
C =+3.3pF
L
L
R =1kΩ
L
C =+3.3pF
L
R =500Ω
2
2
L
1
1
0
0
V =±6
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
S
V =±5V
S
R =150Ω
L
V =±4V
S
R =75Ω
L
V =±3V
S
V =±2.5V
S
R =50Ω
L
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS ±V
FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS
(A = +1)
S
R
LOAD
V
5
5
4
V =±5V
V =±5V
S
S
4
A =+2
A =+5
V
V
R =402Ω
3
2
R =402Ω
F
3
F
C =+3.9pF
L
R =500Ω
C =+3.9pF
L
L
2
R =500Ω
L
R =1kΩ
L
1
1
R =1kΩ
L
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
R =50Ω
L
R =50Ω
L
R =70Ω
L
R =75Ω
L
R
=150Ω
L
R =150Ω
L
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
100
FREQUENCY (MHz)
FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS
(A = +2)
FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS
(A = +5)
R
R
LOAD
LOAD
V
V
5
4
5
4
V =±5V
S
V =±5V
S
C =47pF
C =27pF
L
C =33pF
L
L
A =+1
V
A =+2
C =15pF
V
L
R =0
R =400Ω
F
3
3
F
C =18pF
L
R =500Ω
R =500Ω
L
L
2
2
C =8.2pF
L
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
C =3.3pF
C =8.2pF
L
L
C =0pF
C =0pF
L
L
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS
(A =+1)
FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS
(A = +2)
C
C
LOAD
LOAD
V
V
FN7331.6
June 23, 2006
7
EL5102, EL5103, EL5202, EL5203, EL5302
Typical Performance Curves (Continued)
5
4
5
4
R =150Ω
V =±5V
S
V =±5V
S
F
C =220pF
L
R =100Ω
C =150pF
F
A =+1
A =+5
L
V
V
R =500Ω
R =400Ω
L
3
F
3
C =100pF
L
C =+3pF
L
R =500Ω
L
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
R =50Ω
F
C =56pF
L
R =25Ω
F
R =0Ω
F
C =0pF
L
0.1
1
10
100
0.1
1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS
(A =+5)
FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS R (A = +1)
F
V
C
LOAD
V
5
4
5
4
V =±5V
S
V =±5V
S
R =1.0kΩ
F
A =+2
A =+5
V
V
R =500Ω
R =500Ω
L
3
L
3
R = 680Ω
F
C =+8pF
L
C =+12pF
L
R =4kΩ
F
2
2
R =2kΩ
F
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
R =100Ω
R =402Ω
F
F
R =1kΩ
F
R =274Ω
F
R =402Ω
F
R =100Ω
F
0.1
1
10
100
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS R (A = +2)
FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS R (A = +5)
F
V
F
V
5
4
5
4
C
=4.7pF
IN
C
=10pF
V =±5V
S
V =±5V
S
IN
C
C
=8.2pF
IN
C
=3.3pF
IN
A =+5
V
A =+2
V
R
=402Ω
3
R =RG=402Ω
3
G
F
=6.8pF
IN
C
=2.2pF
IN
R =1600Ω
R =500Ω
L
L
2
2
C =+12pF
L
C =+8pF
L
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
C
=0pF
C
IN
C
=1pF
IN
=4.7pF
IN
C
=0pF
IN
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
100
FREQUENCY (MHz)
FIGURE 18. GAIN vs FREQUENCY FOR VARIOUS C (-)
IN
FIGURE 17. GAIN vs FREQUENCY FOR VARIOUS C (-)
IN
(A = +5)
(A = +2)
V
V
FN7331.6
June 23, 2006
8
EL5102, EL5103, EL5202, EL5203, EL5302
Typical Performance Curves (Continued)
80
70
60
50
40
30
20
10
0
-45
0
A =+2
V
V =±5V
S
45
PHASE
10
90
135
180
225
270
315
360
405
1
GAIN
0.1
V
V
=+5V
=-5V
CC
EE
-10
-20
0.01
10 100 1K 10K 100K 1M 10M 100M 1G
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 20. OUTPUT IMPEDANCE/PHASE vs FREQUENCY
10
-10
A =+1
V
S
A =+5
V
S
0
-20
V =±5V
V =±5V
-10
-20
-30
-40
-50
-60
-30
-40
-50
-60
-70
-80
-90
+PSRR
-70
-80
-100
-110
-PSRR
-90
10M
FREQUENCY (Hz)
100M
500M
1K
10K
100K
1M
1K
10K
100K
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 22. PSRR vs FREQUENCY
FIGURE 21. CMRR vs FREQUENCY
10
9
8
7
6
5
4
3
2
1
0
30
V =±5V
S
25
20
15
10
5
R
=1kΩ
A =+1
LOAD
V
R =0
F
R =500Ω
L
0
-5
-10
-15
-20
-25
-30
V =±5V
S
A =+2
V
R
=150Ω
LOAD
R =R =402Ω
F
L
G
C =8pF
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 24. GROUP DELAY vs FREQUENCY
FIGURE 23. MAX OUTPUT VOLTAGE SWING vs FREQUENCY
FN7331.6
June 23, 2006
9
EL5102, EL5103, EL5202, EL5203, EL5302
Typical Performance Curves (Continued)
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
NOTE:
This was done on the
EL5203 (Dual Op-Amps)
V =±5V
S
V =±5V
S
OUTPUT to INPUT
INPUT to OUTPUT
A =+1
V
A =+1
V
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
R =0
R =0
F
CHIP DISABLED
F
R =500Ω
L
B in to A Out
A in to B Out
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 25. INPUT AND OUTPUT ISOLATION
FIGURE 26. CHANNEL TO CHANNEL ISOLATION
-20
-30
V =±5V
S
V =±5V
S
A =+5
-30
-40
-50
-60
-70
-80
-90
-100
A =+1
V
V
G
-40
-50
R
=402Ω
F
=10MHz
R =0
IN
F
R =1600Ω
R =500Ω
F
L
R =500Ω
C =3.3pF
L
L
C =12pF
V
=2Vp-p
L
OUT
T.H.D
-60
-70
2nd HD
-80
F
3
=1MHz
4
-90
IN
3rd HD
10
FUNDAMENTAL FREQUENCY (MHz)
-100
0
1
2
5
6
7
8
0.1
1
100
OUTPUT VOLTAGES (Vp-p)
FIGURE 28. TOTAL HARMONIC DISTORTION vs OUTPUT
VOLTAGES
FIGURE 27. HARMONIC DISTORTION vs FREQUENCY
6
6
V =±5V
S
V =±5V
S
A =+1
V
5
4
5
4
A =+1
V
ENABLE SIGNAL
R =0
F
R =0
F
R =500
Ω
R =500Ω
L
L
OUT
V
=2Vp-p
V
=2Vp-p
OUT
3
3
DISABLE SIGNAL
OUTPUT SIGNAL
OUTPUT SIGNAL
2
2
1
1
0
0
-1
-2
-3
-1
-2
-3
-600
-600 -400 -200
0
200 400 600 800 1000120014001600
TIME (ns)
-400 -200
0
200 400 600 800 1000 12001400 1600
TIME (ns)
FIGURE 30. TURN-OFF TIME
FIGURE 29. TURN-ON TIME
FN7331.6
June 23, 2006
10
EL5102, EL5103, EL5202, EL5203, EL5302
Typical Performance Curves (Continued)
0.5
0.4
R =500Ω
V =±5V
L
S
V =±5V
S
C =3.3pF
L
A =+1
V
V
=400mV
R =0
F
OUT
0.3
0.2
100
T
=0.9ns
0.1
FALL
0.0
T
=0.923ns
RISE
10
1
-0.1
-0.2
-0.3
-20
0
20 40 60 80 100 120 140 160
TIME (ns)
10
100
1K
10K
100K
FREQUENCY (Hz)
FIGURE 32. SMALL SIGNAL STEP RESPONSE_RISE AND
FALL TIME
FIGURE 31. EQUIVALENT NOISE VOLTAGE vs FREQUENCY
5
6.0
A =+1
V
V =±5V
S
R =500Ω
L
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
R =0
4
3
A =+5
V
F
C =5pF
L
R =500Ω
R
=25Ω
L
V
=4.0V
G
OUT
C =3.3pF
L
2
1
T
=1.167ns
FALL
0
T
=1.243ns
RISE
-1
-2
-3
Please note that the curve showed
positive Current. The negative cur-
rent was almost the same.
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-20
0
20 40 60 80 100 120 140 160
TIME (ns)
SUPPLY VOLTAGE (V)
FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 33. LARGE SIGNAL STEP RESPONSE_RISE AND
FALL TIME
50
10
V =±5V
V =±5V
S
S
Delta IM=(1)-(-77)=78dB
IP3=1+(78/2)=40dBm
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
45
40
35
30
25
20
15
10
5
A =+5
A =+5
V
V
R =1600Ω
R =1600Ω
F
F
f2=1dBm
R =100Ω
R =100Ω
L
L
@ 1.05MHz
C =12pF
L
C =12pF
L
f1=1dBm
@ 0.95MHz
2f2-f1=-77.0dBm
@ 1.15MHz
2f1-f2=-76.8dBm
@ 0.85MHz
0
1
10
100
0.8
0.9
1.0
1.1
1.2
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 36. THIRD ORDER IMD INTERCEPT vs FREQUENCY
FIGURE 35. THIRD ORDER IMD INTERCEPT (IP3)
FN7331.6
June 23, 2006
11
EL5102, EL5103, EL5202, EL5203, EL5302
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.2
1
1.2
1
1.136W
1.087W
543mW
SO8
1.116W
θ
=110°C/W
JA
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
QSOP16
=112°C/W
θ
JA
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 37. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.7
1
607mW
0.6
791mW
MSOP8/10
0.8
488mW
QSOP16
0.5
0.4
0.3
0.2
0.1
0
θ
=206°C/W
JA
781mW
θ
=158°C/W
JA
0.6
0.4
0.2
0
SOT23-5/6
=256°C/W
SO8
=160°C/W
θ
θ
JA
JA
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 40. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7331.6
June 23, 2006
12
EL5102, EL5103, EL5202, EL5203, EL5302
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
SYMBOL
SOT23-5
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
5
SOT23-6
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
6
TOLERANCE
MAX
6
4
N
A
A1
A2
b
±0.05
±0.15
E1
E
±0.05
2
3
c
±0.06
0.15
2X
C
D
D
Basic
1
2
3
0.20
2X
C
E
Basic
5
e
E1
e
Basic
Basic
0.20
C
A-B
D
M
B
b
NX
e1
L
Basic
±0.10
L1
N
Reference
Reference
Rev. E 3/00
0.15
2X
C
A-B
1
3
NOTES:
D
1. Plastic or metal protrusions of 0.25mm maximum per side are
not included.
C
A2
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
SEATING
PLANE
3. This dimension is measured at Datum Plane “H”.
A1
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.10
NX
C
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
6. SOT23-5 version has no center lead (shown as a dashed line).
(L1)
H
A
GAUGE
PLANE
0.25
c
+3°
-0°
L
0°
FN7331.6
June 23, 2006
13
EL5102, EL5103, EL5202, EL5203, EL5302
Quarter Size Outline Plastic Packages Family (QSOP)
A
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
A
A1
A2
b
0.068
0.006
0.056
0.010
0.008
0.193
0.236
0.154
0.025
0.025
0.041
16
0.068
0.006
0.056
0.010
0.008
0.341
0.236
0.154
0.025
0.025
0.041
24
0.068
0.006
0.056
0.010
0.008
0.390
0.236
0.154
0.025
0.025
0.041
28
Max.
±0.002
±0.004
±0.002
±0.001
±0.004
±0.008
±0.004
Basic
-
-
PIN #1
I.D. MARK
E
E1
-
-
c
-
1
(N/2)
D
1, 3
B
E
-
0.010 C A B
E1
e
2, 3
e
-
H
L
±0.009
Basic
-
C
SEATING
L1
N
-
PLANE
Reference
-
0.007 C A B
b
0.004 C
Rev. E 3/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
FN7331.6
June 23, 2006
14
EL5102, EL5103, EL5202, EL5203, EL5302
Mini SO Package Family (MSOP)
MDP0043
0.25 M C A B
A
MINI SO PACKAGE FAMILY
D
(N/2)+1
SYMBOL
MSOP8
1.10
0.10
0.86
0.33
0.18
3.00
4.90
3.00
0.65
0.55
0.95
8
MSOP10
1.10
0.10
0.86
0.23
0.18
3.00
4.90
3.00
0.50
0.55
0.95
10
TOLERANCE
Max.
NOTES
N
A
A1
A2
b
-
±0.05
-
±0.09
-
E
E1
PIN #1
I.D.
+0.07/-0.08
±0.05
-
c
-
D
±0.10
1, 3
E
±0.15
-
1
B
(N/2)
E1
e
±0.10
2, 3
Basic
-
L
±0.15
-
e
H
C
L1
N
Basic
-
SEATING
PLANE
Reference
-
Rev. C 6/99
M
C A B
b
0.08
0.10 C
NOTES:
N LEADS
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
L1
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A
c
SEE DETAIL "X"
A2
GAUGE
PLANE
0.25
L
DETAIL X
A1
3° ±3°
FN7331.6
June 23, 2006
15
EL5102, EL5103, EL5202, EL5203, EL5302
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7331.6
June 23, 2006
16
EL5102, EL5103, EL5202, EL5203, EL5302
Small Outline Transistor Plastic Packages (SC70-5)
D
P5.049
VIEW C
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
e1
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.043
0.004
0.039
0.012
0.010
0.009
0.009
0.085
0.094
0.053
MIN
0.80
0.00
0.80
0.15
0.15
0.08
0.08
1.85
1.80
1.15
MAX
1.10
0.10
1.00
0.30
0.25
0.22
0.20
2.15
2.40
1.35
NOTES
5
1
4
A
A1
A2
b
0.031
0.000
0.031
0.006
0.006
0.003
0.003
0.073
0.071
0.045
-
-
-
-
E
C
L
C
E1
L
2
3
b
b1
c
e
6
6
3
-
C
L
c1
D
0.20 (0.008) M
C
C
C
L
E
E1
e
3
-
SEATING
PLANE
0.0256 Ref
0.0512 Ref
0.010 0.018
0.65 Ref
1.30 Ref
0.26 0.46
A2
A1
A
e1
L
-
-C-
4
-
L1
L2
0.017 Ref.
0.420 Ref.
0.15 BSC
0.10 (0.004)
C
0.006 BSC
o
o
o
o
0
8
0
8
-
α
N
b
WITH
5
5
5
PLATING
b1
R
0.004
0.004
-
0.10
0.15
-
R1
0.010
0.25
c
c1
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
4X θ1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
GAUGE PLANE
SEATING
PLANE
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
L
C
α
L2
L1
4X θ1
VIEW C
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN7331.6
June 23, 2006
17
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