EL5111AIYEZ-T13 [INTERSIL]
60MHz Rail-to-Rail Input-Output Op Amps; 60MHz的轨至轨输入输出运算放大器
| 型号： | EL5111AIYEZ-T13 |
| 厂家： | 
Intersil |
| 描述： | 60MHz Rail-to-Rail Input-Output Op Amps |
| 文件： | 总18页 (文件大小：533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5111, EL5211, EL5411
®
Data Sheet
May 7, 2007
FN7119.7
60MHz Rail-to-Rail Input-Output Op Amps
Features
The EL5111, EL5211, and EL5411 are low power, high
voltage rail-to-rail input-output amplifiers. The EL5111
represents a single amplifier, the EL5211 contains two
amplifiers, and the EL5411 contains four amplifiers.
Operating on supplies ranging from 5V to 15V, while
consuming only 2.5mA per amplifier, the EL5111, EL5211,
and EL5411 have a bandwidth of 60MHz (-3dB). They also
provide common mode input ability beyond the supply rails,
as well as rail-to-rail output capability. This enables these
amplifiers to offer maximum dynamic range at any supply
voltage.
• Pb-free plus anneal available (RoHS compliant)
• 60MHz (-3dB) bandwidth
• Supply voltage = 4.5V to 16.5V
• Low supply current (per amplifier) = 2.5mA
• High slew rate = 75V/µs
• Unity-gain stable
• Beyond the rails input capability
• Rail-to-rail output swing
• ±180mA output short current
The EL5111, EL5211, and EL5411 also feature fast slewing
and settling times, as well as a high output drive capability of
65mA (sink and source). These features make these
amplifiers ideal for high speed filtering and signal
conditioning application. Other applications include battery
power, portable devices, and anywhere low power
consumption is important.
Applications
• TFT-LCD panels
• V
COM
amplifiers
• Drivers for A/D converters
• Data acquisition
The EL5111 is available in 5 Ld TSOT and 8 Ld HMSOP
packages. The EL5211 is available in the 8 Ld HMSOP
package. The EL5411 is available in space-saving 14 Ld
HTSSOP packages. All feature a standard operational
amplifier pinout. These amplifiers operate over a temperature
range of -40°C to +85°C.
• Video processing
• Audio processing
• Active filters
• Test equipment
• Battery-powered applications
• Portable equipment
Pinouts
EL5111
(8 LD HMSOP)
TOP VIEW
EL5111
(5 LD TSOT)
TOP VIEW
EL5211
(8 LD HMSOP)
TOP VIEW
EL5411
(14 LD HTSSOP)
TOP VIEW
NC
VIN-
VIN+
VS-
1
2
3
4
8
7
6
5
NC
VOUT 1
5
4
VS+
VIN-
VOUTA
VINA-
VINA+
VS-
1
2
3
4
8
7
6
5
VS+
VOUTA 1
14 VOUTD
VS+
VOUT
NC
VS-
2
3
-
+
VOUTB
VINB-
VINB+
VINA-
VINA+
VS+
2
3
4
5
6
7
13 VIND-
12 VIND+
11 VS-
-
+
+
-
-
+
-
+
VIN+
-
+
VINB+
VINB-
VOUTB
10 VINC+
+
-
+
-
9
8
VINC-
VOUTC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5111, EL5211, EL5411
Ordering Information
PART NUMBER
PART MARKING
TAPE & REEL
PACKAGE
PKG. DWG. #
MDP0049
EL5111IWT-T7
8
7” (3k pcs)
5 Ld TSOT
5 Ld TSOT
EL5111IWT-T7A
8
7” (250 pcs)
MDP0049
MDP0049
MDP0049
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0050
MDP0048
MDP0048
MDP0048
EL5111IWTZ-T7 (Note)
EL5111IWTZ-T7A (Note)
EL5111IYE
BAAG
BAAG
7
7” (3k pcs)
5 Ld TSOT (Pb-free)
7” (250 pcs)
5 Ld TSOT (Pb-free)
-
7”
13”
-
8 Ld HMSOP (3.0mm)
EL5111IYE-T7
7
8 Ld HMSOP (3.0mm)
EL5111IYE-T13
7
8 Ld HMSOP (3.0mm)
EL5111IYEZ (Note)
EL5111IYEZ-T7 (Note)
EL5111IYEZ-T13 (Note)
EL5111AIYEZ (Note)
EL5111AIYEZ-T13 (Note)
EL5111AIYEZ-T7 (Note)
EL5211IYE
BAAJA
BAAJA
BAAJA
BBLAA
BBLAA
BBLAA
9
8 Ld HMSOP (Pb-free) (3.0mm)
8 Ld HMSOP (Pb-free) (3.0mm)
8 Ld HMSOP (Pb-free) (3.0mm)
8 Ld HMSOP (Pb-free) (3.0mm)
8 Ld HMSOP (Pb-free) (3.0mm)
8 Ld HMSOP (Pb-free) (3.0mm)
8 Ld HMSOP (3.0mm)
7”
13”
-
13”
7”
-
EL5211IYE-T7
9
7”
13”
-
8 Ld HMSOP (3.0mm)
EL5211IYE-T13
9
8 Ld HMSOP (3.0mm)
EL5211IYEZ (Note)
EL5211IYEZ-T7 (Note)
EL5211IYEZ-T13 (Note)
EL5411IRE
BAATA
BAATA
BAATA
5411IRE
5411IRE
5411IRE
5411IREZ
5411IREZ
5411IREZ
5411IR
5411IR
5411IR
5411IRZ
5411IRZ
5411IRZ
8 Ld HMSOP (Pb-free) (3.0mm)
8 Ld HMSOP (Pb-free) (3.0mm)
8 Ld HMSOP (Pb-free) (3.0mm)
14 Ld HTSSOP (4.4mm)
14 Ld HTSSOP (4.4mm)
14 Ld HTSSOP (4.4mm)
7”
13”
-
EL5411IRE-T7
7”
13”
-
EL5411IRE-T13
EL5411IREZ (Note)
EL5411IREZ-T7 (Note)
EL5411IREZ-T13 (Note)
EL5411IR
14 Ld HTSSOP (Pb-free) (4.4mm) MDP0048
14 Ld HTSSOP (Pb-free) (4.4mm) MDP0048
14 Ld HTSSOP (Pb-free) (4.4mm) MDP0048
7”
13”
-
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
MDP0044
MDP0044
MDP0044
EL5411IR-T7
7”
13”
-
EL5411IR-T13
EL5411IRZ (Note)
EL5411IRZ-T7 (Note)
EL5411IRZ-T13 (Note)
14 Ld TSSOP (Pb-free) (4.4mm) M14.173
14 Ld TSSOP (Pb-free) (4.4mm) M14.173
14 Ld TSSOP (Pb-free) (4.4mm) M14.173
7”
13”
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN7119.7
May 7, 2007
2
EL5111, EL5211, EL5411
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . .+18V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
S
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V - - 0.5V, V +0.5V
S
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 65mA
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, R = 1kΩ to 0V, T = +25°C, Unless Otherwise Specified
S
S
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
15
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
V
= 0V
= 0V
3
7
2
1
2
mV
µV/°C
nA
OS
CM
CM
TCV
Average Offset Voltage Drift (Note 1)
Input Bias Current
OS
I
60
B
R
C
Input Impedance
GΩ
pF
IN
Input Capacitance
IN
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open-Loop Gain
-5.5
50
+5.5
V
CMRR
for V from -5.5V to 5.5V
IN
70
70
dB
A
-4.5V ≤ V
≤ 4.5V
OUT
62
dB
VOL
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short-Circuit Current
Output Current
I = -5mA
-4.92
4.92
±180
±65
-4.85
V
V
OL
L
I = 5mA
4.85
OH
L
I
I
mA
mA
SC
OUT
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current
V
is moved from ±2.25V to ±7.75V
60
80
2.5
5
dB
mA
mA
mA
S
I
No load (EL5111)
No load (EL5211)
No load (EL5411)
4.5
7.5
15
S
10
DYNAMIC PERFORMANCE
SR Slew Rate (Note 2)
-4.0V ≤ V
≤ 4.0V, 20% to 80%
75
80
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V step
S
V
O
BW
-3dB Bandwidth
60
MHz
MHz
°
GBWP
PM
Gain-Bandwidth Product
Phase Margin
32
50
CS
Channel Separation
Differential Gain (Note 3)
Differential Phase (Note 3)
f = 5MHz (EL5211 and EL5411 only)
110
0.17
0.24
dB
%
d
d
R
R
= R = 1kΩ and V
= 1.4V
= 1.4V
G
P
F
G
OUT
= R = 1kΩ and V
°
F
G
OUT
NOTES:
1. Measured over operating temperature range.
2. Slew rate is measured on rising and falling edges.
3. NTSC signal generator used.
FN7119.7
May 7, 2007
3
EL5111, EL5211, EL5411
Electrical Specifications V + = +5V, V - = 0V, R = 1kΩ to 2.5V, T = +25°C, Unless Otherwise Specified
S
S
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
15
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
V
= 2.5V
= 2.5V
3
7
2
1
2
mV
µV/°C
nA
OS
CM
CM
TCV
Average Offset Voltage Drift (Note 4)
Input Bias Current
OS
I
60
B
R
C
Input Impedance
GΩ
pF
IN
IN
Input Capacitance
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open-Loop Gain
-0.5
45
+5.5
150
V
CMRR
for V from -0.5V to 5.5V
IN
66
70
dB
A
0.5V ≤ V
≤ 4.5V
OUT
62
dB
VOL
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short-circuit Current
Output Current
I = -5mA
80
mV
V
OL
L
I = 5mA
4.85
4.92
±180
±65
OH
L
I
I
mA
mA
SC
OUT
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current
V
is moved from 4.5V to 15.5V
60
80
2.5
5
dB
mA
mA
mA
S
I
No load (EL5111)
No load (EL5211)
No load (EL5411)
4.5
7.5
15
S
10
DYNAMIC PERFORMANCE
SR Slew Rate (Note 5)
1V ≤ V
≤ 4V, 20% to 80%
75
80
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V step
S
V
O
BW
-3dB Bandwidth
60
MHz
MHz
°
GBWP
PM
Gain-Bandwidth Product
Phase Margin
32
50
CS
Channel Separation
Differential Gain (Note 6)
Differential Phase (Note 6)
f = 5MHz (EL5211 and EL5411 only)
110
0.17
0.24
dB
%
d
d
R
R
= R = 1kΩ and V
= 1.4V
= 1.4V
G
P
F
F
G
OUT
= R = 1kΩ and V
°
G
OUT
NOTES:
4. Measured over operating temperature range.
5. Slew rate is measured on rising and falling edges.
6. NTSC signal generator used.
FN7119.7
May 7, 2007
4
EL5111, EL5211, EL5411
Electrical Specifications V + = +15V, V - = 0V, R = 1kΩ to 7.5V, T = +25°C, Unless Otherwise Specified
S
S
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
15
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
= 7.5V
= 7.5V
3
7
2
1
2
mV
µV/°C
nA
OS
CM
CM
TCV
Average Offset Voltage Drift (Note 7)
Input Bias Current
OS
I
V
60
B
R
C
Input Impedance
GΩ
pF
IN
IN
Input Capacitance
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open-Loop Gain
-0.5
53
+15.5
150
V
CMRR
for V from -0.5V to 15.5V
IN
72
70
dB
A
0.5V ≤ V
≤ 14.5V
OUT
62
dB
VOL
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short-circuit Current
Output Current
I = -5mA
80
mV
V
OL
L
I = 5mA
14.85
14.92
±180
±65
OH
L
I
I
mA
mA
SC
OUT
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current
V
is moved from 4.5V to 15.5V
60
80
2.5
5
dB
mA
mA
mA
S
I
No load (EL5111)
No load (EL5211)
No load (EL5411)
4.5
7.5
15
S
10
DYNAMIC PERFORMANCE
SR Slew Rate (Note 8)
1V ≤ V
≤ 14V, 20% to 80%
75
80
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V step
S
V
O
BW
-3dB Bandwidth
60
MHz
MHz
°
GBWP
PM
Gain-Bandwidth Product
Phase Margin
32
50
CS
Channel Separation
Differential Gain (Note 9)
Differential Phase (Note 9)
f = 5MHz (EL5211 and EL5411 only)
110
0.16
0.22
dB
%
d
d
R
R
= R = 1kΩ and V
= 1.4V
= 1.4V
G
P
F
F
G
OUT
= R = 1kΩ and V
°
G
OUT
NOTES:
7. Measured over operating temperature range
8. Slew rate is measured on rising and falling edges
9. NTSC signal generator used
FN7119.7
May 7, 2007
5
EL5111, EL5211, EL5411
Typical Performance Curves
500
25
V
= ±5V
= +25°C
TYPICAL
PRODUCTION
DISTRIBUTION
V
= ±5V
TYPICAL
PRODUCTION
DISTRIBUTION
S
S
T
A
400
300
200
100
0
20
15
10
5
0
INPUT OFFSET VOLTAGE (mV)
INPUT OFFSET VOLTAGE DRIFT, TCV
(µV/°C)
OS
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT
2.0
1.5
1.0
0.5
0.0
-0.5
0.008
V
= ±5V
S
0.004
0.000
-0.004
-0.008
-0.012
-50
-10
30
70
110
150
-50
-10
30
70
110
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
4.96
-4.85
V
= ±5V
= 5mA
V = ±5V
S
OUT
S
I
I
= 5mA
OUT
-4.87
-4.89
-4.91
-4.93
-4.95
4.94
4.92
4.90
4.88
4.86
-50
-10
30
70
110
150
-50
-10
30
70
110
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
FN7119.7
May 7, 2007
6
EL5111, EL5211, EL5411
Typical Performance Curves (Continued)
75
70
65
60
78
77
76
75
74
73
72
V
R
= ±5V
= 1kΩ
V = ±5V
S
S
L
-50
-10
30
70
110
150
-50
-10
30
70
110
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE
FIGURE 8. SLEW RATE vs TEMPERATURE
2.9
2.70
T
= +25°C
V = ±5V
S
A
2.7
2.5
2.3
2.1
1.9
1.7
1.5
2.65
2.60
2.55
2.50
2.45
2.40
4
8
12
16
20
-50
-10
30
70
110
150
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY
VOLTAGE
FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs
TEMPERATURE
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.14
-0.16
-0.18
V
= ±5V
= 2
= 1kΩ
S
A
V
R
L
0
100
IRE
200
0
100
IRE
200
FIGURE 11. DIFFERENTIAL GAIN
FIGURE 12. DIFFERENTIAL PHASE
FN7119.7
May 7, 2007
7
EL5111, EL5211, EL5411
Typical Performance Curves (Continued)
-30
-40
-50
-60
-70
-80
-90
80
60
40
20
0
250
190
130
70
V
= ±5V
= 2
= 1kΩ
S
A
V
R
L
GAIN
FREQ = 1MHz
2nd HD
PHASE
10
3rd HD
-20
1k
-50
100M
0
2
4
6
8
10
10k
100k
1M
10M
V
(V)
FREQUENCY (Hz)
OP-P
FIGURE 13. HARMONIC DISTORTION vs V
FIGURE 14. OPEN LOOP GAIN AND PHASE
OP-P
5
25
V
= ±5V
= 1
S
100pF
A
V
1000pF
15
C
= 0pF
3
1
LOAD
1kΩ
47pF
10pF
5
-5
-1
-3
-5
560Ω
150Ω
V
= ±5V
= 1
= 1kΩ
S
-15
A
V
R
L
-25
100k
100k
1M
10M
100M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS R
FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS C
L
L
400
350
300
250
200
150
100
50
12
10
8
6
4
V
= ±5V
= 1
= 1kΩ
S
A
V
2
R
L
DISTORTION <1%
0
10k
0
10k
100k
1M
10M
100M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (kHz)
FIGURE 17. CLOSED LOOP OUTPUT IMPEDANCE
FIGURE 18. MAXIMUM OUTPUT SWING vs FREQUENCY
FN7119.7
May 7, 2007
8
EL5111, EL5211, EL5411
Typical Performance Curves (Continued)
-15
-25
-35
-45
-55
-65
-80
-60
-40
-20
0
PSRR+
PSRR-
V
T
= ±5V
= +25°C
S
A
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. CMRR
FIGURE 20. PSRR
-60
-80
1K
100
10
DUAL MEASURED CH A TO B
QUAD MEASURED CH A TO D OR B TO C
OTHER COMBINATIONS YIELD
IMPROVED REJECTION
-100
-120
-140
-160
V
R
= ±5V
= 1kΩ
= 1
S
L
A
V
IN
V
= 110mV
RMS
1
100
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
30M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 21. INPUT VOLTAGE NOISE SPECTRAL DENSITY
FIGURE 22. CHANNEL SEPARATION
5
4
100
V
= ±5V
= 1
= 1kΩ
V
= ±5V
A = 1
V
L
S
S
A
V
R
V
3
R
= 1kΩ
80
60
40
20
0
L
0.1%
= ±50mV
= +25°C
IN
2
T
A
1
0
-1
-2
-3
-4
-5
0.1%
95
10
100
LOAD CAPACITANCE (pF)
1k
55
65
75
85
105
SETTLING TIME (ns)
FIGURE 23. SMALL-SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
FIGURE 24. SETTLING TIME vs STEP SIZE
FN7119.7
May 7, 2007
9
EL5111, EL5211, EL5411
Typical Performance Curves (Continued)
V
T
= ±5V
= +25°C
= 1
V
T
= ±5V
= +25°C
= 1
S
A
S
A
A
A
V
V
R
= 1kΩ
R
= 1kΩ
L
L
100mV STEP
1V STEP
50ns/DIV
50ns/DIV
FIGURE 25. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 26. SMALL SIGNAL TRANSIENT RESPONSE
Pin Descriptions
EL5111
EL5111
EL5211
EL5411
(TSOT-5)
(HMSOP8) (HMSOP8) (HTSSOP14)
NAME
FUNCTION
EQUIVALENT CIRCUIT
1
6 1 1
VOUTA Amplifier A output
V
S+
V
S-
GND
CIRCUIT 1
4
2
2
2
VINA-
Amplifier A inverting input
V
S+
V
S-
CIRCUIT 2
(Reference Circuit 2)
3
5
3
7
3
8
5
6
7
3
4
VINA+
VS+
Amplifier A non-inverting input
Positive power supply
5
VINB+
VINB-
Amplifier B non-inverting input
Amplifier B inverting input
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 1)
(Reference Circuit 1)
(Reference Circuit 2)
(Reference Circuit 2)
6
7
VOUTB Amplifier B output
VOUTC Amplifier C output
8
9
VINC-
VINC+
VS-
Amplifier C inverting input
10
11
12
13
14
Amplifier C non-inverting input
Negative power supply
2
4
4
VIND+
VIND-
Amplifier D non-inverting input
Amplifier D inverting input
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 1)
VOUTD Amplifier D output
NC Not connected
1, 5, 8
FN7119.7
May 7, 2007
10
EL5111, EL5211, EL5411
Short Circuit Current Limit
Applications Information
The EL5111, EL5211, and EL5411 will limit the short circuit
current to ±180mA if the output is directly shorted to the
positive or the negative supply. If an output is shorted
indefinitely, the power dissipation could easily increase such
that the device may be damaged. Maximum reliability is
maintained if the output continuous current never exceeds
±65mA. This limit is set by the design of the internal metal
interconnects.
Product Description
The EL5111, EL5211, and EL5411 voltage feedback
amplifiers are fabricated using a high voltage CMOS
process. They exhibit rail-to-rail input and output capability,
are unity gain stable and have low power consumption
(2.5mA per amplifier). These features make the EL5111,
EL5211, and EL5411 ideal for a wide range of general-
purpose applications. Connected in voltage follower mode
and driving a load of 1kΩ, the EL5111, EL5211, and EL5411
have a -3dB bandwidth of 60MHz while maintaining a 75V/µs
slew rate. The EL5111 is a single amplifier, the EL5211 a
dual amplifier, and the EL5411 a quad amplifier.
Output Phase Reversal
The EL5111, EL5211, and EL5411 are immune to phase
reversal as long as the input voltage is limited from V - -0.5V
S
to V + +0.5V. Figure 28 shows a photo of the output of the
S
device with the input voltage driven beyond the supply rails.
Although the device's output will not change phase, the
input's overvoltage should be avoided. If an input voltage
exceeds supply voltage by more than 0.6V, electrostatic
protection diodes placed in the input stage of the device
begin to conduct and overvoltage damage could occur.
Operating Voltage, Input, and Output
The EL5111, EL5211, and EL5411 are specified with a single
nominal supply voltage from 5V to 15V or a split supply with
its total range from 5V to 15V. Correct operation is
guaranteed for a supply range of 4.5V to 16.5V. Most
EL5111, EL5211, and EL5411 specifications are stable over
both the full supply range and operating temperatures of
-40°C to +85°C. Parameter variations with operating voltage
and/or temperature are shown in the typical performance
curves.
V
= ±2.5V, T = +25°C, A = 1, V = 6V
S
A
V
IN
P-P
1V
10µs
The input common-mode voltage range of the EL5111,
EL5211, and EL5411 extends 500mV beyond the supply
rails. The output swings of the EL5111, EL5211, and EL5411
typically extend to within 100mV of positive and negative
supply rails with load currents of 5mA. Decreasing load
currents will extend the output voltage range even closer to
the supply rails. Figure 27 shows the input and output
waveforms for the device in the unity-gain configuration.
Operation is from ±5V supply with a 1kΩ load connected to
1V
FIGURE 28. OPERATION WITH BEYOND-THE-RAILS INPUT
GND. The input is a 10V
sinusoid. The output voltage is
P-P
Power Dissipation
approximately 9.8V
.
P-P
With the high-output drive capability of the EL5111, EL5211,
and EL5411 amplifiers, it is possible to exceed the +125°C
'absolute-maximum junction temperature' under certain load
current conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if load conditions need to be modified for the
amplifier to remain in the safe operating area.
V
= ±5V, T = +25°C, A = 1, V = 10V
IN P-P
S
A
V
5V
10µs
The maximum power dissipation allowed in a package is
determined according to:
T
– T
AMAX
JMAX
--------------------------------------------
P
=
5V
DMAX
θ
JA
(EQ. 1)
FIGURE 27. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
where:
• T
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
• Θ = Thermal resistance of the package
JA
• P
DMAX
= Maximum power dissipation in the package
FN7119.7
May 7, 2007
11
EL5111, EL5211, EL5411
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD -
HTSSOP EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
P
= Σi[V × I
+ (V + – V
i) × I
i]
LOAD
DMAX
S
SMAX
S
OUT
(EQ. 2)
2.632W
when sourcing, and:
HTSSOP14
θ
= +38°C/W
JA
P
= Σi[V × I
+ (V
i – V -) × I
i]
LOAD
DMAX
S
SMAX
OUT
S
(EQ. 3)
when sinking,
where:
• i = 1 to 2 for dual and 1 to 4 for quad
• V = Total supply voltage
0
25
50
75 85 100
125
S
AMBIENT TEMPERATURE (°C)
• I
SMAX
= Maximum supply current per amplifier
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
• V
i = Maximum output voltage of the application
OUT
• I
i = Load current
LOAD
If we set the two P
can solve for R
through 36 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
equations equal to each other, we
i to avoid device overheat. Figures 29
DMAX
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
LOAD
1.2
TSSOP28
1.0
0.8
0.6
θ
θ
θ
θ
= +120°C/W
JA
TSSOP24
= +128°C/W
simple matter to see if P
exceeds the device's power
JA
DMAX
TSSOP20
1.042W
977mW
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figures 29 through 36.
= +140°C/W
JA
TSSOP16
0.4 893mW
845mW
= +148°C/W
JA
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
0.2
TSSOP14
CONDUCTIVITY TEST BOARD
758mW
0.9
θ
= +165°C/W
125 150
JA
0.0
0.8
0
25
50
75 85 100
694mW
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
HTSSOP14
= +144°C/W
AMBIENT TEMPERATURE (°C)
θ
JA
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.8
TSSOP28
=+75°C/W
1.6
0
25
50
75 85 100
125
θ
θ
θ
θ
JA
TSSOP24
1.4
1.2
1.0
0.8
AMBIENT TEMPERATURE (°C)
=+85°C/W
FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JA
TSSOP20
1.667W
1.471W
=+90°C/W
JA
TSSOP16
0.6 1.389W
=+97°C/W
JA
1.289W
1.250W
0.4
0.2
0.0
TSSOP14
θ
=+100°C/W
125 150
JA
0
25
50
75 85 100
AMBIENT TEMPERATURE (°C)
FIGURE 32. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7119.7
May 7, 2007
12
EL5111, EL5211, EL5411
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY (SINGLE LAYER) TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
0.6
0.5
0.4
0.3
0.2
0.1
0.0
290mW
483mW
TSOT5
= +345°C/W
TSOT5
= +207°C/W
θ
JA
θ
JA
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
CONDUCTIVITY TEST BOARD
0.6
1
870mW
0.9
486mW
0.5
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
0
25
50
75 85 100
125
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 35. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 36. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Unused Amplifiers
Power Supply Bypassing and Printed Circuit
Board Layout
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
The EL5111, EL5211, and EL5411 can provide gain at high
frequency. As with any high-frequency device, good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the V - pin is
S
connected to ground, a 0.1µF ceramic capacitor should be
placed from V + to pin to V - pin. A 4.7µF tantalum
S
S
capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7µF capacitor may be used for
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used.
FN7119.7
May 7, 2007
13
EL5111, EL5211, EL5411
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
0.25 M C A B
D
A
(N/2)+1
MILLIMETERS
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
2X
1
(N/2)
c
N/2 LEAD TIPS
B
D
TOP VIEW
E
Basic
E1
e
±0.10
Basic
0.05
H
e
L
±0.15
C
L1
Reference
Rev. F 2/07
SEATING
PLANE
NOTES:
0.10 M C A B
b
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN7119.7
May 7, 2007
14
EL5111, EL5211, EL5411
HTSSOP (Heat-Sink TSSOP) Family
MDP0048
HTSSOP (HEAT-SINK TSSOP) FAMILY
0.25 M C A B
D
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE
A
A1
A2
b
1.20
1.20
1.20
1.20
1.20
Max
PIN #1 I.D.
E
0.075 0.075 0.075 0.075 0.075
±0.075
E1
0.90
0.25
0.15
5.00
3.2
0.90
0.25
0.15
6.50
4.2
0.90
0.25
0.15
7.80
4.3
0.90
0.25
0.15
9.70
5.0
0.90
0.22
0.15
9.70
7.25
6.40
4.40
3.0
+0.15/-0.10
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
c
2X
1
(N/2)
N/2 LEAD TIPS
TOP VIEW
B
D
D1
E
Reference
Basic
6.40
4.40
3.0
6.40
4.40
3.0
6.40
4.40
3.0
6.40
4.40
3.0
D1
EXPOSED
THERMAL PAD
E1
E2
e
±0.10
Reference
Basic
0.65
0.60
1.00
14
0.65
0.60
1.00
20
0.65
0.60
1.00
24
0.65
0.60
1.00
28
0.50
0.60
1.00
38
E2
L
±0.15
L1
N
Reference
Reference
Rev. 3 2/07
BOTTOM VIEW
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.05
H
e
C
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEATING
PLANE
3. Dimensions “D” and “E1” are measured at Datum Plane H.
0.10 M C A B
b
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.10 C
N LEADS
SIDE VIEW
SEE DETAIL “X”
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN7119.7
May 7, 2007
15
EL5111, EL5211, EL5411
TSOT Package Family
MDP0049
e1
D
TSOT PACKAGE FAMILY
A
MILLIMETERS
TSOT6
1.00
6
4
N
SYMBOL
TSOT5
1.00
0.05
0.87
0.38
0.127
2.90
2.80
1.60
0.95
1.90
0.40
0.60
0.20
5
TSOT8
1.00
0.05
0.87
0.29
0.127
2.90
2.80
1.60
0.65
1.95
0.40
0.60
0.13
8
TOLERANCE
Max
A
A1
A2
b
0.05
±0.05
E1
E
0.87
±0.03
2
3
0.38
±0.07
0.15
2X
C
D
c
0.127
2.90
+0.07/-0.007
Basic
1
2
(N/2)
0.25
C
D
5
2X N/2 TIPS
e
E
2.80
Basic
E1
e
1.60
Basic
ddd
C A-B D
M
B
b
NX
0.95
Basic
e1
L
1.90
Basic
0.40
±0.10
L1
ddd
N
0.60
Reference
-
0.20
0.15
2X
C A-B
1
3
D
6
Reference
Rev. B 2/07
C
NOTES:
A2
1. Plastic or metal protrusions of 0.15mm maximum per side are
not included.
SEATING
PLANE
2. Plastic interlead protrusions of 0.15mm maximum per side are
not included.
A1
0.10
NX
C
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(TSOT6 AND TSOT8 only).
(L1)
H
6. TSOT5 version has no center lead (shown as a dashed line).
A
GAUGE
PLANE
0.25
c
L
4° ±4°
FN7119.7
May 7, 2007
16
EL5111, EL5211, EL5411
HMSOP (Heat-Sink MSOP) Package Family
MDP0050
HMSOP (HEAT-SINK MSOP) PACKAGE FAMILY
E
0.25 M C A B
B
E1
MILLIMETERS
1
N
SYMBOL HMSOP8 HMSOP10
TOLERANCE
Max.
NOTES
A
A1
A2
b
1.00
0.075
0.86
0.30
0.15
3.00
1.85
4.90
3.00
1.73
0.65
0.55
0.95
8
1.00
0.075
0.86
0.20
0.15
3.00
1.85
4.90
3.00
1.73
0.50
0.55
0.95
10
-
D
(N/2)+1
+0.025/-0.050
±0.09
-
-
(N/2)
PIN #1
I.D.
A
+0.07/-0.08
±0.05
-
c
-
TOP VIEW
D
±0.10
1, 3
D1
E
Reference
±0.15
-
E2
EXPOSED
THERMAL PAD
-
E1
E2
e
±0.10
2, 3
Reference
Basic
-
D1
-
L
±0.15
-
L1
N
Basic
-
BOTTOM VIEW
Reference
-
Rev. 1 2/07
NOTES:
e
H
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
C
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
0.08
M
C A B
b
0.10 C
N LEADS
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
L1
A
c
END VIEW
SEE DETAIL "X"
A2
GAUGE
PLANE
0.25
L
A1
3° ±3°
DETAIL X
FN7119.7
May 7, 2007
17
EL5111, EL5211, EL5411
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
INDEX
AREA
0.25(0.010)
M
B M
E
PACKAGE
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
α
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7119.7
May 7, 2007
18
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