EL5172_08 [INTERSIL]
250MHz Differential Line Receivers; 250MHz的差动线路接收器
| 型号： | EL5172_08 |
| 厂家： | 
Intersil |
| 描述： | 250MHz Differential Line Receivers |
| 文件： | 总16页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5172, EL5372
®
Data Sheet
January 25, 2008
FN7311.8
250MHz Differential Line Receivers
Features
The EL5172 and EL5372 are single and triple high
bandwidth amplifiers designed to extract the difference
signal from noisy environments. They are primarily targeted
for applications such as receiving signals from twisted-pair
lines or any application where common mode noise injection
is likely to occur.
• Differential input range ±2.3V
• 250MHz 3dB bandwidth
• 800V/µs slew rate
• 60mA maximum output current
• Single 5V or dual ±5V supplies
• Low power - 5mA to 6mA per channel
• Pb-free available (RoHS compliant)
The EL5172 and EL5372 are stable for a gain of one and
requires two external resistors to set the voltage gain.
The output common mode level is set by the reference pin
(V
), which has a -3dB bandwidth of over 120MHz.
REF
Applications
Generally, this pin is grounded but it can be tied to any
voltage reference.
• Twisted-pair receivers
• Differential line receivers
The output can deliver a maximum of ±60mA and is short
circuit protected to withstand a temporary overload
condition.
• VGA over twisted-pair
• ADSL/HDSL receivers
The EL5172 is available in the 8 Ld SOIC and 8 Ld MSOP
packages and the EL5372 in a 24 Ld QSOP package. Both
are specified for operation over the full -40°C to +85°C
temperature range.
• Differential to single-ended amplification
• Reception of analog signals in a noisy environment
Pinouts
EL5172
(8 LD SOIC, MSOP)
TOP VIEW
EL5372
(24 LD QSOP)
TOP VIEW
OUT
VS-
FB
IN+
IN-
1
2
3
4
8
7
REF1
INP1
INN1
NC
1
2
3
4
5
6
7
8
9
24 NC
+
-
23 FB1
22 OUT1
21 NC
+
-
6 VS+
5 EN
REF
REF2
INP2
INN2
NC
20 VSP
19 VSN
18 NC
+
-
17 FB2
16 OUT2
15 EN
REF3
INP3 10
INN3 11
NC 12
+
-
14 FB3
13 OUT3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2005, 2008. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
EL5172, EL5372
Ordering Information
PART NUMBER
PART MARKING
PACKAGE
8 Ld SOIC (150 mil)
PKG. DWG. #
MDP0027
EL5172IS
5172IS
5172IS
5172IS
5172ISZ
5172ISZ
5172ISZ
h
EL5172IS-T7*
8 Ld SOIC (150 mil)
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0043
MDP0043
MDP0043
MDP0043
MDP0043
MDP0043
MDP0040
MDP0040
MDP0040
MDP0040
MDP0040
MDP0040
EL5172IS-T13*
8 Ld SOIC (150 mil)
EL5172ISZ (Note)
EL5172ISZ-T7* (Note)
EL5172ISZ-T13* (Note)
EL5172IY
8 Ld SOIC (150 mil) (Pb-free)
8 Ld SOIC (150 mil) (Pb-free)
8 Ld SOIC (150 mil) (Pb-free)
8 Ld MSOP (3.0mm)
EL5172IY-T7*
h
8 Ld MSOP (3.0mm)
EL5172IY-T13*
h
8 Ld MSOP (3.0mm)
EL5172IYZ (Note)
EL5172IYZ-T7* (Note)
EL5172IYZ-T13* (Note)
EL5372IU
BAAWA
BAAWA
BAAWA
8 Ld MSOP (3.0mm) (Pb-free)
8 Ld MSOP (3.0mm) (Pb-free)
8 Ld MSOP (3.0mm) (Pb-free)
24 Ld QSOP (150 mil)
EL5372IU
EL5372IU
EL5372IU
EL5372IUZ
EL5372IUZ
EL5372IUZ
EL5372IU-T7*
24 Ld QSOP (150 mil)
EL5372IU-T13*
24 Ld QSOP (150 mil)
EL5372IUZ (Note)
EL5372IUZ-T7* (Note)
EL5372IUZ-T13* (Note)
24 Ld QSOP (150 mil) (Pb-free)
24 Ld QSOP (150 mil) (Pb-free)
24 Ld QSOP (150 mil) (Pb-free)
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN7311.8
January 25, 2008
2
EL5172, EL5372
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage (V + to V -) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
S
S
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, T = +25°C, V = 0V, R = 500Ω, R = 0, R = OPEN, C = 2.7pF, Unless Otherwise
S
S
A
IN
L
F
G
L
Specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
A
=1, C = 2.7pF
250
70
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
V
L
A
=2, R = 1000Ω, C = 2.7pF
F L
V
A
=10, R = 1000Ω, C = 2.7pF
10
V
F
L
BW
SR
±0.1dB Bandwidth
A
=1, C = 2.7pF
25
V
L
Slew Rate
V
V
V
= 3V , 20% to 80%, EL5172
P-P
550
550
800
700
10
1000
1000
OUT
OUT
OUT
= 3V , 20% to 80%, EL5372
P-P
t
t
Settling Time to 0.1%
= 2V
P-P
STL
Output Overdrive Recovery Time
Gain Bandwidth Product
20
ns
OVR
GBWP
100
120
600
26
MHz
MHz
V/µs
nV/√Hz
pA/√Hz
dBc
dBc
dBc
dBc
%
V
V
V
BW (-3dB)
SR
V
V
-3dB Bandwidth
Slew Rate
A =1, C = 2.7pF
V L
REF
REF
N
REF
REF
V
= 2V , 20% to 80%
P-P
OUT
Input Voltage Noise
at f = 11kHz
at f = 11kHz
I
Input Current Noise
2
N
HD2
Second Harmonic Distortion
V
V
V
V
= 1V , 5MHz
P-P
-66
-63
-84
-76
0.04
0.41
90
OUT
OUT
OUT
OUT
= 2V , 50MHz
P-P
HD3
Third Harmonic Distortion
= 1V , 5MHz
P-P
= 2V , 50MHz
P-P
dG
Differential Gain at 3.58MHz
Differential Phase at 3.58MHz
Channel Separation at 100kHz
R
R
= 150Ω, A = 2
V
L
L
dθ
= 150Ω, A = 2
°
V
e
EL5372 only
dB
S
INPUT CHARACTERISTICS
Input Referred Offset Voltage
Input Bias Current (V , V
V
±7
-6
±25
-3
mV
µA
kΩ
pF
V
OS
I
, V
)
-14
IN
IN INB REF
R
Differential Input Resistance
300
1
IN
IN
C
Differential Input Capacitance
Differential Input Range
DMIR
±2.1
3.3
±2.38
3.5
-4.5
3.7
-3.9
±2.5
-4.3
-3.6
CMIR+
CMIR-
Common Mode Positive Input Range at V +, V
IN
-
-
V
IN
Common Mode Positive Input Range at V +, V
IN
IN
V
V
Reference Input Positive Voltage Range
Reference Input Negative Voltage Range
V
V
+ = V - = 0V
IN
3.3
V
REFIN+
REFIN-
IN
IN
+ = V - = 0V
IN
FN7311.8
January 25, 2008
3
EL5172, EL5372
Electrical Specifications V + = +5V, V - = -5V, T = +25°C, V = 0V, R = 500Ω, R = 0, R = OPEN, C = 2.7pF, Unless Otherwise
S
S
A
IN
L
F
G
L
Specified. (Continued)
PARAMETER
CMRR
DESCRIPTION
CONDITIONS
= ±2.5V
MIN
75
TYP
95
1
MAX
UNIT
dB
Input Common Mode Rejection Ratio
Gain Accuracy
V
V
IN
IN
Gain
= 1
0.985
1.015
V
OUTPUT CHARACTERISTICS
V
Positive Output Voltage Swing
Negative Output Voltage Swing
Maximum Output Current
Output Impedance
R
R
R
= 500Ω to GND
= 500Ω to GND
= 10Ω
3.3
3.63
-3.87
±95
V
V
OUT
L
L
L
-3.5
I
(Max)
OUT
±60
mA
mΩ
R
100
OUT
SUPPLY
V
Supply Operating Range
V + to V -
4.75
4.6
11
7
V
SUPPLY
S
S
I
I
Power Supply Current Per Channel - Enabled
Positive Power Supply Current - Disabled
5.6
80
mA
µA
µA
µA
dB
S (on)
+
-
EN pin tied to 4.8V, EL5172
EN pin tied to 4.8V, EL5372
100
5
S (off)
S (off)
1.7
-120
58
I
Negative Power Supply Current - Disabled
Power Supply Rejection Ratio
-150
50
-90
PSRR
V from ±4.5V to ±5.5V
S
ENABLE
t
t
Enable Time
150
1.4
ns
µs
V
EN
DS
Disable Time
V
V
EN Pin Voltage for Power-up
EN Pin Voltage for Shut-down
EN Pin Input Current High Per Channel
EN Pin Input Current Low Per Channel
V + - 1.5
S
IH
V + - 0.5
S
V
IL
I
I
At V
At V
= 5V
= 0V
40
-3
60
µA
µA
IH-EN
IL-EN
EN
EN
-10
FN7311.8
January 25, 2008
4
EL5172, EL5372
Pin Descriptions
EL5172
EL5372
PIN NAME
FB
PIN FUNCTION
1
2
3
4
5
6
7
8
Feedback input
Non-inverting input
Inverting input
IN+
IN-
REF
Sets the common mode output voltage level
EN
Enabled when this pin is floating or the applied voltage ≤ V + - 1.5
S
VS+
Positive supply voltage
VS-
Negative supply voltage
OUT
Output voltage
1, 5, 9
2, 6, 10
3, 7, 11
REF1, 2, 3
INP1, 2, 3
INN1, 2, 3
NC
Reference input, controls common-mode output voltage
Non-inverting inputs
Inverting inputs
4, 8, 12, 18, 21, 24
No connect; grounded for best crosstalk performance
Non-inverting outputs
13, 16, 22
OUT1, 2, 3
FB1, 2, 3
EN
14, 17, 23
Feedback from outputs
15
19
20
Enabled when this pin is floating or the applied voltage ≤ V + - 1.5
S
VSN
Negative supply
Positive supply
VSP
FN7311.8
January 25, 2008
5
Connection Diagrams
R
G
R
= 0Ω
F
-5V
1
2
3
4
FB
OUT
8
7
6
5
VOUT
500Ω
C
2.7pF
R
L
L
INP
INN
INP
INN
VSN
VSP
EN
REF
REF
EL5172
EN
R
R
R
S3
50Ω
S2
50Ω
S2
50Ω
+5V
+5V
R
R
G
REF1
INP1
INN1
1
2
3
4
5
6
7
8
9
REF1
NC 24
FB1 23
OUT1 22
NC 21
F
INP1
INN1
NC
OUT1
C
2.7pF
L1
R
L1
500Ω
REF2
INP2
INN2
REF2
INP2
INN2
NC
VSP 20
VSN 19
NC 18
R
R
G
G
R
R
F
F
FB2 17
OUT2 16
EN 15
OUT2
OUT3
REF3
INP3
INN3
REF3
R
500Ω
L2
10 INP3
11 INN3
12 NC
FB3 14
OUT3 13
R
R
R
R
R
R
R
50Ω
R
R
SR3
50Ω
SP1
50Ω
SN1
50Ω
SR1
50Ω
SP2
50Ω
SN2
50Ω
SR2
50Ω
SP3
SN3
50Ω
R
500Ω
L3
C
2.7pF
C
-5V
L2
L3
2.7pF
EL5372
ENABLE
EL5172, EL5372
Typical Performance Curves
A
= 1, R = 500Ω, C = 2.7pF
A = 1, R = 100Ω, C = 2.7pF
V L L
V
L
L
4
3
4
3
2
2
1
1
0
0
V
= ±5V
S
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
V
= ±5V
S
V
= ±2.5V
S
V
= ±2.5V
S
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
V
= ±5V, R = 500Ω, C = 2.7pF
L L
V
= ±5V, A = 1, R = 500Ω
V L
S
S
5
4
4
3
C
= 56pF
L
3
2
C = 33pF
L
2
1
C
= 15pF
L
1
0
A
= 1
0
-1
-2
-3
-4
-5
-6
V
-1
-2
-3
-4
-5
C
= 10pF
L
A
= 2
V
C
= 2.7pF
L
A
= 5
V
A
= 10
V
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE vs VARIOUS GAIN
FIGURE 4. FREQUENCY RESPONSE vs C
L
V
= ±5V, A = 1, R = 500Ω
V
= ±5V, A = 2, R = 500Ω, C = 2.7pF
V L L
S
V
L
S
5
4
4
3
C
= 56pF
L
3
2
C
= 33pF
L
2
1
R
= 1kΩ
F
1
0
C
= 15pF
L
R
= 500Ω
F
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
C
= 10pF
R
= 200Ω
L
F
C
= 2.7pF
L
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE vs C
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS R
F
L
FN7311.8
January 25, 2008
7
EL5172, EL5372
Typical Performance Curves (Continued)
A
= 1, R = 500Ω, C = 2.7pF
V
L
L
4
3
270
225
180
135
90
60
50
40
2
1
30
0
20
V
= ±5V
S
-1
-2
-3
-4
-5
-6
45
10
0
0
V
= ±2.5V
S
-45
-90
-135
-180
-10
-20
-30
-40
1M
10M
100M
1G
1M
FREQUENCY (Hz)
10k
100k
10M
100M
500M
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE FOR V
FIGURE 8. OPEN LOOP GAIN
REF
100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
10
1
PSRR+
PSRR-
0.1
10k
100k
1M
10M
100M
100k
FREQUENCY (Hz)
1k
10k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 9. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 10. PSRR vs FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
1k
100
10
E
N
I
N
1
10
10M
10k
FREQUENCY (Hz)
100k
1M
100M
1G
100
1k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 11. CMRR vs FREQUENCY
FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FN7311.8
January 25, 2008
8
EL5172, EL5372
Typical Performance Curves (Continued)
V
= ±5V, R = 500Ω, f = 5MHz
S
L
0
-10
-20
-30
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
CH1 <=> CH2, CH2 <=> CH3
-50
-60
-70
HD3 (A = 1)
V
CH1 <=> CH3
-80
-90
-100
100k
10M
4
1M
100M
1G
1
2
3
5
7
6
FREQUENCY (Hz)
V
(V)
OP-P
FIGURE 13. CHANNEL ISOLATION vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE
V
V
= ±5V, f = 5MHz, V
= 1V @A = 1,
OP-P V
V
V
= ±5V, R = 500Ω, V
= 1V FOR A = 1,
OP-P V
S
S
L
= 2V @A = 2
= 2V for A = 2
OP-P
V
OP-P
V
-45
-50
-55
-60
-65
-70
-75
-80
-85
-80
-40
-50
-60
-70
HD3 (A = 1)
V
-80
-90
HD3 (A = 1)
V
-100
100 200 300 400 500 600 700 800 900 1000
(Ω)
0
5
10
15
20
25
30
35
40
R
LOAD
FREQUENCY (MHz)
FIGURE 15. HARMONIC DISTORTION vs LOAD RESISTANCE
FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
50mV/DIV
0.5V/DIV
10ns/DIV
10ns/DIV
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
FN7311.8
January 25, 2008
9
EL5172, EL5372
Typical Performance Curves (Continued)
M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
M = 100ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
CH1
CH1
CH2
CH2
400ns/DIV
100ns/DIV
FIGURE 19. ENABLED RESPONSE
FIGURE 20. DISABLED RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1.4
1.136W
909mW
870mW
1.2
1.0
0.8
0.6
0.4
0.2
0
1.0
870mW
QSOP24
θ
= +88°C/W
JA
0.8
0.6
QSOP24
625mW
θ
= +115°C/W
JA
SOIC8
SOIC8
= +160°C/W
θ
= +110°C/W
JA
θ
JA
0.4 486mW
MSOP8/10
= +115°C/W
θ
JA
MSOP8
0.2
θ
= +206°C/W
JA
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Simplified Schematic
V +
S
I
I
I
I
R
R
4
1
2
3
4
3
R
R
D1
D2
Q
8
V
VIN+
VIN-
FBP
FBN
Q
7
B1
Q
Q
Q
Q
1
2
3
4
Q
9
x1
V
OUT
Q
6
25
V
B2
C
C
R
R
1
2
V -
S
FN7311.8
January 25, 2008
10
EL5172, EL5372
Choice of Feedback Resistor and Gain Bandwidth
Product
Description of Operation and Application
Information
For applications that require a gain of +1, no feedback
resistor is required. Just short the OUT pin to the FB pin. For
gains greater than +1, the feedback resistor forms a pole
with the parasitic capacitance at the inverting input. As this
pole becomes smaller, the amplifier's phase margin is
reduced. This causes ringing in the time domain and
Product Description
The EL5172 and EL5372 are wide bandwidth, low power
and single/differential ended to single ended output
amplifiers. The EL5172 is a single channel differential to
single ended amplifier. The EL5372 is a triple channel
differential to single ended amplifier. The EL5172 and
EL5372 are internally compensated for closed loop gain of
+1 or greater. Connected in gain of 1 and driving a 500Ω
load, the EL5172 and EL5372 have a -3dB bandwidth of
250MHz. Driving a 150Ω load at gain of 2, the bandwidth is
about 50MHz. The bandwidth at the REF input is about
450MHz. The EL5172 and EL5372 are available with a
power-down feature to reduce the power while the amplifier
is disabled.
peaking in the frequency domain. Therefore, R has some
F
maximum value that should not be exceeded for optimum
performance. If a large value of R must be used, a small
F
capacitor in the few Pico farad range in parallel with R can
F
help to reduce the ringing and peaking at the expense of
reducing the bandwidth.
The bandwidth of the EL5172 and EL5372 depends on the
load and the feedback network. R and R appear in
F
G
parallel with the load for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
Input, Output and Supply Voltage Range
Consequently, R also has a minimum value that should not
be exceeded for optimum bandwidth performance. For a
The EL5172 and EL5372 have been designed to operate
with a single supply voltage of 5V to 10V or a split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.3V to 3.3V for
±5V supply. The differential mode input range (DMIR)
between the two inputs is about from -2.3V to +2.3V. The
input voltage range at the REF pin is from -3.6V to 3.3V. If
the input common mode or differential mode signal is outside
the above-specified ranges, it will cause the output signal to
be distorted.
F
gain of +1, R = 0 is optimum. For the gains other than +1,
F
optimum response is obtained with R between 500Ω to
F
1kΩ. For A = 2 and R = R = 1kΩ, the BW is about 80MHz
V
F
G
and the frequency response is very flat.
The EL5172 and EL5372 have a gain bandwidth product of
100MHz. For gains ≥5, its bandwidth can be predicted by
Equation 1:
(EQ. 1)
Gain × BW = 100MHz
The output of the EL5172 and EL5372 can swing from -3.8V
to 3.6V at 500Ω load at ±5V supply. As the load resistance
becomes lower, the output swing is reduced respectively.
Driving Capacitive Loads and Cables
The EL5172 and EL5372 can drive 56pF capacitance in
parallel with 500Ω load to ground with 4dB of peaking at gain
of +1. If less peaking is desired in applications, a small
series resistor (usually between 5Ω to 50Ω) can be placed in
series with each output to eliminate most peaking. However,
this will reduce the gain slightly. If the gain setting is greater
Over All Gain Settings
The gain setting for the EL5172 and the EL5372 is similar to
the conventional operational amplifier. The output voltage is
equal to the difference of the inputs plus V
times the gain.
and then
REF
R
than 1, the gain resistor R can then be chosen to make up
for any gain loss which may be created by the additional
series resistor at the output.
⎛
⎞
⎟
⎠
F
G
--------
V
= (V + – V - + V
) × 1 +
⎜
O
IN
IN
REF
R
G
⎝
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
EN
V
V
+
+
-
IN
-
IN
Σ
G/B
V
O
V
+
-
REF
FB
R
F
Disable/Power-Down
R
G
The EL5172 and EL5372 can be disabled and its outputs
placed in a high impedance state. The turn-off time is about
1.4µs and the turn-on time is about 150ns. When disabled,
FIGURE 23.
the amplifier's supply current is reduced to 80µA for I + and
S
FN7311.8
January 25, 2008
11
EL5172, EL5372
120µA for I - typically, thereby effectively eliminating the
For sourcing, use Equation 3:
S
power consumption. The amplifier's power-down can be
controlled by standard CMOS signal levels at the ENABLE
V
OUT
(EQ. 3)
(EQ. 4)
-------------------
PD
=
V
× I
+ (V + – V ) ×
OUT
× i
MAX
S
SMAX
S
R
LOAD
pin. The applied logic signal is relative to V + pin. Letting the
S
EN pin float or applying a signal that is less than 1.5V below
For sinking, use Equation 4:
V + will enable the amplifier. The amplifier will be disabled
S
when the signal at EN pin is above V + - 0.5V. If a TTL
S
signal is used to control the enabled/disabled function,
Figure 24 could be used to convert the TTL signal to CMOS
PD
= [V × I
+ (V
– V -) × I
] × i
LOAD
MAX
S
SMAX
OUT
S
signal.
Where:
• V = Total supply voltage
5V
S
10k
• I
= Maximum quiescent supply current per channel
= Maximum output voltage of the application
SMAX
EN
1k
CMOS/TTL
• V
OUT
• R
= Load resistance
LOAD
• I
= Load current
LOAD
• i = Number of channels
By setting the two PD
FIGURE 24.
Output Drive Capability
equations equal to each other, we
MAX
The EL5172 and EL5372 have internal short circuit
protection. Its typical short circuit current is ±95mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnections.
can solve the output current and R
overheat.
to avoid the device
LOAD
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
Power Dissipation
With the high output drive capability of the EL5172 and
EL5372, it is possible to exceed the +135°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
For normal single supply operation, where the V - pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from V +
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
S
S
be used. In this case, the V - pin becomes the negative
S
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
The maximum power dissipation allowed in a package is
determined according to Equation 2:
T
– T
AMAX
JMAX
(EQ. 2)
--------------------------------------------
PD
=
MAX
Θ
JA
• T
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
• θ = Thermal resistance of the package
JA
Assuming the REF pin is tied to GND for V = ±5V
S
application, the maximum power dissipation actually
produced by an IC is the total quiescent supply current times
the total power supply voltage, plus the power in the IC due
to the load, or:
FN7311.8
January 25, 2008
12
EL5172, EL5372
Typical Applications
0Ω
50
50
V
V
FB
50Ω
50Ω
EL5173,
EL5373
OR
EL5172,
EL5372
IN
EL5172,
EL5372
V
OUT
V
V
INB
Z
= 100Ω
O
REF
FIGURE 25. TWISTED PAIR CABLE RECEIVER
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
for this loss is to boost the high frequency gain at the
receiver side.
R
R
R
2
3
1
GAIN
(dB)
C
1
1 + R /R
2
1
V
V
FB
IN
50Ω
50Ω
EL5172,
EL5372
V
OUT
V
V
INB
1 + R /(R + R )
2
1
3
Z
= 100Ω
O
REF
f
f
f
A
C
FIGURE 26. COMPENSATED LINE RECEIVER
Level Shifter and Signal Summer
The EL5172 and EL5372 contains two pairs of differential
pair input stages, which make sure that the inputs are all
high impedance inputs. To take advantage of the two high
impedance inputs, the EL5172 and EL5372 can be used as
a signal summer to add two signals together. One signal can
be applied to VIN+, the second signal can be applied to REF
and V - is ground. The output is equal to Equation 5:
IN
V
= (V + + V
) × Gain
REF
(EQ. 5)
O
IN
Also, the EL5172 and EL5372 can be used as a level shifter
by applying a level control signal to the REF input.
FN7311.8
January 25, 2008
13
EL5172, EL5372
Small Outline Package Family (SO)
A
D
h X 45¬
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL ‚Äö
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4¬¨Ðó
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7311.8
January 25, 2008
14
EL5172, EL5372
Quarter Size Outline Plastic Packages Family (QSOP)
A
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
A
A1
A2
b
0.068
0.006
0.056
0.010
0.008
0.193
0.236
0.154
0.025
0.025
0.041
16
0.068
0.006
0.056
0.010
0.008
0.341
0.236
0.154
0.025
0.025
0.041
24
0.068
0.006
0.056
0.010
0.008
0.390
0.236
0.154
0.025
0.025
0.041
28
Max.
±0.002
±0.004
±0.002
±0.001
±0.004
±0.008
±0.004
Basic
-
PIN #1
I.D. MARK
E
E1
-
-
-
1
(N/2)
c
-
B
D
1, 3
0.010 C A B
E
-
e
E1
e
2, 3
H
-
C
SEATING
L
±0.009
Basic
-
PLANE
L1
N
-
0.007 C A B
b
0.004 C
Reference
-
Rev. F 2/07
L1
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
A
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4¬¨Ðó
DETAIL X
FN7311.8
January 25, 2008
15
EL5172, EL5372
Mini SO Package Family (MSOP)
MDP0043
0.25 M C A B
A
MINI SO PACKAGE FAMILY
D
(N/2)+1
MILLIMETERS
N
SYMBOL
MSOP8
1.10
0.10
0.86
0.33
0.18
3.00
4.90
3.00
0.65
0.55
0.95
8
MSOP10
1.10
0.10
0.86
0.23
0.18
3.00
4.90
3.00
0.50
0.55
0.95
10
TOLERANCE
Max.
NOTES
A
A1
A2
b
-
±0.05
-
E
E1
PIN #1
I.D.
±0.09
-
+0.07/-0.08
±0.05
-
c
-
D
±0.10
1, 3
1
B
(N/2)
E
±0.15
-
E1
e
±0.10
2, 3
Basic
-
e
H
C
L
±0.15
-
SEATING
PLANE
L1
N
Basic
-
Reference
-
M
C A B
b
0.08
0.10 C
Rev. D 2/07
N LEADS
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
0.25
L
DETAIL X
A1
3¬¨Ðó
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN7311.8
January 25, 2008
16
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