EL5177IY-T13 [INTERSIL]
550MHz Differential Twisted-Pair Driver; 550MHz的差分双绞线驱动器
| 型号： | EL5177IY-T13 |
| 厂家： | 
Intersil |
| 描述： | 550MHz Differential Twisted-Pair Driver |
| 文件： | 总11页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5177
®
Data Sheet
August 11, 2004
FN7344.2
550MHz Differential Twisted-Pair Driver
Features
• Pb-free available
The EL5177 is a high bandwidth
amplifier with an output in differential
• Fully differential inputs, outputs, and feedback
• Differential input range ±2.3V
• 550MHz 3dB bandwidth
form. It is primarily targeted for
applications such as driving twisted-pair lines or any
application where common mode injection is likely to occur.
The input signal can be in either single-ended or differential
form but the output is always in differential form.
• 1100V/µs slew rate
• Low distortion at 20MHz
On the EL5177, two feedback inputs provide the user with
the ability to set the device gain (stable at minimum gain of
one.)
• Single 5V or dual ±5V supplies
• 40mA maximum output current
• Low power - 12.5mA typical supply current
The output common mode level is set by the reference pin
(REF), which has a -3dB bandwidth of 110MHz. Generally,
this pin is grounded but it can be tied to any voltage
reference.
Applications
• Twisted-pair drivers
Both outputs (OUT+, OUT-) are short circuit protected to
withstand temporary overload condition.
• Differential line drivers
• VGA over twisted-pair
The EL5177 is available in the 10-pin MSOP package and is
specified for operation over the full -40°C to +85°C
temperature range.
• ADSL/HDSL drivers
• Single ended to differential amplification
• Transmission of analog signals in a noisy environment
See also EL5174 (EL5177 in 8-pin MSOP.)
Ordering Information
Pinout
PART
EL5177
(10-PIN MSOP)
TOP VIEW
NUMBER
PACKAGE
10-Pin MSOP
10-Pin MSOP
10-Pin MSOP
TAPE & REEL PKG. DWG. #
EL5177IY
-
7”
13”
-
MDP0043
MDP0043
MDP0043
MDP0043
EL5177IY-T7
EL5177IY-T13
FBP
IN+
1
2
3
4
5
10 OUT+
9
8
7
6
VS-
EL5177IYZ
(See Note)
10-Pin MSOP
(Pb-free)
+
-
REF
IN-
VS+
EN
EL5177IYZ-T7 10-Pin MSOP
7”
MDP0043
MDP0043
(See Note)
(Pb-free)
FBN
OUT-
EL5177IYZ-
T13 (See Note)
10-Pin MSOP
(Pb-free)
13”
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL5177
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage (V + to V -) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Recommended Operating Temperature . . . . . . . . . .-40°C to +85°C
S
S
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+135°C
V
V
, V , V . . . . . . . . . . V - + 0.8V (min) to V + - 0.8V (max)
IN INB REF S S
- V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±5V
IN
INB
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, T = 25°C, V = 0V, R = 1kΩ, R = 0, R = OPEN, C = 2.7pF, Unless Otherwise
S
S
A
IN
LD
F
G
LD
Specified
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
A
= 1, C = 2.7pF
LD
550
130
20
MHz
MHz
MHz
MHz
V/µs
ns
V
A
= 2, R = 500, C = 2.7pF
LD
V
F
A
= 10, R = 500, C = 2.7pF
V
F
LD
BW
SR
±0.1dB Bandwidth
Slew Rate
A
= 1, C = 2.7pF
120
1100
10
V
LD
V
V
= 3V , 20% to 80%
P-P
800
OUT
OUT
T
T
Settling Time to 0.1%
= 2V
P-P
STL
Output Overdrive Recovery Time
Gain Bandwidth Product
20
ns
OVR
GBWP
200
110
134
70
MHz
MHz
V/µs
V/µs
nV/√Hz
pA/√Hz
dBc
dBc
dBc
dBc
%
V
V
V
V
BW (-3dB) V
-3dB Bandwidth
Slew Rate - Rise
Slew Rate - Fall
A =1, C = 2.7pF
V LD
REF
REF
REF
N
REF
REF
REF
SR+
SR-
V
V
V
V
= 2V , 20% to 80%
P-P
OUT
OUT
= 2V , 20% to 80%
P-P
Input Voltage Noise
at 10kHz
at 10kHz
21
I
Input Current Noise
2.7
-95
-94
-88
-87
0.06
0.13
N
HD2
Second Harmonic Distortion
V
V
V
V
= 2V , 5MHz
P-P
OUT
OUT
OUT
OUT
= 2V , 20MHz
P-P
HD3
Third Harmonic Distortion
= 2V , 5MHz
P-P
= 2V , 20MHz
P-P
dG
Differential Gain at 3.58MHz
Differential Phase at 3.58MHz
R
= 300Ω, A =2
LD
LD
V
dθ
R
= 300Ω, A =2
°
V
INPUT CHARACTERISTICS
Input Referred Offset Voltage
V
±1.4
-14
2.3
150
1
±25
-7
mV
µA
µA
kΩ
pF
V
OS
I
I
Input Bias Current (V +, V -)
-20
0.5
IN
REF
IN
IN
Input Bias Current (V
)
4
REF
R
Differential Input Resistance
Differential Input Capacitance
Differential Mode Input Range
IN
IN
C
DMIR
±2.1
3.4
±2.3
3.4
-4.3
3.7
-3.3
±2.5
-3
CMIR+
CMIR-
Common Mode Positive Input Range at V +, V
IN
-
V
IN
Common Mode Negative Input Range at V +, V
IN
-
V
IN
V
V
+
-
Positive Reference Input Voltage Range
Negative Reference Input Voltage Range
V
V
+ = V - = 0V
IN
V
REFIN
IN
IN
+ = V - = 0V
IN
V
REFIN
2
EL5177
Electrical Specifications V + = +5V, V - = -5V, T = 25°C, V = 0V, R = 1kΩ, R = 0, R = OPEN, C = 2.7pF, Unless Otherwise
S
S
A
IN
LD
F
G
LD
Specified (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
±50
MAX
UNIT
mV
dB
V
Output Offset Relative to V
±100
REFOS
CMRR
REF
Input Common Mode Rejection Ratio
V
V
= ±2.5V
65
78
IN
IN
Gain
Gain Accuracy
= 1V
0.980
0.995
1.010
-30
V
OUTPUT CHARACTERISTICS
V
Output Voltage Swing
R
R
V
V
V
= 500Ω to GND
= 10Ω,
+ = 1.1V,
- = -1.1V,
±3.6
35
±3.8
50
V
OUT
L
I
I
+(Max)
Maximum Source Output Current
Maximum Sink Output Current
mA
mA
OUT
OUT
L
IN
IN
REF
-(Max)
-40
= 0
R
Output Impedance
130
mΩ
OUT
SUPPLY
V
Supply Operating Range
V + to V -
4.75
10
11
14
V
SUPPLY
S
S
I
I
I
Power Supply Current - Per Channel
12.5
76
mA
µA
µA
dB
S(ON)
+
-
Positive Power Supply Current - Disabled
Negative Power Supply Current - Disabled
Power Supply Rejection Ratio
EN pin tied to 4.8V
120
S(OFF)
S(OFF)
-200
60
-120
75
PSRR
ENABLE
V from ±4.5V to ±5.5V
S
t
t
Enable Time
130
1.2
ns
µs
V
EN
DS
Disable Time
V
EN Pin Voltage for Power-Up
V + -
S
IH
1.5
V
EN Pin Voltage for Shut-Down
V + -
S
V
IL
0.5
I
I
EN Pin Input Current High
EN Pin Input Current Low
At V
At V
= 5V
= 0V
40
50
µA
µA
IH-EN
IL-EN
EN
EN
-6
-2.5
Pin Descriptions
PIN NUMBER
PIN NAME
FBP
PIN DESCRIPTION
1
2
Non-inverting feedback input; resistor R must be connected from this pin to V
F1
OUT
IN+
Non-inverting input
3
REF
IN-
Output common-mode control; the common-mode voltage of V
Inverting input
will follow the voltage on this pin
OUT
4
5
FBN
OUT-
EN
Inverting feedback input; resistor R must be connected from this pin to V
F2
OUT
6
Inverting output
7
Enabled when this pin is floating or the applied voltage ≤ V + -1.5
S
8
VS+
Positive supply
9
VS-
Negative supply
Non-inverting output
10
OUT+
3
EL5177
Connection Diagram
R
F1
0Ω
VREF
INP
R
50Ω
S3
1
2
3
4
5
FBP
IN+
OUT+ 10
OUT+
VS-
VS+
EN
9
8
7
6
-5V
R
50Ω
R
S1
LD
1kΩ
R
OPEN
G
REF
IN-
+5V
EN
OUT-
INN-
R
S2
50Ω
FBN
OUT-
R
F2
0Ω
Typical Performance Curves
A
= 1, R = 1kΩ, C = 2.7pF
LD LD
R
= 1kΩ, C = 2.7pF
LD
V
LD
4
3
4
3
2
2
V
= 200mV
OP-P
1
1
A
= 1
V
0
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
A
= 2
V
V
= 1V
OP-P
A
= 5
V
A
= 10
V
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS GAIN
A
= 1, C = 2.7pF
LD
A
= 1, R = 1kΩ
V
V
LD
4
3
10
C
= 50pF
LD
8
6
C
= 23pF
LD
2
C
= 34pF
LD
R
= 1kΩ
LD
1
4
0
2
-1
-2
-3
-4
-5
-6
0
R
= 500Ω
= 200Ω
C
= 9pF
LD
R
LD
-2
-4
-6
-8
-10
C
= 2.7pF
LD
LD
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 4. FREQUENCY RESPONSE vs R
LD
FIGURE 3. FREQUENCY RESPONSE vs C
LD
4
EL5177
Typical Performance Curves (Continued)
A
= 2, R = 1kΩ, C = 2.7pF
A
= 2, C = 2.7pF, R = 750Ω
LD
V
LD
LD
V
F
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
R
= 1kΩ
F
R
= 1kΩ
LD
R
= 500Ω
R
= 500Ω
F
LD
R
= 200Ω
F
R
= 200Ω
LD
1M
10M
FREQUENCY (Hz)
100M
400M
1M
10M
FREQUENCY (Hz)
100M
400M
FIGURE 5. FREQUENCY RESPONSE
FIGURE 6. FREQUENCY RESPONSE vs R
LD
0
5
4
-10
-20
-30
-40
-50
-60
-70
-80
-90
3
2
1
PSRR-
0
-1
-2
-3
-4
-5
PSRR+
10M
1M
FREQUENCY (Hz)
10K
100K
100M
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 8. PSRR vs FREQUENCY
FIGURE 7. FREQUENCY RESPONSE - V
REF
1K
100
10
100
80
60
40
20
0
E
N
I
N
1
10
-20
1K
10K
FREQUENCY (Hz)
100
1K
100K
1M
10M
1M
10M
10K
100K
100M
1G
FREQUENCY (Hz)
FIGURE 10. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 9. CMRR vs FREQUENCY
5
EL5177
Typical Performance Curves (Continued)
V
= ±5V, A = 1, R = 1kΩ
LD
S
V
100
-40
-50
HD3 (f = 5MHz)
10
1
-60
HD3 (f = 20MHz)
-70
-80
-90
HD2 (f = 20MHz)
4.5 5
HD2 (f = 5MHz)
0.1
10K
-100
100K
1M
10M
100M
1
1.5
2
2.5
V
3
3.5
(V)
4
FREQUENCY (Hz)
OP-P, DM
FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 12. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
V
= ±5V, A = 1, V
= 1V
OP-P, DM
S
V
V
= ±5V, A = 2, R = 1kΩ
LD
S
V
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-40
-50
-60
HD3 (f = 20MHz)
-70
-80
-90
HD2 (f = 5MHz)
-100
100 200 300 400 500 600 700 800 900 1000
(Ω)
1
2
3
4
5
6
7
8
9
10
V
(V)
R
OP-P, DM
LD
FIGURE 13. HARMONIC DISTORTION vs DIFFERENTIAL
OUTPUT VOLTAGE
FIGURE 14. HARMONIC DISTORTION vs R
LD
V
= ±5V, R = 1kΩ, V
= 1V for A = 1,
S
LD
OP-P, DM V
V
= ±5V, A = 2, V
= 2V
S
V
OP-P, DM
V
= 2V for A = 2
V
OP-P, DM
-40
-50
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
HD3 (f = 20MHz)
HD3 (A = 2)
V
HD3 (f = 5MHz)
-60
-70
-80
HD2 (f = 2
0MHz)
-90
HD2 (f = 5MHz)
-100
0
10
20
30
40
50
60
200 300 400 500 600 700 800 900 1000
(Ω)
FREQUENCY (MHz)
R
LD
FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
FIGURE 15. HARMONIC DISTORTION vs R
LD
6
EL5177
Typical Performance Curves (Continued)
50mV/DIV
0.5V/DIV
10ns/DIV
10ns/DIV
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
M = 400ns, CH1 = 500mV/DIV, CH2 = 5V/DIV
CH1
CH2
CH1
CH2
400ns/DIV
400ns/DIV
FIGURE 20. DISABLED RESPONSE
FIGURE 19. ENABLED RESPONSE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
CONDUCTIVITY TEST BOARD
0.6
0.9
0.5
870mW
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
486mW
MSOP8/10
MSOP8/10
0.4
θ
=115°C/W
JA
θ
=206°C/W
JA
0.3
0.2
0.1
0
0
25
50
75 85 100
125
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
7
EL5177
Simplified Schematic
V +
S
R
R
3
4
R
R
2
1
R
R
7
8
IN+
IN-
FBP
FBN
V
V
B1
OUT+
R
R
CD
CD
REF
10
R
R
9
OUT-
B2
C
C
C
C
R
R
6
5
V -
S
The gain setting for EL5177 is:
Description of Operation and Application
Information
Product Description
The EL5177 is a wide bandwidth, low power and
single/differential ended to differential output amplifier. It can
be used as single/differential ended to differential converter.
The EL5177 is internally compensated for closed loop gain
of +1 of greater. Connected in gain of 1 and driving a 1kΩ
differential load, the EL5177 has a -3dB bandwidth of
550MHz. Driving a 200Ω differential load at gain of 2, the
bandwidth is about 130MHz. The EL5177 is available with a
power down feature to reduce the power while the amplifier
is disabled.
R
+ R
F2
F1
V
= (V + – V -) × 1 + ---------------------------
ODM
IN
IN
R
G
2R
F
V
V
= (V + – V -) × 1 + ----------
ODM
OCM
IN
IN
R
G
= V
REF
Where:
• R = R = R
F1 F2
F
R
F1
Input, Output, and Supply Voltage Range
FBP
The EL5177 has been designed to operate with a single
supply voltage of 5V to 10V or a split supplies with its total
voltage from 5V to 10V. The amplifiers have an input
common mode voltage range from -4.3V to 3.4V for ±5V
supply. The differential mode input range (DMIR) between
the two inputs is from -2.3V to +2.3V. The input voltage
range at the REF pin is from -3.3V to 3.7V. If the input
common mode or differential mode signal is outside the
above-specified ranges, it will cause the output signal
distorted.
V
+
V
V
+
-
IN
O
I +
N
R
G
V
-
IN
I -
N
V
REF
FBN
REF
O
R
F2
FIGURE 23.
Choice of Feedback Resistor and Gain Bandwidth
Product
The output of the EL5177 can swing from -3.8V to +3.8V at
1kΩ differential load at ±5V supply. As the load resistance
becomes lower, the output swing is reduced.
For applications that require a gain of +1, no feedback
resistor is required. Just short the OUT+ pin to FBP pin and
OUT- pin to FBN pin. For gains greater than +1, the
feedback resistor forms a pole with the parasitic capacitance
at the inverting input. As this pole becomes smaller, the
amplifier's phase margin is reduced. This causes ringing in
the time domain and peaking in the frequency domain.
Differential and Common Mode Gain Settings
The voltage applied at REF pin can set the output common
mode voltage and the gain is one. The differential gain is set
by the R and R network.
F
G
Therefore, R has some maximum value that should not be
F
8
EL5177
exceeded for optimum performance. If a large value of R
maintained if the output current never exceeds ±40mA. This
F
must be used, a small capacitor in the few Pico farad range
limit is set by the design of the internal metal interconnect.
in parallel with R can help to reduce the ringing and
F
Power Dissipation
peaking at the expense of reducing the bandwidth.
With the high output drive capability of the EL5177. It is
possible to exceed the 135°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if the load
conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
The bandwidth of the EL5177 depends on the load and the
feedback network. R and R appear in parallel with the
F
G
load for gains other than +1. As this combination gets
smaller, the bandwidth falls off. Consequently, R also has a
F
minimum value that should not be exceeded for optimum
bandwidth performance. For gain of +1, R = 0 is optimum.
F
For the gains other than +1, optimum response is obtained
The maximum power dissipation allowed in a package is
determined according to:
with R between 500Ω to 1kΩ.
F
The EL5177 has a gain bandwidth product of 200MHz for
T
– T
AMAX
R
= 1kΩ. For gains ≥5, its bandwidth can be predicted by
LD
JMAX
PD
= --------------------------------------------
MAX
the following equation:
Θ
JA
Gain × BW = 200MHz
Where:
• T
= Maximum junction temperature
Driving Capacitive Loads and Cables
JMAX
The EL5177 can drive 23pF differential capacitor in parallel
with 1kΩ differential load with less than 5dB of peaking at
gain of +1. If less peaking is desired in applications, a small
series resistor (usually between 5Ω to 50Ω) can be placed in
series with each output to eliminate most peaking. However,
this will reduce the gain slightly. If the gain setting is greater
• T
AMAX
= Maximum ambient temperature
• θ = Thermal resistance of the package
JA
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
than 1, the gain resistor R can then be chosen to make up
∆V
G
O
-----------
PD = V × I
+ V ×
S
for any gain loss which may be created by the additional
series resistor at the output.
S
SMAX
R
LD
Where:
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
• V = Total supply voltage
S
• I
= Maximum quiescent supply current per channel
SMAX
• ∆V = Maximum differential output voltage of the
O
application
• R = Differential load resistance
LD
• I
= Load current
LOAD
Disable/Power-Down
By setting the two PD
equations equal to each other, we
MAX
The EL5177 can be disabled and placed its outputs in a high
impedance state. The turn off time is about 1.2µs and the
turn on time is about 130ns. When disabled, the amplifier's
supply current is reduced to 1.7µA for I + and 120µA for I -
can solve the output current and R to avoid the device
LD
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
S
S
typically, thereby effectively eliminating the power
consumption. The amplifier's power down can be controlled
by standard CMOS signal levels at the EN pin. The applied
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
logic signal is relative to V + pin. Letting the EN pin float or
S
applying a signal that is less than 1.5V below V + will enable
S
the amplifier. The amplifier will be disabled when the signal
normal single supply operation, where the V - pin is
S
at EN pin is above V + - 0.5V.
S
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from V +
S
Output Drive Capability
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
The EL5177 has internal short circuit protection. Its typical
short circuit current is ±40mA. If the output is shorted
indefinitely, the power dissipation could easily increase such
that the part will be destroyed. Maximum reliability is
be used. In this case, the V - pin becomes the negative
supply rail.
S
9
EL5177
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
Typical Applications
R
F
FBP
IN+
IN-
50
50
TWISTED PAIR
IN+
R
R
G
T
EL5177
EL5175
V
O
REF
IN-
Z
= 100Ω
O
FBN
REF
R
F
R
FR
R
GR
FIGURE 24. TWISTED PAIR CABLE RECEIVER
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
this loss is to boost the high frequency gain at the receiver
side.
R
F
Gain
(dB)
FBP
I +
V
V
+
-
O
N
R
75
T
R
R
G
GC
I -
N
C
REF
FBN
L
O
f
f
H
frequency
R
L
F
2R
1
F
------------------------
≅
f
DC Gain = 1 + ----------
L
2πR
C
C
R
G
G
1
----------------------------
≅
2R
f
F
H
2πR
C
C
(HF)Gain = 1 + --------------------------
GC
||
R
R
GC
G
FIGURE 25. TRANSMIT EQUALIZER
10
EL5177
MSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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