EL5225 [INTERSIL]
10-Channel TFT-LCD Reference Voltage Generator; 10通道TFT -LCD参考电压发生器
| 型号： | EL5225 |
| 厂家： | 
Intersil |
| 描述： | 10-Channel TFT-LCD Reference Voltage Generator |
| 文件： | 总12页 (文件大小：859K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5225
®
Data Sheet
March 11, 2004
FN7356.0
10-Channel TFT-LCD Reference Voltage
Generator
Features
• 10-channel reference outputs
• Accuracy of ±1%
The EL5225 is designed to produce the reference voltages
required in TFT-LCD applications. Each output is
programmed to the required voltage with 10 bits of
resolution. Reference pins determine the high and low
voltages of the output range, which are capable of swinging
to either supply rail. Programming of each output is
performed using the 3-wire, SPI compatible interface.
• Supply voltage of 5V to 16.5V
• Digital supply 3.3V to 5V
• Low supply current of 9mA
• Rail-to-rail capability
A number of the EL5225 can be stacked for applications
requiring more than 10 outputs. The reference inputs can be
tied to the rails, enabling each part to output the full voltage
range, or alternatively, they can be connected to external
resistors to split the output range and enable finer
resolutions of the outputs.
• Pb-free available (RoHS compliant)
Applications
• TFT-LCD drive circuits
• Reference voltage generators
The EL5225 has 10 outputs, and is available in the 24-pin
TSSOP package. They are specified for operation over the
full -40°C to +85°C temperature range.
Pinout
EL5225
(24-PIN TSSOP)
TOP VIEW
Ordering Information
1
2
24
23
22
21
20
19
18
17
16
15
14
13
ENA
SDI
OUTA
PART
NUMBER
(See Note)
PACKAGE
(Pb-Free)
TAPE &
REEL
OUTB
OUTC
GND
PKG. DWG. #
MDP0044
MDP0044
MDP0044
3
SCLK
SDO
EL5225IRZ
24-Pin TSSOP
24-Pin TSSOP
-
EL5225IRZ-T7
7”
4
EL5225IRZ-T13 24-Pin TSSOP
13”
5
EXT_OSC
VS+
OUTD
OUTE
OUTF
OUTG
GND
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
6
7
VSD
8
REFH
REFL
VS+
9
10
OUTH
OUTI
GND 11
CAP 12
OUTJ
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL5225
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V & GND. . . . . . . . 4.5V (min) to 18V (max)
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
S
Supply Voltage between V & GND . . 3V (min) to V and 7V (max)
SD
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications
V
= 15V, V = 5V, V
SD
= 13V, V
= 2V, R = 1.5kΩ and C = 200pF to 0V, T = 25°C, unless
S
REFH
REFL
L
L
A
otherwise specified.
PARAMETER
SUPPLY
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
I
I
Supply Current
No load
9
11.5
0.35
mA
mA
S
Digital Supply Current
0.17
SD
ANALOG
V
V
Output Swing Low
Sinking 5mA (V
= 15V, V
= 0)
50
14.95
140
65
150
mV
V
OL
REFH
REFL
= 15V, V = 0)
REFL
Output Swing High
Sourcing 5mA (V
14.85
100
45
OH
REFH
I
Short Circuit Current
R
= 10Ω
L
mA
SC
PSRR
Power Supply Rejection Ratio
Program to Out Delay
Accuracy referred to the ideal value
Channel to Channel Mismatch
Droop Voltage
V + is moved from 14V to 16V
S
dB
t
4
ms
D
V
Code = 512
Code = 512
20
mV
AC
∆V
2
mV
MIS
V
1
2
mV/ms
kΩ
DROOP
R
Input Resistance @ V
Load Regulation
Band Gap
, V
REFH REFL
32
INH
REG
I
= 5mA step
0.5
1.3
1.5
1.6
mV/mA
V
OUT
CAP
Bypass with 0.1µF
1
DIGITAL
V
Logic 1 Input Voltage
V
V
= 5V
4
2
V
V
IH
SD
= 3.3V
SD
F
Clock Frequency
Logic 0 Input Voltage
Setup Time
5
1
MHz
V
CLK
V
V
= 3.3V/5V
IL
SD
t
t
t
t
t
20
20
20
20
10
1
ns
ns
ns
ns
ns
GΩ
µs
S
Hold Time
H
Load to Clock Time
Clock to Load Line
LC
CE
DCO
Clock to Out Delay Time
S Input Resistance
DIN
Negative edge of SCLK
R
SDIN
T
Minimum Pulse Width for EXT_OSC
Signal
5
PULSE
Duty Cycle
INL
Duty Cycle for EXT_OSC Signal
Integral Nonlinearity Error
50
1.3
0.5
21
%
LSB
LSB
kHz
DNL
Differential Nonlinearity Error
Internal Refresh Oscillator Frequency
F_OSC
OSC_Select = 0
FN7356.0
March 11, 2004
2
EL5225
Pin Descriptions
PIN NUMBER
PIN NAME
PIN TYPE
Logic Input
PIN FUNCTION
1
ENA
SDI
Chip select, low enables data input to logic
Serial data input
2
3
Logic Input
SCLK
SDO
Logic Input
Serial data clock
4
Logic Output
Logic Input/Output
Analog Power
Serial data output
5
EXT_OSC
VS+
External oscillator input or internal oscillator output
Positive supply voltage for analog circuits
Not connected
6, 10
NC
7
VSD
Digital Power
Analog Reference Input
Analog Reference Input
Ground
Positive power supply for digital circuits (3.3V - 5V)
High reference voltage
8
REFH
REFL
GND
9
Low reference voltage
11
12
13
14
15
17
18
19
20
22
23
24
Ground
CAP
Analog Bypass Pin
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Analog Output
Power
Decoupling capacitor for internal reference generator, 0.1µF
Channel J programmable output voltage
Channel I programmable output voltage
Channel H programmable output voltage
Channel G programmable output voltage
Channel F programmable output voltage
Channel E programmable output voltage
Channel D programmable output voltage
Channel C programmable output voltage
Channel B programmable output voltage
Channel A programmable output voltage
Channel L programmable output voltage
Channel K programmable output voltage
Ground
OUTJ
OUTI
OUTH
OUTG
OUTF
OUTE
OUTD
OUTC
OUTB
OUTA
OUTL
OUTK
GND
16, 21
FN7356.0
March 11, 2004
3
EL5225
Typical Performance Curves
0.3
0.2
0.1
1.5
1
REF =13V
H
REF =2V
L
0.5
0
0
-0.1
-0.2
-0.3
V =15V
S
V
V
V
=5V
-0.5
-1
SD
=13V
=2V
REFH
REFL
10
210
410
610
810
1010
0
200
400
600
800
1000
1200
INPUT CODE
CODE
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. INTEGRAL NONLINEARITY ERROR
0mA
5mA
5mA/DIV
5mA
0mA
C =1nF
L
R =20Ω
S
C =4.7nF
L
S
C =4.7nF
L
R =20Ω
R =20Ω
S
5V
200mV/DIV
200mV/DIV
C =1nF
L
C =180pF
L
R =20Ω
S
C =180pF
L
V =V
=15V
V =V =15V
REFH
S
REFH
S
M=400ns/DIV
M=400ns/DIV
FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING)
FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)
SCLK
SCLK
5V
5V
0V
0V
SDA
SDA
5V
5V
0V
10V
5V
0V
OUTPUT
10V
5V
OUTPUT
0V
0V
M=400µs/DIV
M=400µs/DIV
FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
FIGURE 6. LARGE SIGNAL RESPONSE (FALLING FROM 8V
TO 0V)
FN7356.0
March 11, 2004
4
EL5225
Typical Performance Curves (Continued)
SCLK
SCLK
SDA
5V
5V
0V
0V
SDA
5V
0V
5V
0V
200mV
200mV
OUTPUT
OUTPUT
0V
0V
M=400µs/DIV
M=400µs/DIV
FIGURE 7. SMALL SIGNAL RESPONSE (RISING FROM 0V
TO 200mV)
FIGURE 8. SMALL SIGNAL RESPONSE (FALLING FROM
200mV TO 0V)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
CONDUCTIVITY TEST BOARD
1.4
0.9
781mW
0.8
1.176W
1.2
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.8
0.6
0.4
0.2
0
0
25
50
75 85 100
125
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 9. POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 10. POWER DISSIPATION vs AMBIENT
TEMPERATURE
General Description
The EL5225 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
Digital Interface
The EL5225 uses a simple 3-wire SPI compliant digital
interface to program the outputs. The EL5225 can support
the clock rate up to 5MHz.
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5225,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5225. As all of the output
buffers are identical, it is also possible to use the EL5225 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
Serial Interface
The EL5225 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB (bit
15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
FN7356.0
March 11, 2004
5
EL5225
To facilitate the system designs that use multiple EL5225
chips, a buffered serial output of the shift register (SDO pin)
is available. Data appears on the SDO pin at the 16th falling
SCLK edge after being applied to the SDI pin.
TABLE 1. CONTROL BITS LOGIC TABLE
BIT
B15
B14
B13
B12
B11
B10
B9
NAME
Test
Oscillator
A3
DESCRIPTION
Always 0
To control the multiple EL5225 chips from a single three-wire
serial port, just connect the ENA pins and the SCLK pins
together, connect the SDO pin to the SDI pin on the next
chip. While the ENA is held low, the 16m-bit data is loaded to
the SDI input of the first chip. The first 16-bit data will go to
the last chip and the last 16-bit data will go to the first chip.
While the ENA is held high, all addressed outputs will be
updated simultaneously.
0 = Internal, 1 = External
Channel Address
A2
Channel Address
A1
Channel Address
A0
Channel Address
Data
D9
The Serial Timing Diagram and parameters table show the
timing requirements for three-wire signals.
B8
D8
Data
B7
D7
Data
The serial data has a minimum length of 16 bits, the MSB
(most significant bit) is the first bit in the signal. The bits are
allocated to the following functions (also refer to the Control
Bits Logic Table)
B6
D6
Data
B5
D5
Data
B4
D4
Data
• Bit 15 is always set to a zero
B3
D3
Data
• Bit 14 controls the source of the clock, see the next
section for details
B2
D2
Data
• Bits 13 through 10 select the channel to be written to,
these are binary coded with channel A = 0, and channel
H = 7
B1
D1
Data
B0
D0
Data
• The 10-bit data is on bits 9 through 0. Some examples of
data words are shown in the table of Serial Programming
Examples
Serial Timing Diagram
ENA
t
t
T
t
t
t
t
SE
HE
SE
r
f
HE
SCLK
t
t
HD
t
SD
w
SDI
B15
B14
B13
B12-B2
B1
B0
t
MSB
Load MSB first, LSB last
LSB
FN7356.0
March 11, 2004
6
EL5225
TABLE 2. SERIAL TIMING PARAMETERS
PARAMETER
RECOMMENDED OPERATING RANGE
DESCRIPTION
T
≥200ns
0.05 * T
≥10ns
Clock Period
t /t
r f
Clock Rise/Fall Time
ENA Hold Time
t
HE
t
≥10ns
ENA Setup Time
Data Hold Time
SE
t
≥10ns
HD
t
≥10ns
Data Setup Time
Clock Pulse Width
SD
t
0.50 * T
W
TABLE 3. SERIAL PROGRAMMING EXAMPLES
DATA
CONTROL CHANNEL ADDRESS
C1
0
C0
0
A3 A2 A1
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1
D0
CONDITION
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
Internal Oscillator, Channel A, Value = 0
Internal Oscillator, Channel A, Value = 1023
Internal Oscillator, Channel A, Value = 512
0
0
0
0
0
0
1‘t Internal Oscillator, Channel C, Value = 513
0
0
1
1
Internal Oscillator, Channel H, Value = 31
External Oscillator, Channel H, Value = 31
0
1
CLOCK OSCILLATOR
Analog Section
The EL5225 requires an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling OSC
clock edges. The output refreshed switches open at the rising
edges of the OSC clock. The driving load shouldn’t be changed
at the rising edges of the OSC clock. Otherwise, it will generate
a voltage error at the outputs. This clock may be input or output
via the clock pin labeled OSC. The internal clock is provided by
an internal oscillator running at approximately 21kHz and can
be output to the OSC pin. In a 2 chip system, if the driving loads
are stable, one chip may be programmed to use the internal
oscillator; then the OSC pin will output the clock from the
internal oscillator. The second chip may have the OSC pin
connected to this clock source.
TRANSFER FUNCTION
The transfer function is:
data
1024
------------
V
= V
+
× (V
- V
)
REFL
OUT(IDEAL)
REFL
REFH
where data is the decimal value of the 10-bit data binary
input code.
The output voltages from the EL5225 will be derived from
the reference voltages present at the V
pins. The impedance between those two pins is about 32kΩ.
and V
REFL
REFH
Care should be taken that the system design holds these two
reference voltages within the limits of the power rails of the
For transient load application, the external clock Mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect. The
Application Drawing shows the LCD H rate signal used, here
the positive clock edge is timed to avoid the transient load of
the column driver circuits.
EL5225. GND < V
REFH
≤ V and GND ≤ V
REFL
≤ V .
REFH
S
In some LCD applications that require more than 10
channels, the system can be designed such that one
EL5225 will provide the Gamma correction voltages that are
more positive than the V potential. The second EL5225
COM
can provide the Gamma correction voltage more negative
than the V potential. The Application Drawing shows a
COM
system connected in this way.
After power on, the chip will start with the internal oscillator
mode. At this time, the OSC pin will be in a high impedance
condition to prevent contention. By setting B14 to high, the
chip is on external clock mode. Setting B14 to low, the chip is
on internal clock mode.
FN7356.0
March 11, 2004
7
EL5225
Block Diagram
REFERENCE HIGH
OUTA
OUTB
OUTH
OUTI
EIGHT
CHANNEL
MEMORY
VOLTAGE
SOURCES
OUTJ
REFERENCE LOW
REFERENCE DECOUPLE
CLK
SDI
SDO
CONTROL IF
LOAD
FILTER
EXT_OSC
CHANNEL OUTPUTS
and 4.2ms depending on the absolute timing relative to the
update cycle.
Each of the channel outputs has a rail-to-rail buffer. This
enables all channels to have the capability to drive to within
50mV of the power rails, (see Electrical Characteristics for
details).
Output Stage and the Use of External Oscillator
Simplified output sample and hold amp stage for one
channel.
When driving large capacitive loads, a series resistor should
be placed in series with the output. (Usually between 5Ω and
50Ω).
CH
S
1
1.3V
+
-
+
-
V
OUT
1.3V
Each of the channels is updated on a continuous cycle, the
time for the new data to appear at a specific output will
depend on the exact timing relationship of the incoming data
to this cycle.
S
2
V
+
-
IN
OSC
The best-case scenario is when the data has just been
captured and then passed on to the output stage
immediately; this can be as short as 48µs. In the worst-case
scenario, this will be 480µs when the data has just missed
the cycle.
FIGURE 11.
The output voltage is generated from the DAC, which is V
at the above circuit. The refreshed switches are controlled
IN
by the internal or external oscillator signal. When the OSC
When a large change in output voltage is required, the
change will occur in 2V steps, thus the requisite number of
timing cycles will be added to the overall update time. This
means that a large change of 16V can take between 3.8ms
clock signal is low, the switch S and S are closed. The
1
2
output V
= V and at the same time the sample and
OUT
IN
hold cap CH is being charged. When the OSC clock signal is
high, the refreshed switch S and S are opened and the
1
2
output voltage is maintained by CH. This refreshed process
FN7356.0
March 11, 2004
8
EL5225
will repeat every 10-clock cycles for each channel. The time
takes to update the output depends on the timing at the V
IN
and the state of the switches. It can take 1 to 10 clock cycles
to update each output.
V
OUT1
For the sample and hold capacitor CH to maintain the
correct output voltage, the driving load shouldn’t be changed
at the rising edge of the OSC signal. Since at the rising edge
of the OSC clock, the refreshed switches are being opened,
if the load changes at that time, it will generate an error
output voltage. For a fixed load condition, the internal
oscillator can be used.
OSC
V
OUT2
M=400µs/DIV
For the transient load condition, the external OSC mode
should be used to avoid the conflict between the rising edge
of the OSC signal and the changing load. So a timing delay
circuit will be needed to delay the OSC signal and avoid the
rising edge of the OSC signal and changing the load at the
same time.
FIGURE 13. CHANNEL-TO-CHANNEL REFRESH
Ch1 - Output1
Ch3 - Output2
Ch2 - EXT_OSC
At the falling edge of the OSC, output 1 is refreshing and one
clock cycle later, output2 is being refreshed. The spike you
see here is the response of the output amplifier when the
refreshed switches are closed. When driving a big capacitor
load, there will be ringing at the spikes because the phase
margin of the amplifier is decreased.
I
OUT
V
OUT
The speed of the external OSC signal shouldn’t be greater
than 70kHz because for the worst condition, it will take at
least 4µs to charge the sample and hold Capacitor CH. The
pulse width has to be at least 4µs long. From our lab test, the
duty cycle of the OSC signal must be greater than 30%.
OSC
M=400µs/DIV
POWER DISSIPATION
FIGURE 12. TRANSIENT LOAD RESPONSE
With the 30mA maximum continues output drive capability
for each channel, it is possible to exceed the 125°C absolute
maximum junction temperature. Therefore, it is important to
calculate the maximum junction temperature for the
application to determine if load conditions need to be
modified for the part to remain in the safe operation.
Channel 3 - sinking and sourcing 5mA current
Channel 2 - EXT_OSC signal
Channel 1 - V
OUT
Here, the OSC signal is synchronized to the load signal. The
rising edge of the OSC signal is then delayed by some
amount of time and gives enough time for CH to be charged
to a new voltage before the switches are opened.
The maximum power dissipation allowed in a package is
determined according to:
T
- T
AMAX
JMAX
--------------------------------------------
P
=
DMAX
Θ
JA
where:
• T
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
• θ = Thermal resistance of the package
JA
• P
DMAX
= Maximum power dissipation in the package
FN7356.0
March 11, 2004
9
EL5225
The maximum power dissipation actually produced by the IC
is the total quiescent supply current times the total power
supply voltage and plus the power in the IC due to the loads.
POWER SUPPLY BYPASSING AND PRINTED CIRCUIT
BOARD LAYOUT
Good printed circuit board layout is necessary for optimum
performance. A low impedance and clean analog ground
plane should be used for the EL5225. The traces from the
two ground pins to the ground plane must be very short.
Lead length should be as short as possible and all power
supply pins must be well bypassed. A 0.1µF ceramic
P
= V × I + Σ[(V - V
i) × I
i]
LOAD
DMAX
S
S
S
OUT
when sourcing, and:
P
= V × I + Σ(V
i × I
i)
LOAD
DMAX
S
S
OUT
capacitor must be place very close to the V , V
,
S
REFH
V
, and CAP pins. A 4.7µF local bypass tantalum
when sinking.
Where:
REFL
capacitor should be placed to the V , V
pins.
, and V
REFL
S
REFH
• i = 1 to total 10
APPLICATION USING THE EL5225
• V = Supply voltage
S
In the first application drawing, the schematic shows the
interconnect of a pair of EL5225 chips connected to give
• I = Quiescent current
S
10 gamma corrected voltages above the V
10 gamma corrected voltages below the V
voltage, and
voltage.
COM
COM
• V
i = Output voltage of the i channel
OUT
• I
i = Load current of the i channel
LOAD
By setting the two P
equations equal to each other, we
DMAX
s to avoid the device overheat. The
can solve for the R
LOAD
package power dissipation curves provide a convenient way
to see if the device will overheat.
FN7356.0
March 11, 2004
10
EL5225
Application Drawing
HIGH REFERENCE
VOLTAGE
COLUMN
(SOURCE)
DRIVER
+10V
REFH
OUTA
OUTB
OUTC
OUTD
OUTE
OUTF
0.1µF
+12V
VS
0.1µF
LCD PANEL
+5V
0.1µF
VSD
MICROCONTROLLER
SDI
SCK
ENA
SDO
HORIZONTAL
RATE
LCD
TIMING
OSC
CONTROLLER
CAP
0.1µF
OUTI
REFL
GND
OUTJ
EL5225
MIDDLE REFERENCE VOLTAGE
+5.5V
REFH
OSC
OUTA
OUTB
OUTC
OUTD
OUTE
OUTF
+12V
+5V
VS
0.1µF
VSD
0.1µF
SDI
SCK
ENA
CAP
0.1µF
LOW REFERENCE
VOLTAGE
+1V
REFL
0.1µF
OUTI
GND
OUTJ
EL5225
FN7356.0
March 11, 2004
11
EL5225
TSSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil
website at <http://www.intersil.com/design/packages/index.asp>
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7356.0
March 11, 2004
12
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