EL5308IUZ-T13 [INTERSIL]
450MHz Fixed Gain Amplifiers with Enable; 450MHz的固定增益放大器，使
| 型号： | EL5308IUZ-T13 |
| 厂家： | 
Intersil |
| 描述： | 450MHz Fixed Gain Amplifiers with Enable |
| 文件： | 总13页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5108, EL5308
®
Data Sheet
June 15, 2006
FN7358.5
450MHz Fixed Gain Amplifiers with Enable
Features
The EL5108 and EL5308 are fixed gain amplifiers with a
bandwidth of 450MHz. This makes these amplifiers ideal for
today’s high speed video and monitor applications. They
feature internal gain-setting resistors and can be configured
in a gain of +1, -1 or +2. The same bandwidth is seen in both
gain-of-1 and gain-of-2 applications.
• Pb-free plus anneal available (RoHS compliant)
• Gain selectable (+1, -1, +2)
• 450MHz -3dB BW (A = -1, +1, +2)
V
• 3.5mA supply current per amplifier
• Single and dual supply operation, from 5V to 12V
• Available in SOT-23 packages
The EL5108 and EL5308 also incorporate an enable and
disable function to reduce the supply current to 25µA typical
per amplifier. Allowing the CE pin to float or applying a low
logic level will enable the amplifier.
• 350MHz, 1.5mA product available (EL5106 & EL5306)
Applications
The EL5108 is offered in the 6 Ld SOT-23 and the industry-
standard 8 Ld SO packages and the EL5308 is available in
the 16 Ld SO and 16 Ld QSOP packages. All operate over
the industrial temperature range of -40°C to +85°C.
• Battery powered equipment
• Handheld, portable devices
• Video amplifiers
• Cable drivers
• RGB amplifiers
Ordering Information
PART NUMBER
PART MARKING
PACKAGE
6 Ld SOT-23
TAPE & REEL
PKG. DWG. #
MDP0038
EL5108IW-T7
r
r
7” (3K pcs)
EL5108IW-T7A
EL5108IS
6 Ld SOT-23
8 Ld SO
7” (250 pcs)
MDP0038
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0040
MDP0040
MDP0040
MDP0040
MDP0040
MDP0040
5108IS
5108IS
5108IS
5108ISZ
-
7”
13”
-
EL5108IS-T7
8 Ld SO
EL5108IS-T13
EL5108ISZ (See Note)
8 Ld SO
8 Ld SO
EL5108ISZ-T7 (See Note) 5108ISZ
EL5108ISZ-T13 (See Note) 5108ISZ
8 Ld SO
7”
13”
-
8 Ld SO
EL5308IS
EL5308IS
EL5308IS
EL5308IS
5308IU
16 Ld SO (0.150”)
16 Ld SO (0.150”)
16 Ld SO (0.150”)
16 Ld QSOP
16 Ld QSOP
16 Ld QSOP
16 Ld QSOP (Pb-free)
16 Ld QSOP (Pb-free)
16 Ld QSOP (Pb-free)
EL5308IS-T7
EL5308IS-T13
EL5308IU
7”
13”
-
EL5308IU-T7
EL5308IU-T13
EL5308IUZ (See Note)
5308IU
7”
13”
-
5308IU
5308IUZ
EL5308IUZ-T7 (See Note) 5308IUZ
EL5308IUZ-T13 (See Note) 5308IUZ
7”
13”
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL5108, EL5308
Pinout
EL5108
(8 LD SO)
TOP VIEW
EL5308
(16 LD SO, QSOP)
TOP VIEW
NC
IN-
1
2
3
4
8
7
6
5
CE
INA+
CEA
VS-
1
2
3
4
5
6
7
8
16 INA-
-
+
VS+
OUT
NC
-
+
15 OUTA
14 VS+
IN+
VS-
+
-
CEB
INB+
NC
13 OUTB
12 INB-
11 NC
EL5108
(6 LD SOT-23)
TOP VIEW
+
-
CEC
INC+
10 OUTC
VS+
CE
OUT
VS-
IN+
1
2
3
6
5
4
9
INC-
+
-
IN-
FN7358.5
June 15, 2006
2
EL5108, EL5308
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . 13.2V
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . V - -0.5V to V + +0.5V
S S
S
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Slewrate from V + to V - . . . . . . . . . . . . . . . . . . . . 1V/µs
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
S
S
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, R = 150Ω, T = 25°C unless otherwise specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
A
= +1
= -1
440
445
450
40
MHz
MHz
MHz
MHz
V/µs
ns
V
A
V
A
= +2
= +2
V
BW1
SR
0.1dB Bandwidth
A
V
Slew Rate
V
V
= -2.5V to +2.5V, A = +2
3500
4500
10
O
V
t
0.1% Settling Time
Input Voltage Noise
Input Current Noise
= -2.5V to +2.5V, A = +2
OUT V
S
e
2
nV/√Hz
pA/√Hz
%
N
i
f = 2kHz
12
N
dG
dP
Differential Gain Error (Note 1)
Differential Phase Error (Note 1)
A
= +2
= +2
0.01
0.01
V
A
°
V
DC PERFORMANCE
V
Offset Voltage
-8
+3
5
+8
mV
OS
T V
Input Offset Voltage Temperature
Coefficient
Measured from T
MIN
to T
MAX
µV/°C
C
OS
A
Gain Error
V
= -3V to +3V, R = 150Ω
0.7
2.5
%
E
O
L
R , R
Internal R and R
G
325
Ω
F
G
F
INPUT CHARACTERISTICS
CMIR
Common Mode Input Range
+ Input Current
±3
±3.3
2
V
+I
8
µA
MΩ
pF
IN
IN
IN
R
C
Input Resistance
at I +
0.7
1
N
Input Capacitance
OUTPUT CHARACTERISTICS
V
Output Voltage Swing
R = 150Ω to GND
±3.6
±3.8
100
±3.8
±4.0
135
V
V
O
L
R = 1kΩ to GND
L
I
Output Current
R = 10Ω to GND
mA
OUT
L
SUPPLY
I
I
Supply Current - Enabled (per amplifier) No load, V = 0V
IN
3.18
3.7
9
4.35
25
mA
µA
dB
SON
Supply Current - Disabled (per amplifier) No load, V = 0V
IN
SOFF
PSRR
Power Supply Rejection Ratio
DC, V = ±4.75V to ±5.25V
75
S
FN7358.5
June 15, 2006
3
EL5108, EL5308
Electrical Specifications V + = +5V, V - = -5V, R = 150Ω, T = 25°C unless otherwise specified. (Continued)
S
S
L
A
PARAMETER
ENABLE
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
t
t
I
I
Enable Time
280
560
5
ns
ns
µA
µA
V
EN
Disable Time (Note 2)
DIS
CE Pin Input High Current
CE Pin Input Low Current
CE = V +
-1
25
-1
IHCE
ILCE
S
CE = V -
+1
S
V
V
CE Input High Voltage for Power-down
CE Input Low Voltage for Enable
V + -1
S
IHCE
ILCE
V + -3
V
S
NOTES:
1. Standard NTSC test, AC signal amplitude = 286mV , f = 3.58MHz
P-P
2. Measured from the application of the CE logic signal until the output voltage is at the 50% point between initial and final values
Pin Descriptions
EL5308
EL5108
(SO8)
EL5108
(SOT23-6)
(SO16,
QSOP16)
PIN NAME
NC
FUNCTION
Not connected
EQUIVALENT CIRCUIT
1, 5
2
6, 11
4
9, 12, 16
IN-
Inverting input
R
G
IN+
IN-
R
F
CIRCUIT 1
3
4
6
3
2
1
1, 5, 8
3
IN+
VS-
Non-inverting input
Negative supply
Output
(Reference Circuit 1)
10, 13, 15
OUT
OUT
R
F
CIRCUIT 2
7
8
6
5
14
VS+
CE
Positive supply
Chip enable
2, 4, 7
V +
S
CE
V -
S
CIRCUIT 3
FN7358.5
June 15, 2006
4
EL5108, EL5308
Typical Performance Curves
5
135
45
V =±5V
V =±5V
S
S
V
=200mV
V
=200V
P-P
IN
P-P
IN
R =150Ω
R =150Ω
L
L
3
1
A
= -1
A
= -1
V
V
-45
A
= 2
V
-1
-3
-5
-135
-225
-315
A
= 1
V
A
= 2
V
A
= 1
V
100K
1M
10M
FREQUENCY (Hz)
1G
100K
1M
10M
1G
1G
1G
100M
100M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE
FIGURE 2. PHASE RESPONSE
11
9
11
9
V =±5V
S
V =±5V
S
A =2
V
A =2
V
R
= 500Ω
L
R =150Ω
L
R
= 150Ω
L
V
= 400mV
OP-P
7
5
3
1
7
5
3
1
V
= 2V
R
= 100Ω
OP-P
L
R
= 50Ω
L
100K
1M
10M
FREQUENCY (Hz)
1G
100K
1M
10M
FREQUENCY (Hz)
100M
100M
FIGURE 3. FREQUENCY RESPONSE vs OUTPUT VOLTAGE
FIGURE 4. FREQUENCY RESPONSE vs R
L
11
1.2
1
V =±5V
V =±5V
S
A = -1
V
S
C
C
= 6.8pF
= 4.7pF
L
A =2
R =150Ω
V
L
R =150Ω
A = 1
V
L
9
7
5
3
1
L
0.8
0.6
0.4
A
= 2
V
C
= 2.2pF
L
C
= 0pF
L
0.2
0
100K
1M
10M
FREQUENCY (Hz)
1G
100M
100K
1M
10M
FREQUENCY (Hz)
100M
FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS C
FIGURE 6. GROUP DELAY vs FREQUENCY
L
FN7358.5
June 15, 2006
5
EL5108, EL5308
Typical Performance Curves (Continued)
100
15
A =2
V
R =150Ω
L
10
1
-5
-25
-45
-65
-85
0.1
0.01
0.002
10K
100K
1M
100M
10M
100K
1M
10M
1G
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. INPUT TO OUTPUT ISOLATION vs FREQUENCY
(FOR DISABLE MODE)
FIGURE 8. OUTPUT IMPEDENCE vs FREQUENCY
0
1K
V =±5V
S
A =2
V
-10
-20
-30
-40
-50
-60
-70
-80
100
I
N
10
1
V
N
1K
10K
100K
1M
10M
100M
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 10. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
1.4
480
R
= 150Ω
L
R
= 150Ω
L
460
440
420
400
380
360
340
A = 2
V
1.2
1
A
= -1
= 2
= 1
V
A
= -1
V
0.8
0.6
0.4
0.2
A
A
V
V
A
= 1
V
320
300
4.5
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11
5
5.5
6
6.5
7
7.5
8
8.5 9 9.5 10 10.5 11
V
(V)
S
V
(V)
S
FIGURE 11. BANDWIDTH vs SUPPLY VOLTAGE
FIGURE 12. PEAKING vs SUPPLY VOLTAGE
FN7358.5
June 15, 2006
6
EL5108, EL5308
Typical Performance Curves (Continued)
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
-40
V =±5V
S
A =2
V
HD2
HD3
R =150Ω
L
O
-50
-60
-70
-80
-90
V
=2V
P-P
I +, I -
S
S
4.5
5
5.5
6
6.5
7
7.5
8
8.5 9 9.5 10 10.5 11
0
10
20
30
40
50
60
V
(V)
S
FREQUENCY (MHz)
FIGURE 13. DISTORTION vs FREQUENCY
FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE
V
=±2V
V
=±200mV
O
O
1V/DIV
100mV/DIV
10ns/DIV
10ns/DIV
FIGURE 15. LARGE SIGNAL RESPONSE
FIGURE 16. SMALL SIGNAL RESPONSE
M=100ns
M=100ns
CH1 2.00V/DIV
CH1 2.00V/DIV
CH2 1.00V/DIV
CH2 1.00V/DIV
FIGURE 17. DISABLED RESPONSE
FIGURE 18. ENABLED RESPONSE
FN7358.5
June 15, 2006
7
EL5108, EL5308
Typical Performance Curves (Continued)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
1.4
1.2
1
909mW
1.250W
0.9
SO16 (0.150”)
SO16 (0.150”)
θ
=110°C/W
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
JA
θ
=80°C/W
JA
625mW
633mW
909mW
893mW
SO8
SO8
0.8
0.6
0.4
θ
θ
=160°C/W
θ
θ
=110°C/W
JA
JA
435mW
391mW
SOT23-6
=256°C/W
QSOP16
=158°C/W
JA
SOT23-6
QSOP16
=112°C/W
θ
JA
θ
=230°C/W
0.2
0.1
0
JA
JA
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Disable/Power-Down
Applications Information
The EL5108 and EL5308 amplifiers can be disabled and
placing their outputs in a high impedance state. When
disabled, the amplifier supply current is reduced to <25µA.
The EL5108 and EL5308 are disabled when the CE pin is
pulled up to within 1V of the positive supply. Similarly, the
amplifier is enabled by floating or pulling its CE pin to at least
3V below the positive supply. For ±5V supply, this means
that the amplifier will be enabled when CE is 2V or less, and
disabled when CE is above 4V. Although the logic levels are
not standard TTL, this choice of logic voltages allow the
EL5108 and EL5308 to be enabled by tying CE to ground,
even in 5V single supply applications. The CE pins can be
driven from CMOS outputs.
Product Description
The EL5108 and EL5308 are fixed gain amplifiers that offer
a wide -3dB bandwidth of 450MHz and a low supply current
of 3.5mA per amplifier. They work with supply voltages
ranging from a single 5V to 10V and they are also capable of
swinging to within 1.2V of either supply on the output. These
combinations of high bandwidth, low power, and high slew
rate make the EL5108 and EL5308 the ideal choice for many
low-power/high-bandwidth applications such as portable,
handheld, or battery-powered equipment.
For varying bandwidth and higher gains, consider the
EL5166 with 1GHz on a 9mA supply current or the EL5164
with 600MHz on a 3.5mA supply current. Versions include
single, dual, and triple amp packages with 6 Ld SOT-23,
16 Ld QSOP, and 8 Ld or 16 Ld SO outlines.
Gain Setting
The EL5108 and EL5308 are built with internal feedback and
gain resistors. The internal feedback resistors have equal
value; as a result, the amplifier can be configured into gain of
+1, -1, and +2 without any external resistors. Figure 21
shows the amplifier in gain of +2 configuration. The gain
error is ±2% maximum. Figure 22 shows the amplifier in gain
of -1 configuration. For gain of +1, IN+ and IN- should be
connected together as shown in Figure 23. This
configuration avoids the effects of any parasitic capacitance
on the IN- pin. Since the internal feedback and gain resistors
change with temperature and process, external resistor
should not be used to adjust the gain settings.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Low
impedance ground plane construction is essential. Surface
mount components are recommended, but if leaded
components are used, lead lengths should be as short as
possible. The power supply pins must be well bypassed to
reduce the risk of oscillation. The combination of a 4.7µF
tantalum capacitor in parallel with a 0.01µF capacitor has
been shown to work well when placed at each supply pin.
325Ω
325Ω
IN-
-
IN+
+
FIGURE 21. A = +2
V
FN7358.5
June 15, 2006
8
EL5108, EL5308
Video Performance
325Ω
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency response as DC levels are changed at the output.
This is especially difficult when driving a standard video load
of 150Ω, because of the change in output current with DC
level. Previously, good differential gain could only be
achieved by running high idle currents through the output
transistors (to reduce variations in output impedance).
Special circuitry has been incorporated in the EL5108 and
EL5308 to reduce the variation of output impedance with
current output. This results in dG and dP specifications of
0.01% and 0.01°, while driving 150Ω at a gain of 2.
325Ω
IN-
-
GND
+
FIGURE 22. A = -1
V
325Ω
IN- 325Ω
-
+
IN+
FIGURE 23. A = +1
V
Output Drive Capability
In spite of its low 3.5mA of supply current per amplifier, the
EL5108 and EL5308 are capable of providing a maximum of
±130mA of output current.
Supply Voltage Range and Single-Supply
Operation
The EL5108 and EL5308 have been designed to operate
with supply voltages having a span of greater than or equal
to 5V and less than 12V. In practical terms, this means that
they will operate on dual supplies ranging from ±2.5V to
±5V. With single-supply, they will operate from 5V to 10V.
Driving Cables and Capacitive Loads
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, the back-termination series resistor will
decouple the EL5108 and EL5308 from the cable and allow
extensive capacitive drive. However, other applications may
have high capacitive loads without a back-termination
resistor. In these applications, a small series resistor (usually
between 5Ω and 50Ω) can be placed in series with the
output to eliminate most peaking.
As supply voltages continue to decrease, it becomes
necessary to provide input and output voltage ranges that
can get as close as possible to the supply voltages. The
EL5108 and EL5308 have an input range which extends to
within 2V of either supply. So, for example, on ±5V supplies,
the input range is about ±3V. The output range is also quite
large, extending to within 1V of the supply rail. On a ±5V
supply, the output is therefore capable of swinging from -4V
to +4V. Single-supply output range is larger because of the
increased negative swing due to the external pull-down
resistor to ground. Figure 24 shows an AC-coupled, gain of
+2, +5V single supply circuit configuration.
Current Limiting
The EL5108 and EL5308 have no internal current-limiting
circuitry. If the output is shorted, it is possible to exceed the
Absolute Maximum Rating for output current or power
dissipation, potentially resulting in the destruction of the
device.
Power Dissipation
325Ω
With the high output drive capability of the EL5108 and
EL5308, it is possible to exceed the 125°C Absolute
Maximum junction temperature under certain very high load
+5
current conditions. Generally speaking when R falls below
L
about 25Ω, it is important to calculate the maximum junction
4.7µF
temperature (T
) for the application to determine if
325Ω
JMAX
-
power supply voltages, load conditions, or package type
need to be modified for the EL5108 and EL5308 to remain in
the safe operating area. These parameters are calculated as
follows:
V
OUT
+5
+
0.1µF
1K
1K
0.1µF
V
IN
T
= T
+ (θ × n × PD
)
MAX
JMAX
MAX
JA
FIGURE 24.
FN7358.5
June 15, 2006
9
EL5108, EL5308
where:
T
= Maximum ambient temperature
MAX
θ
= Thermal resistance of the package
JA
n = Number of amplifiers in the package
PD = Maximum power dissipation of each amplifier in
MAX
the package
PD
for each amplifier can be calculated as follows:
MAX
V
OUTMAX
R
L
----------------------------
PD
= (2 × V × I
) + (V - V ) ×
OUTMAX
MAX
S
SMAX
S
where:
V
= Supply voltage
S
I
= Maximum supply current of 1A
SMAX
V
= Maximum output voltage (required)
OUTMAX
R = Load resistance
L
FN7358.5
June 15, 2006
10
EL5108, EL5308
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7358.5
June 15, 2006
11
EL5108, EL5308
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
SYMBOL
SOT23-5
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
5
SOT23-6
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
6
TOLERANCE
MAX
6
4
N
A
A1
A2
b
±0.05
±0.15
E1
E
±0.05
2
3
c
±0.06
0.15
2X
C
D
D
Basic
1
2
3
0.20
2X
C
E
Basic
5
e
E1
e
Basic
Basic
0.20
C
A-B
D
M
B
b
NX
e1
L
Basic
±0.10
L1
N
Reference
Reference
Rev. E 3/00
0.15
2X
C
A-B
1
3
NOTES:
D
1. Plastic or metal protrusions of 0.25mm maximum per side are
not included.
C
A2
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
SEATING
PLANE
3. This dimension is measured at Datum Plane “H”.
A1
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.10
NX
C
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
6. SOT23-5 version has no center lead (shown as a dashed line).
(L1)
H
A
GAUGE
PLANE
0.25
c
+3°
-0°
L
0°
FN7358.5
June 15, 2006
12
EL5108, EL5308
Quarter Size Outline Plastic Packages Family (QSOP)
A
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
A
A1
A2
b
0.068
0.006
0.056
0.010
0.008
0.193
0.236
0.154
0.025
0.025
0.041
16
0.068
0.006
0.056
0.010
0.008
0.341
0.236
0.154
0.025
0.025
0.041
24
0.068
0.006
0.056
0.010
0.008
0.390
0.236
0.154
0.025
0.025
0.041
28
Max.
±0.002
±0.004
±0.002
±0.001
±0.004
±0.008
±0.004
Basic
-
-
PIN #1
I.D. MARK
E
E1
-
-
c
-
1
(N/2)
D
1, 3
B
E
-
0.010 C A B
E1
e
2, 3
e
-
H
L
±0.009
Basic
-
C
SEATING
L1
N
-
PLANE
Reference
-
0.007 C A B
b
0.004 C
Rev. E 3/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
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FN7358.5
June 15, 2006
13
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