EL7182_06 [INTERSIL]
2-Phase, High Speed CCD Driver; 2相，高速CCD驱动器
| 型号： | EL7182_06 |
| 厂家： | 
Intersil |
| 描述： | 2-Phase, High Speed CCD Driver |
| 文件： | 总7页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL7182
®
Data Sheet
June 15, 2006
FN7281.1
2-Phase, High Speed CCD Driver
Features
The EL7182 is extremely well suited for driving CCD's,
especially where high contrast imaging is desirable. The 16V
supply rating is attractive for higher voltage CCD
applications, as in color fax machines. The input is TTL and
3V compatible. The low quiescent current requirement is
advantageous in portable/battery powered systems. The
EL7182 is available in 8 Ld PDIP and 8 Ld SOIC packages.
• 3V and 5V Input compatible
• Clocking speeds up to 10MHz
• Reduced clock skew
• 20ns Switching/delay time
• 2A Peak drive
• Low quiescent current
Pinout
• Wide operating voltage: 4.5V–16V
EL7182
(8 LD PDIP, SOIC)
TOP VIEW
• Pb-free plus anneal available (RoHS compliant)
Applications
• CCD Drivers requiring high-contrast imaging
• Differential line drivers
• Push-pull circuits
Ordering Information
Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047
PART
TEMP.
PKG.
PART NUMBER MARKING RANGE (°C) PACKAGE DWG. #
EL7182CN
EL7182CS
EL7182CN -40 to +85 8 Ld PDIP MDP0031
7182CS
-40 to +85 8 Ld SOIC MDP0027
EL7182CSZ
(Note)
7182CSZ
-40 to +85 8 Ld SOIC MDP0027
(Pb-free)
EL7182CSZ-T7 7182CSZ 8 Ld SOIC (7” Tape and Reel)
(Note) (Pb-free)
EL7182CSZ-T13 7182CSZ 8 Ld SOIC (7” Tape and Reel)
(Note) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL7182
Absolute Maximum Ratings (T = 25°C)
A
Supply (V+ to Gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V
Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+
Combined Peak Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . .4A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications
PARAMETER
T = 25°C, V = 15V unless otherwise specified
A
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT
V
Logic “1” Input Voltage
2.4
V
µA
V
IH
I
Logic “1” Input Current
Logic “0” Input Voltage
Logic “0” Input Current
Input Hysteresis
@V+
@0V
0.1
10
0.8
10
IH
V
IL
I
0.1
0.3
µA
V
IL
V
HVS
OUTPUT
R
Pull-Up Resistance
Pull-Down Resistance
Peak Output Current
I
I
= -100mA
= +100mA
3
4
2
2
6
6
Ω
Ω
OH
OL
OUT
R
OUT
I
I
Source
A
PK
Sink
A
Continuous Output Current
Source/Sink
100
4.5
mA
DC
POWER SUPPLY
I
Power Supply Current
Operating Voltage
Input High
2.5
5
mA
V
S
V
16
S
AC Electrical Specifications
T = 25°C, V = 15V unless otherwise specified
A
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS
t
t
Rise Time
Fall Time
C = 500pF
7.5
10
10
13
18
20
ns
ns
ns
ns
ns
ns
R
F
L
C = 1000pF
20
L
C = 500pF
L
C = 1000pF
20
25
25
L
t
t
Turn-On Delay Time
Turn-Off Delay Time
D-ON
D-OFF
FN7281.1
June 15, 2006
2
EL7182
Timing Table
Standard Test Configuration
Simplified Schematic
FN7281.1
June 15, 2006
3
EL7182
Typical Performance Curves
Switch Threshold vs
Supply Voltage
Max Power/Derating Curves
Input Current vs Voltage
Peak Drive vs Supply Voltage
Quiescent Supply Current
“ON” Resistance vs Supply Voltage
CASE:
Input Level
GND
Curve
B
D
V+
Average Supply Current vs
Voltage and Frequency
Average Supply Current
vs Capacitive Load
FN7281.1
June 15, 2006
4
EL7182
Typical Performance Curves (Continued)
Rise/Fall Time vs Load
Rise/Fall Time vs Supply Voltage
Rise/Fall Time vs Temperature
Propagation Delay vs Supply Voltage
Delay Time vs Temperature
FN7281.1
June 15, 2006
5
EL7182
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7281.1
June 15, 2006
6
EL7182
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7281.1
June 15, 2006
7
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