概述
数据手册
替代型号EL7563CREZ-T7 概述
Monolithic 4 Amp DC:DC Step-Down Regulator 单片4安培直流： DC降压稳压器 DC/DC转换器
EL7563CREZ-T7 数据手册
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PDF下载EL7563
®
ta Sheet
May 13, 2005
FN7296.2
Monolithic 4 Amp DC/DC Step-Down
Regulator
Features
• Integrated synchronous MOSFETs and current mode
controller
The EL7563 is an integrated, full-featured synchronous step-
down regulator with output voltage adjustable from 1.0V to
2.5V. It is capable of delivering 4A continuous current at up
to 95% efficiency. The EL7563 operates at a constant
frequency pulse width modulation (PWM) mode, making
external synchronization possible. Patented on-chip
resistorless current sensing enables current mode control,
which provides cycle-by-cycle current limiting, over-current
protection, and excellent step load response. The EL7563
features power tracking, which makes the start-up
sequencing of multiple converters possible. A junction
temperature indicator conveniently monitors the silicon die
temperature, saving the designer time on the tedious
thermal characterization. The minimal external components
and full functionality make this EL7563 ideal for desktop and
portable applications.
• 4A continuous output current
• Up to 95% efficiency
• Internal patented current sense
• Cycle-by-cycle current limit
• 3V to 3.6V input voltage
• Adjustable output voltage 1V to 2.5V
• Precision reference
• ±0.5% load and line regulation
• Adjustable switching frequency to 1MHz
• Oscillator synchronization possible
• Internal soft-start
The EL7563 is offered in 20-pin SO and 28-pin HTSSOP
packages.
• Over-voltage protection
• Junction temperature indicator
• Over-temperature protection
• Under-voltage lockout
Pinout
EL7563
(20-PIN SO)
TOP VIEW
• Multiple supply start-up tracking
• Power-good indicator
C5
• 20-pin SO (0.300”) package
• 28-pin HTSSOP package
• Pb-Free available (RoHS compliant)
1
EN 20
FB 19
VREF
0.1µF
C4
2 SGND
3 COSC
4 VDD
5 VTJ
PG 18
D2
D4
C8
390pF
C2
R4
VDRV 17
VHI 16
Applications
• DSP, CPU core, and I/O supplies
C3
22Ω
0.22µF
D3
0.22µF
D1
2.2nF
C6
C9
6 PGND
7 PGND
8 VIN
LX 15
0.22µF
0.1µF
• Logic/Bus supplies
C1
V
OUT
2.5V
4A
LX 14
L1
V
330µF
IN
3.3V
• Portable equipment
C10
2.2nF
4.7µH
PGND 13
PGND 12
PGND 11
R2
• DC/DC converter modules
• GTL + Bus power supply
1.58kΩ
R1
9 STP
C7
330µF
1kΩ
10 STN
Typical Application Diagrams continued on page 3
Manufactured Under U.S. Patent No. 5,7323,974
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL7563
Ordering Information
TAPE &
REEL
PART NUMBER
PACKAGE
PKG. DWG. #
MDP0027
EL7563CM
20-Pin SO (0.300”)
-
-
EL7563CMZ
(See Note)
20-Pin SO (0.300”)
(Pb-free)
MDP0027
EL7563CMZ-T13 20-Pin SO (0.300”)
13”
MDP0027
(See Note)
(Pb-free)
EL7563CRE
28-Pin HTSSOP
28-Pin HTSSOP
28-Pin HTSSOP
-
7”
13”
-
MDP0048
MDP0048
MDP0048
MDP0048
EL7563CRE-T7
EL7563CRE-T13
EL7563CREZ
(See Note)
28-Pin HTSSOP
(Pb-free)
EL7563CREZ-T7
(See Note)
28-Pin HTSSOP
(Pb-free)
7”
MDP0048
MDP0048
EL7563CREZ-T13 28-Pin HTSSOP
(See Note) (Pb-free)
13”
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN7296.2
2
May 13, 2005
EL7563
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V or V
and GND . . . . . . . . . . . . +4.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
IN
DD
V
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V +0.3V
LX
IN
DD
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, V
+0.3V
V
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, V +6V
LX
HI
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
DC Electrical Specifications
V
= V = 3.3V, T = T = 25°C, C
= 390pF, unless otherwise specified.
DD
DESCRIPTION
Reference Accuracy
IN
A
J
OSC
CONDITIONS
PARAMETER
MIN
TYP
1.26
50
MAX
UNIT
V
V
V
V
V
1.24
1.28
REF
Reference Temperature Coefficient
Reference Load Regulation
Oscillator Ramp Amplitude
Oscillator Charge Current
ppm/°C
%
REFTC
0 < I
< 50µA
REF
-1
REFLOAD
RAMP
1.15
200
8
V
I
I
I
I
0.1V < V
0.1V < V
< 1.25V
< 1.25V
µA
mA
mA
mA
V
OSC_CHG
OSC_DIS
OSC
OSC
Oscillator Discharge Current
+V
V
V
V
V
+V
Supply Current
Standby Current
V
= 2.7V, F
OSC
= 120kHz
2
5.5
1
6.5
1.5
VDD DRV
DD DRV
EN
EN = 0
VDD_OFF
DD
DD
DD
V
V
for Shutdown
for Startup
2.4
2.6
2.65
2.95
DD_OFF
DD_ON
OT
V
T
T
Over Temperature Threshold
Over Temperature Hysteresis
Internal FET Leakage Current
135
20
°C
°C
HYS
I
EN = 0, L = 3.3V (low FET), L = 0V
10
60
µA
LEAK
X
X
(high FET)
I
Peak Current Limit
FET On Resistance
5
A
mΩ
LMAX
R
R
Wafer level test only
30
0.2
2.5
DSON
R
Tempco
mΩ/°C
µA
DSONTC
DSON
I
Auxiliary Supply Tracking Positive Input
Pull Down Current
V
V
= V /2
IN
-4
STP
STP
STN
I
Auxiliary Supply Tracking Negative Input
Pull Up Current
= V /2
IN
2.5
4
µA
STN
V
V
V
V
V
V
V
V
V
Positive Power Good Threshold
Negative Power Good Threshold
Power Good Drive High
Power Good Drive Low
Over Voltage Protection
Output Initial Accuracy
With respect to target output voltage
With respect to target output voltage
6
16
-6
%
%
V
PGP
-16
2.7
PGN
I
I
= 1mA
PG_HI
PG_LO
OVP
PG
= -1mA
0.5
V
PG
10
0.992
0.5
%
V
I
= 0A
0.977
1.007
FB
LOAD
Output Line Regulation
Output Load Regulation
Output Temperature Stability
Feedback Input Pull Up Current
EN Input High Level
V
= 3.3V, ∆V = 10%, I
IN IN LOAD
= 0A
%
%
%
nA
V
FB_LINE
FB_LOAD
FB_TC
0.5A < I
< 4A
0.5
LOAD
-40°C < T < 85°C, I
= 2A
LOAD
±1
A
I
V
V
= 0V
100
200
2.7
FB
FB
EN
V
V
EN_HI
EN Input Low Level
1
V
EN_LO
I
Enable Pull Up Current
= 0
-4
-2.5
µA
EN
FN7296.2
3
May 13, 2005
EL7563
Closed-Loop AC Electrical Specifications
V
= V = 3.3V, T = T = 25°C, C
= 390pF, unless otherwise specified.
S
IN
A
J
OSC
PARAMETER
DESCRIPTION
Oscillator Initial Accuracy
Minimum Oscillator Sync Width
Soft Start Slope
CONDITIONS
MIN
TYP
365
25
MAX
UNIT
kHz
ns
F
310
420
OSC
t
SYNC
M
0.5
15
V/ms
ns
SS
BRM
LEB
t
t
FET Break Before Make Delay
High Side FET Minimum On Time
Maximum Duty Cycle
150
95
ns
D
%
MAX
Typical Application Diagrams (Continued)
C5
1
2
3
4
5
6
7
8
9
EN 28
VREF
SGND
COSC
VDD
0.1µF
C4
FB 27
PG 26
D2
D4
390pF
C2
R4
VDRV 25
VHI 24
LX 23
C3
0.22µF
C8
0.22µF
22Ω
D3
VTJ
D1
2.2nF
C6
C9
0.1µF
PGND
PGND
PGND
PGND
0.22µF
C1
330µF
V
OUT
2.5V
4A
LX 22
L1
V
IN
3.3V
C10
4.7µH
LX 21
2.2nF
R2
1.58kΩ
R1
LX 20
C7
330µF
1kΩ
10 VIN
11 VIN
12 NC
LX 19
LX 18
NC 17
13 STP
14 STN
PGND 16
PGND 15
28-PIN HTSSOP
FN7296.2
4
May 13, 2005
EL7563
Pin Descriptions
20-PIN SO
(0.300”)
28-PIN
HTSSOP
PIN NAME
VREF
SGND
COSC
VDD
PIN FUNCTION
1
2
1
Bandgap reference bypass capacitor; typically 0.1µF to SGND
Control circuit negative supply or signal ground
2
3
3
Oscillator timing capacitor (see performance curves)
4
4
5
Control circuit positive supply; normally connected to VIN through an RC filter
Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND
5
VTJ
6, 7
6, 7, 8, 9
PGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
8
9
10, 11
13
VIN
Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
STP
Auxiliary supply tracking positive input; tied to regulator output to synchronize start up with a
second supply; leave open for stand alone operation; 2µA internal pull down current
10
11, 12, 13
14, 15
16
14
STN
PGND
LX
Auxiliary supply tracking negative input; connect to output of a second supply to synchronize
start up; leave open for stand alone operation; 2µA internal pull up current
15, 16
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
18, 19, 20, 21,
22, 23
Inductor drive pin; high current output whose average voltage equals the regulator output
voltage
24
VHI
Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF
capacitor
17
18
25
26
VDRV
PG
Positive supply of low-side driver and input voltage for high side boot strap
Power good window comparator output; logic 1 when regulator output is within ±10% of target
output voltage
19
20
27
28
FB
EN
Voltage feedback input; connected to external resistor divider between VOUT and SGND; a
125nA pull-up current forces VOUT to SGND in the event that FB is floating
Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open;
a capacitor can be added at this pin to delay the start of converter
Typical Performance Curves (20 Pin SO Package)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
V
=3.3V
V =3.3V
IN
IN
100
95
90
85
80
75
70
100
95
90
85
80
75
70
65
60
V
=2.5V
O
V
=2.5V
O
V
=1.8V
O
V
=1.8V
O
V
=1.2V
O
V
=1.2V
O
V
=1V
O
0
0.5
1
1.5
2
2.5
3
3.5
4
0.1 0.6 1.1 1.6 2.1 2.6 3.1 3.6
(A)
4
LOAD CURRENT I (A)
I
O
O
FIGURE 1. EL7563CM EFFICIENCY vs I
FIGURE 2. EL7563CRE EFFICIENCY
O
FN7296.2
May 13, 2005
5
EL7563
Typical Performance Curves (20 Pin SO Package) (Continued)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
V
=3.3V
IN
1.8
1.6
1.4
1.2
1
1.6
1.4
1.2
1
V
=1.8V
O
V
=1.2V
V
=2.5V
V
O
O
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
V
=1V
O
=1.2V
O
V
=2.5V
3
O
0
0.5
1
1.5
2
2.5
3.5
4
0
1
2
3
4
OUTPUT CURRENT I (A)
I (A)
O
O
FIGURE 3. EL7563CM CONVERTER POWER LOSS vs I
FIGURE 4. EL7563CRE TOTAL CONVERTER POWER LOSS
O
V
=2.5V
V =2.5V
O
O
2.505
2.5
0.6
0.4
0.2
0
V
=3.6V
IN
V
=3.3V
IN
2.495
2.49
V
=3.3V
IN
V
=3.6V
IN
2.485
2.48
-0.2
-0.4
-0.6
-0.8
V
=3V
3
IN
V
=3V
1.5
IN
2.475
2.47
2.465
0.5
1
1.5
2
2.5
3.5
4
0
0.5
1
2
2.5
3
3.5
4
LOAD CURRENT I (A)
I (A)
O
O
FIGURE 5. EL7563CM LOAD REGULATION
FIGURE 6. EL7563CRE LOAD REGULATION
CONDITION:
EL7563CRE THERMAL PAD SOLDERED TO 2-LAYER
PCB WITH 0.039” THICKNESS AND 1 OZ. COPPER ON
BOTH SIDES
TEST CONDITION:
CHIP IN THE CENTER OF COPPER AREA
50
50
45
40
35
30
25
46
WITH NO AIRFLOW
42
38
WITH 100 LFPM AIRFLOW
34
1 OZ. COPPER PCB USED
30
1
1.5
2
2.5
3
3.5
4
0
1.5
2
2.5
3
3.5
4
2
2
PCB COPPER HEAT-SINKING AREA (in )
PCB AREA (in )
FIGURE 7. EL7563CM θ vs COPPER AREA
FIGURE 8. EL7563CRE THERMAL RESISTANCE vs PCB
AREA - NO AIR FLOW
JA
FN7296.2
May 13, 2005
6
EL7563
Typical Performance Curves (20 Pin SO Package) (Continued)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
60
50
40
30
20
10
0
45
40
35
30
25
20
15
10
5
NO AIRFLOW
100 LFM
200 LFM
500 LPF
3
0
0
1
2
4
1
1.5
2
2.5
(A)
3
3.5
4
I
(A)
I
O
O
FIGURE 9. EL7563CM JUNCTION TEMPERATURE RISE ON
DEMO BOARD
FIGURE 10. EL7563CRE JUNCTION TEMPERATURE RISE
ON DEMO BOARD - NO AIR FLOW
1000
900
800
700
600
500
400
300
200
360
350
340
I
I
=4A
=0A
O
330
320
310
300
290
280
O
100
100 200 300 400 500 600 700 800 900 1000
-40
-20
0
20
40
60
80
C
(pF)
TEMPERATURE (°C)
OSC
FIGURE 12. SWITCHING FREQUENCY vs C
FIGURE 11. SWITCHING FREQUENCY vs TEMPERATURE
OSC
8
7
1.5
1.3
1.1
0.9
V
=3.3V
V
=3.6V
IN
IN
6
5
4
3
V
=3V
IN
-40
-20
0
20
40
(°C)
60
80
100 120
0
25
50
75
100
125
150
T
JUNCTION TEMPERATURE (°C)
J
FIGURE 13. CURRENT LIMIT vs T
FIGURE 14. VTJ vs JUNCTION TEMPERATURE
J
FN7296.2
May 13, 2005
7
EL7563
Typical Performance Curves (20 Pin SO Package) (Continued)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
V
=3.3V, V =1.8V, I =0.2A-4A
IN
O
O
V
=3.3V, V =1.8V, I =4A
IN
O
O
∆VIN
V
LX
I
O
O
i
L
∆V
∆V
O
FIGURE 15. SWITCHING WAVEFORMS
FIGURE 16. TRANSIENT RESPONSE
V
=3.3V, V =1.8V, I =0.2A
IN
V
=3.3V, V =1.8V, I =4A
IN
O
O
O
O
V
IN
V
O
FIGURE 17. POWER-UP
FIGURE 18. POWER-DOWN
V
=3.3V, V =1.8V AT 4A
IN
V
=3.3V, V =1.8V AT 4A
O
O
IN
EN
EN
V
O
V
O
FIGURE 19. ENABLE
FIGURE 20. DISABLE
FN7296.2
8
May 13, 2005
EL7563
Typical Performance Curves (20 Pin SO Package) (Continued)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
V
=3.3V, V =1.8V, I =4A TO SHORT
O O
IN
I
O
O
V
FIGURE 21. SHORT-CIRCUIT PROTECTION
Block Diagram
390pF
0.1µF
V
C
OSC
REF
D
D
4
2
V
DRV
VTJ
JUNCTION
VOLTAGE
OSCILLATOR
TEMPERATURE REFERENCE
2.2nF
0.22µF
0.1µF
V
V
HI
IN
CONTROLLER
SUPPLY
22Ω
D
3
V
DD
D
1
POWER
0.22µF
4.7µH
3.3V
0.22µF
FET
PWM
V
OUT
DRIVERS
CONTROLLER
(2.5V, 4A)
POWER
FET
1.58kΩ
1kΩ
2.2nF
330µF
PGND
PG
EN
STP
STN
POWER
CURRENT
TRACKING
SENSE
V
REF
-
+
SGND
FB
FN7296.2
9
May 13, 2005
EL7563
Applications Information
Circuit Description
General
The EL7563 is a fixed frequency, current mode controlled
DC/DC converter with integrated N-channel power
MOSFETs and a high precision reference. The device
incorporates all the active circuitry required to implement a
cost effective, user-programmable 4A synchronous step-
down regulator suitable for use in DSP core power supplies.
By combining fused-lead packaging technology with an
efficient synchronous switching architecture, high power
output (10W) can be realized without the use of discrete
external heat sinks.
feedback is measured by the patented sensing scheme that
senses the inductor current flowing through the high-side
switch whenever it is conducting. At the beginning of each
oscillator period the high-side NMOS switch is turned on.
The comparator inputs are gated off for a minimum period of
time of about 150ns (LEB) after the high-side switch is
turned on to allow the system to settle. The Leading Edge
Blanking (LEB) period prevents the detection of erroneous
voltages at the comparator inputs due to switching noise. If
the inductor current exceeds the maximum current limit
(I
) a secondary over-current comparator will terminate
LMAX
the high-side switch on time. If I
has not been reached,
LMAX
the feedback voltage FB derived from the regulator output
voltage V is then compared to the internal feedback
OUT
PWM Controller
reference voltage. The resultant error voltage is summed
with the current feedback and slope compensation ramp.
The high-side switch remains on until all four comparator
inputs have summed to zero, at which time the high-side
switch is turned off and the low-side switch is turned on.
However, the maximum on-duty ratio of the high-side switch
is limited to 95%. In order to eliminate cross-conduction of
the high-side and low-side switches a 15ns break-before-
make delay is incorporated in the switch drive circuitry. The
output enable (EN) input allows the regulator output to be
disabled by an external logic control signal.
The EL7563 regulates output voltage through the use of
current-mode controlled pulse width modulation. The three
main elements in a PWM controller are the feedback loop and
reference, a pulse width modulator whose duty cycle is
controlled by the feedback error signal, and a filter which
averages the logic level modulator output. In a step-down
(buck) converter, the feedback loop forces the time-averaged
output of the modulator to equal the desired output voltage.
Unlike pure voltage-mode control systems, current-mode
control utilizes dual feedback loops to provide both output
voltage and inductor current information to the controller. The
voltage loop minimizes DC and transient errors in the output
voltage by adjusting the PWM duty-cycle in response to
changes in line or load conditions. Since the output voltage is
equal to the time-averaged of the modulator output, the
relatively large LC time constant found in power supply
applications generally results in low bandwidth and poor
transient response. By directly monitoring changes in inductor
current via a series sense resistor the controller's response
time is not entirely limited by the output LC filter and can react
more quickly to changes in line and load conditions. This feed-
forward characteristic also simplifies AC loop compensation
since it adds a zero to the overall loop response. Through
proper selection of the current-feedback to voltage-feedback
ratio the overall loop response will approach a one-pole
system. The resulting system offers several advantages over
traditional voltage control systems, including simpler loop
compensation, pulse by pulse current limiting, rapid response
to line variation and good load step response.
Output Voltage Setting
In general:
R
2
V
= 0.992V × 1 + ------
OUT
R
1
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and loop-
gain is changed. This is shown in the performance curves. A
100nA pull-up current from FB to V
in the event that FB is floating.
forces V
to GND
DD
OUT
NMOS Power FETs and Drive Circuitry
The EL7563 integrates low on-resistance (30mΩ) NMOS
FETs to achieve high efficiency at 4A. In order to use an
NMOS switch for the high-side drive it is necessary to drive
the gate voltage above the source voltage (L ). This is
X
accomplished by bootstrapping the V pin above the L
HI
X
voltage with an external capacitor CV and internal switch
HI
and diode. When the low-side switch is turned on and the L
X
The heart of the controller is an input direct summing
comparator which sum voltage feedback, current feedback,
slope compensation ramp and power tracking signals
together. Slope compensation is required to prevent system
instability that occurs in current-mode topologies operating
at duty-cycles greater than 50% and is also used to define
the open-loop gain of the overall system. The slope
compensation is fixed internally and optimized for 500mA
inductor ripple current. The power tracking will not contribute
any input to the comparator steady-state operation. Current
voltage is close to GND potential, capacitor CV is charged
HI
through internal switch to V
, typically 6V with external
DRV
charge-pump. At the beginning of the next cycle the high-
side switch turns on and the L pins begin to rise from GND
X
to V potential. As the L pin rises the positive plate of
IN
X
capacitor CV follows and eventually reaches a value of
HI
V
+V , typically 9V, for V =3.3V. This voltage is then
DRV IN IN
level shifted and used to drive the gate of the high-side FET,
via the V pin. A value of 0.22µF for CV is recommended.
HI HI
FN7296.2
10
May 13, 2005
EL7563
Reference
Junction Temperature Sensor
A 1.5% temperature compensated bandgap reference is
An internal temperature sensor continuously monitors die
temperature. In the event that die temperature exceeds the
thermal trip-point, the system is in fault state and will be shut
down. The upper and low trip-points are set to 135°C and
115°C respectively.
integrated in the EL7563. The external V
capacitor acts
REF
as the dominant pole of the amplifier and can be increased
in size to maximize transient noise rejection. A value of
0.1µF is recommended.
The VTJ pin is an accurate indication of the internal silicon
junction temperature (see performance curve.) The junction
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 95%.
temperature T (°C) can be deducted from the following
J
relation:
Operating frequency can be adjusted through the C
pin
OSC
or can be driven by an external source. If the oscillator is
driven by an external source care must be taken in selecting
the ramp amplitude. Since C value is derived from the
1.2 – VTJ
0.00384
T
= 75 + -------------------------
J
SLOPE
ramp will change the
C
C
ramp, changes to C
SLOPE
gain of the system.
OSC
OSC
Where VTJ is the voltage at VTJ pin in volts.
compensation ramp which determine the open-loop
Power Good and Power On Reset
During power up the output regulator will be disabled until
When external synchronization is required, always choose
V
reaches a value of approximately 2.9V. About 300mV
IN
C
such that the free-running frequency is at least 20%
OSC
hysteresis is present to eliminate noise-induced
oscillations.
lower than that of sync source to accommodate component
and temperature variations. Figure 22 shows a typical
connection.
Under-voltage and over-voltage conditions on the regulator
output are detected through an internal window comparator.
A logic high on the PG output indicates that the regulated
output voltage is within about +10% of the nominal selected
output voltage.
1
2
20
19
18
16
15
14
13
12
11
100pF
BAT54S
390pF
EXTERNAL
3
OSCILLATOR
5
6
EL7563
7
8
9
10
FIGURE 22. OSCILLATOR SYNCHRONIZATION
FN7296.2
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May 13, 2005
EL7563
Power Tracking
The power tracking pins STP and STN are the inputs to a
comparator, whose HI output forces the PWM controller to
skip switching cycle.
2. Offset Tracking
The intended start-up sequence is shown in Figure 24. In
this configuration, V will not start until V reaches a preset
C
P
value of:
R
B
1. Linear Tracking
---------------------
× V
IN
R
+ R
B
A
In this application, it is always the case that the lower voltage
supply V tracks the higher output supply V . See Figure 23.
C
P
1
2
20
19
15
14
13
12
11
6
V
C
7
EL7563
8
V
V
P
C
9
+
-
10
V
OUT
1
2
20
19
15
14
13
12
11
TIME
6
V
P
7
EL7563
8
9
+
-
10
FIGURE 23. LINEAR POWER TRACKING
1
2
20
19
15
14
13
12
11
6
V
C
EL7563
7
V
IN
R
8
A
V
P
C
STP
9
+
-
STN
R
10
B
V
V
OUT
1
2
20
19
15
14
13
12
11
TIME
6
V
P
7
EL7563
8
STP
9
+
-
STN
10
FIGURE 24. OFFSET POWER TRACKING
FN7296.2
12
May 13, 2005
EL7563
The second way of offset tracking is to use the EN and
Power Good pins, as shown in Figure 25. In this
3. External Soft Start
An external soft start can be combined with auxiliary supply
tracking to provide desired soft start other than internally
preset soft start (Figure 26). The appropriate start-up time is:
configuration, V does not have to be larger than V .
P
C
V
O
---------
t
= R × C ×
s
V
IN
1
2
EN 20
19
3
PG 18
16
5
6
EL7563
15
V
C
7
14
8
13
9
12
10
11
V
V
P
C
1
2
EN 20
19
TIME
3
PG 18
16
5
6
EL7563
15
V
P
7
14
8
13
9
12
10
11
FIGURE 25. OFFSET TRACKING
1
2
20
19
15
14
13
12
11
6
V
OUT
V
IN
7
EL7563
R
C
8
STP
9
+
-
STN
10
FIGURE 26. EXTERNAL SOFT START
FN7296.2
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May 13, 2005
EL7563
The EL7563CRE utilizes the 28-pin HTSSOP package. The
Start-up Delay
A capacitor can be added to the EN pin to delay the
converter start-up (Figure 27) by utilizing the pull-up current.
The delay time is approximately:
majority of heat is dissipated through the heat pad exposed
at the bottom of the package. Therefore, the heat pad needs
to be soldered to the PCB. The thermal resistance for this
package is as low as 29°C/W, better than that of the SO20.
Typical performance is shown in the curve section. The
actual junction temperature can be measured at VTJ pin.
t (ms) = 1200 × C(µF)
d
Thermal Management
Since the thermal performance of the IC is heavily
The EL7563CM utilizes “fused lead” packaging technology in
conjunction with the system board layout to achieve a lower
thermal resistance than typically found in standard SO20
packages. By fusing (or connecting) multiple external leads
to the die substrate within the package, a very conductive
heat path is created to the outside of the package. This
conductive heat path MUST then be connected to a heat
sinking area on the PCB in order to dissipate heat out and
away from the device. The conductive paths for the SO20
package are the fused leads: # 6, 7, 11, 12, and 13. If a
sufficient amount of PCB metal area is connected to the
fused package leads, a junction-to-ambient resistance of
43°C/W can be achieved (compared to 85°C/W for a
standard SO20 package). The general relationship between
PCB heat-sinking metal area and the thermal resistance for
this package is shown in the Performance Curves section of
this data sheet. It can be readily seen that the thermal
resistance for this package approaches an asymptotic value
of approximately 43°C/W without any airflow, and 33°C/W
with 100 LFPM airflow. Additional information can be found
in Application Note #8 (Measuring the Thermal Resistance
of Power Surface-Mount Packages). For a thermal shutdown
die junction temperature of 135°C, and power dissipation of
1.5W, the ambient temperature can be as high as 70°C
without airflow. With 100 LFPM airflow, the ambient
dependent on the board layout, the system designer should
exercise care during the design phase to ensure that the IC
will operate under the worst-case environmental conditions.
Layout Considerations
The layout is very important for the converter to function
properly. Power Ground ( ) and Signal Ground (
)
should be separated to ensure that the high pulse current in
the Power Ground never interferes with the sensitive signals
connected to Signal Ground. They should only be connected
at one point (normally at the negative side of either the input
or output capacitor.)
The trace connected to the FB pin is the most sensitive
trace. It needs to be as short as possible and in a “quiet”
place, preferably between PGND or SGND traces.
In addition, the bypass capacitor connected to the V
needs to be as close to the pin as possible.
pin
DD
The heat of the chip is mainly dissipated through the PGND
pins and through the heat pad at the bottom of the CRE
package. Maximizing the copper area around these pins is
preferable. In addition, a solid ground plane is always helpful
for the EMI performance.
The demo board is a good example of layout based on these
principles. Please refer to the EL7563 Application Brief for
the layout.
temperature can be extended to 85°C.
1
2
20
19
15
14
13
12
11
C
6
V
OUT
7
EL7563
V
V
IN
8
O
STP
9
t
+
-
d
STN
10
TIME
FIGURE 27. START-UP DELAY
FN7296.2
14
May 13, 2005
EL7563
SO Package Outline Drawing
FN7296.2
15
May 13, 2005
EL7563
HTSSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
<http://www.intersil.com/design/packages/index.asp>
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7296.2
16
May 13, 2005
EL7563CREZ-T7 CAD模型
引脚图
封装焊盘图
EL7563CREZ-T7 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| EL7563CREZ | INTERSIL | Monolithic 4 Amp DC:DC Step-Down Regulator | 完全替代 |
|
| EL7563CREZ-T13 | INTERSIL | Monolithic 4 Amp DC:DC Step-Down Regulator | 类似代替 |
|
| EL7554IREZ | INTERSIL | Monolithic 4 Amp DC-DC Step-Down Regulator | 功能相似 |
|
EL7563CREZ-T7 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| EL7564 | INTERSIL | Monolithic 4 Amp DC/DC Step-Down Regulator | 获取价格 |
|
| EL7564C | ELANTEC | Monolithic 4 Amp DC:DC Step-down Regulator | 获取价格 |
|
| EL7564CM | ELANTEC | Monolithic 4 Amp DC:DC Step-down Regulator | 获取价格 |
|
| EL7564CM | INTERSIL | Monolithic 4 Amp DC/DC Step-Down Regulator | 获取价格 |
|
| EL7564CM-T13 | ELANTEC | Monolithic 4 Amp DC:DC Step-down Regulator | 获取价格 |
|
| EL7564CM-T13 | INTERSIL | Monolithic 4 Amp DC/DC Step-Down Regulator | 获取价格 |
|
| EL7564CMZ | INTERSIL | Monolithic 4 Amp DC/DC Step-Down Regulator | 获取价格 |
|
| EL7564CMZ-T13 | INTERSIL | Monolithic 4 Amp DC/DC Step-Down Regulator | 获取价格 |
|
| EL7564CRE | ELANTEC | Monolithic 4 Amp DC:DC Step-down Regulator | 获取价格 |
|
| EL7564CRE | INTERSIL | Monolithic 4 Amp DC/DC Step-Down Regulator | 获取价格 |
|
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