EL7585A [INTERSIL]
TFT-LCD Power Supply; TFT- LCD电源
| 型号： | EL7585A |
| 厂家： | 
Intersil |
| 描述： | TFT-LCD Power Supply |
| 文件： | 总18页 (文件大小：729K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL7585A
®
Data Sheet
September 21, 2005
FN7523.2
TFT-LCD Power Supply
The EL7585A represents a multiple output regulators for use
in all large panel, TFT-LCD applications. It features a single
boost converter with integrated 3.5A FET, two positive LDOs
Features
• 3.5A current limit FET options
• 3V to 5V input
• Up to 20V boost out
• 1% regulation on all outputs
for V
for V
and V
OFF
generation, and a single negative LDO
ON
LOGIC
generation. The boost converter can be
programmed to operate in either P-mode or PI-mode for
improved load regulation.
• V
-V
-V
BOOST OFF ON
or
OFF BOOST ON
V
-V -V
sequence control
The EL7585A also integrates fault protection for all four
channels. Once a fault is detected, the device is latched off
until the input supply or EN is cycled. This device also
- V
is on from start-up for EL7585A
LOGIC
• Programmable sequence delay
• Fully fault protected
features an integrated start-up sequence for V
V
,
BOOST, OFF
sequencing. The
then V
or for V
, V
, and V
ON
OFF BOOST
ON
• Thermal shutdown
latter requires a single external transistor. The timing of the
start-up sequence is set using an external capacitor. The
• Internal soft-start
V
output is constantly enabled, but does shut down
LOGIC
• 20 Ld QFN packages
when a fault condition is detected.
• Pb-free plus anneal available (RoHS compliant)
The EL7585A is specified for operation over the -40°C to
+85°C temperature range.
Applications
• LCD monitors (15”+)
Pinout
EL7585A
(20 LD QFN)
TOP VIEW
• LCD-TV (up to 40”+)
• Notebook displays (up to 16”)
• Industrial/medical LCD displays
Ordering Information
PART
TAPE&
PKG.
CDLY
DELB
LX1
1
2
3
4
5
15 CINT
14 VREF
13 PGND
12 PGND
11 FBN
PART NUMBER MARKING
PACKAGE
REEL DWG. #
EL7585AILZ
(Note)
EL7585AIL Z 20 Ld 4x4 QFN
(Pb-free)
-
MDP0046
MDP0046
MDP0046
THERMAL
PAD
EL7585AILZ-T7 EL7585AIL Z 20 Ld 4x4 QFN
(Note) (Pb-free)
7”
LX2
DRVP
EL7585AILZ-T13 EL7585AIL Z 20 Ld 4x4 QFN
(Note) (Pb-free)
13”
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
EL7585A
Absolute Maximum Ratings (T = 25°C)
A
V
V
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
DRVL
DRVP
DRVN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum continuous junction temperature. . . . . . . . . . . . . . 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
DD
DELB, LX
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications
V
= 5V, V
= 11V, I
= 200mA, V
= 15V, V
OFF
= -5V, V = 2.5V, over temperature from
LOGIC
DD
BOOST
LOAD
ON
-40°C to 85°C, unless otherwise specified.
PARAMETER
SUPPLY
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
V
Supply Voltage
3
5.5
2.5
V
S
I
Quiescent Current
Enabled, LX not switching
Disabled
1.7
mA
µA
S
700
900
CLOCK
F
Oscillator Frequency
900
1000
1100
kHz
OSC
BOOST
V
V
Boost Output Range
5.5
20
V
V
BOOST
FBB
Boost Feedback Voltage
T
= 25°C
= 25°C
1.192
1.188
1.205
1.205
0.9
1.218
1.222
A
V
V
V
FBB Fault Trip Point
Reference Voltage
V
F_FBB
REF
T
1.19
1.187
22
1.215
1.215
100
1.235
1.238
V
A
V
C
D
V
Capacitor
nF
%
REF
REF
Maximum Duty Cycle
Switch Current Limit
Switch Leakage Current
Switch On-Resistance
Boost Efficiency
85
MAX
I
I
3.5
A
LXMAX
LEAK
V
= 16V
10
µA
mΩ
%
LX
r
160
92
DS(ON)
Eff
I(V
See curves
Pl mode, V
)
Feedback Input Bias Current
Line Regulation
= 1.35V
50
500
nA
%/V
FBB
FBB
= 4.7nF, I = 100mA, V = 3V to 5.5V
OUT IN
∆V
∆V
/
/
/
C
0.05
BOOST
IN
INT
∆V
∆I
Load Regulation - “P” mode
Load Regulation - “PI” mode
CINT Pl Mode Select Threshold
C
pin strapped to V
,
3
%
%
V
BOOST
BOOST
INT
DD
< 250mA
50mA < I
LOAD
∆V
∆I
C
= 4.7nF, 50mA < I < 250mA
0.1
4.7
BOOST
BOOST
INT
O
V
V
V
4.8
CINT_T
LDO
ON
FBP Regulation Voltage
I
I
= 0.2mA, T = 25°C
A
1.176
1.172
0.82
1.2
1.2
1.224
1.228
0.92
V
V
FBP
DRVP
= 0.2mA
falling
DRVP
V
FBP Fault Trip Point
V
V
V
0.87
V
F_FBP
FBP
I
FBP Input Bias Current
FBP Effective Transconductance
= 1.35V
-250
250
nA
ms
FBP
FBP
GMP
= 25V, I
= 0.2 to 2mA
DRVP
50
DRVP
FN7523.2
2
September 21, 2005
EL7585A
Electrical Specifications
V
= 5V, V
= 11V, I
LOAD
= 200mA, V
= 15V, V
OFF
= -5V, V = 2.5V, over temperature from
LOGIC
DD
BOOST
ON
-40°C to 85°C, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
∆V /∆I(V ) V Load Regulation
ON
CONDITION
MIN
TYP
-0.5
4
MAX
UNIT
%
I(V ) = 0mA to 20mA
ON
ON
ON
I
I
DRVP Sink Current Max
DRVP Leakage Current
V
V
= 1.1V, V
= 1.5V, V
= 25V
= 35V
2
mA
µA
DRVP
FBP
FBP
DRVP
DRVP
0.1
5
L_DRVP
V
LDO
OFF
V
FBN Regulation Voltage
I
I
= 0.2mA, T = 25°C
A
0.173
0.171
0.38
0.203
0.203
0.43
0.233
0.235
0.48
V
V
FBN
DRVN
DRVN
= 0.2mA
rising
V
FNN Fault Trip Point
V
V
V
V
F_FBN
FBN
I
FBN Input Bias Current
FBN Effective Transconductance
= 0.2V
-250
250
nA
ms
%
FBN
FBN
GMN
∆V
∆I(V
= -6V, I
DRVN
= 0.2mA to 2mA
50
DRVN
/
V
Load Regulation
I(V
) = 0mA to 20mA
OFF
-0.5
OFF
OFF
OFF
)
I
I
DRVN Source Current Max
DRVN Leakage Current
V
V
= 0.3V, V
= -6V
2
4
mA
µA
DRVN
L_DRVN
FBN
FBN
DRVN
= -20V
= 0V, V
0.1
5
DRVN
V
LDO
LOGIC
V
FBL Regulation Voltage
I
I
= 1mA, T = 25°C
A
1.176
1.174
0.82
1.2
1.2
1.224
1.226
0.92
V
V
FBL
DRVL
DRVL
= 1mA
falling
V
FBL Fault Trip Point
V
V
V
0.87
V
F_FBL
FBL
I
FBL Input Bias Current
FBL Effective Transconductance
= 1.35V
-500
500
nA
ms
%
FBL
FBL
G
= 2.5V, I
DRVL
= 1mA to 8mA
200
0.5
ML
DRVL
∆V
∆I(V
/
V
Load Regulation
I(V
) = 100mA to 500mA
LOGIC
LOGIC
LOGIC
LOGIC
)
I
I
DRVL Sink Current Max
V
V
= 1.1V, V
= 2.5V
= 5.5V
8
16
mA
µA
DRVL
L_DRL
FBL
FBL
DRVL
I
= 1.5V, V
0.1
5
L_DRVL
DRVL
SEQUENCING
t
t
t
t
t
Turn On Delay
C
C
C
C
C
= 0.22µF
= 0.22µF
= 0.22µF
= 0.22µF
= 0.22µF
30
2
ms
ms
ms
ms
ms
ON
DLY
DLY
DLY
DLY
DLY
Soft-start Time
SS
Delay Between A
Delay Between V
Delay Between V
and V
OFF
10
17
10
DEL1
DEL2
DEL3
VDD
and V
ON
OFF
and Delayed
OFF
V
BOOST
I
DELB Pull-down Current
Delay Capacitor
V
V
> 0.6V
< 0.6V
50
1.4
220
µA
mA
nF
DELB
DELB
DELB
C
10
DEL
FAULT DETECTION
t
Fault Time Out
C
= 0.22µF
DLY
50
140
15
ms
°C
FAULT
OT
Over-temperature Threshold
PG Pull-down Current
I
VPG>0.6V
VPG<0.6V
µA
mA
PG
1.7
LOGIC ENABLE
V
V
Logic High Threshold
Logic Low Threshold
2.2
V
V
HI
0.8
LO
FN7523.2
3
September 21, 2005
EL7585A
Electrical Specifications
V
= 5V, V
= 11V, I
LOAD
= 200mA, V
= 15V, V
OFF
= -5V, V = 2.5V, over temperature from
LOGIC
DD
BOOST
ON
-40°C to 85°C, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
Logic Low bias Current
Logic High bias Current
CONDITION
MIN
TYP
0.2
18
MAX
1
UNIT
µA
I
I
LOW
at V
= 5V
EN
12
24
µA
HIGH
Pin Descriptions
PIN NAME
PIN NUMBER
DESCRIPTION
1
CDLY
A capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault
timeout time
2
3, 4
5
DELB
LX1, LX2
DRVP
FBP
Gate drive of optional V
delay FET
BOOST
Drain of the internal N channel boost FET; for EL7586, pin 4 is not connected
Positive LDO base drive; open drain of an internal N channel FET
Positive LDO voltage feedback input pin; regulates to 1.2V nominal
Logic LDO base drive; open drain of an internal N channel FET
Logic LDO voltage feedback input pin; regulates to 1.2V nominal
Low noise signal ground
6
7
DRVL
FBL
8
9, 17
10
SGND
DRVN
FBN
Negative LDO base drive; open drain of an internal P channel FET
Negative LDO voltage feedback input pin; regulates to 0.2V nominal
Power ground, connected to source of internal N channel boost FET
Bandgap voltage bypass, connect a 0.1µF to SGND
11
12, 13
14
PGND
VREF
CINT
15
V
integrator output, connect capacitor to SGND for PI mode or connect to V
for P mode
DD
BOOST
operation
16
18
19
20
FBB
EN
Boost regulator voltage feedback input pin; regulates to 1.2V nominal
Enable pin, High=Enable; Low or floating=Disable
Positive supply
VDD
PG
Gate drive of optional fault protection FET, when chip is disabled or when a fault has been detected, this
is high
Typical Performance Curves
100
90
80
100
90
80
70
60
50
40
30
20
10
0
V
=9V
O
V
O
=9V
O
V
=12V
O
V
=12V
70
V
=15V
O
V
=15V
60
50
40
30
20
10
0
O
0
0.1
0.2
0.3
(A)
0.4
0.5
0.6
0
0.5
1
1.5
I
I
(A)
OUT
OUT
FIGURE 1. V
EFFICIENCY AT V =3V (PI MODE)
IN
FIGURE 2. V
EFFICIENCY AT V =5V (PI MODE)
BOOST IN
BOOST
FN7523.2
September 21, 2005
4
EL7585A
Typical Performance Curves (Continued)
100
100
90
80
70
60
50
40
30
20
10
0
V
=9V
O
V
=9V
90
80
70
60
50
40
30
20
10
0
O
V
=12V
O
V
=15V
O
V
=12V
O
V
=15V
O
0
0.1
0.2
0.3
0.4
(A)
0.5
0.6
0.7
0
0.5
1
1.5
I
OUT
I
(A)
OUT
FIGURE 3. V
EFFICIENCY AT V =3V (P MODE)
IN
BOOST
FIGURE 4. V
EFFICIENCY AT V =5V (P MODE)
IN
BOOST
0
-0.1
-0.2
-0.3
-0.4
0
-0.1
-0.2
-0.3
-0.4
V
=9V
O
V
=9V
O
V
=15V
O
V
=12V
O
-0.5
V
=15V
O
V
=12V
0.5
O
-0.5
0
-0.6
0
0.1
0.2
0.3
(A)
0.4
0.6
0.2
0.4
0.6
OUT
0.8
(A)
1
1.2
1.4
I
I
OUT
FIGURE 5. V
LOAD REGULATION AT V =3V (PI MODE)
IN
FIGURE 6. V
LOAD REGULATION AT V =5V (PI MODE)
BOOST IN
BOOST
0
-1
-2
-3
-4
-5
-6
-7
-8
0
-2
-4
V
=9V
O
V
=9V
O
-6
V
=15V
0.2
O
-8
V
=15V
O
V
=12V
0.4
V
=12V
O
O
-10
0
0.6
0.8
0
0.5
1
1.5
I
(A)
I
(A)
OUT
OUT
FIGURE 7. V
LOAD REGULATION AT V =3V (P MODE)
IN
FIGURE 8. V
LOAD REGULATION AT V =5V (P MODE)
BOOST IN
BOOST
FN7523.2
5
September 21, 2005
EL7585A
Typical Performance Curves (Continued)
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
0
20
40
(mA)
60
80
0
20
40
60
(mA)
80
100
I
I
OUT
OUT
FIGURE 9. V
LOAD REGULATION
FIGURE 10. V
LOAD REGULATION
OFF
ON
0
-0.2
-0.4
-0.6
-0.8
-1
V
CDLY
V
LOGIC
V
IN
EN
C
=220nF
DLY
-1.2
0
100
200
400
500
600
700
300
I
(mA)
TIME (10ms/DIV)
OUT
FIGURE 11. V
LOAD REGULATION
FIGURE 12. START-UP SEQUENCE
LOGIC
AVDD
LOGIC
V
CDLY
V
V
LOGIC
V
OFF
V
IN
V
C
=220nF
DLY
ON
C
=220nF
DLY
V
REF
TIME (10ms/DIV)
TIME (10ms/DIV)
FIGURE 13. START-UP SEQUENCE
FIGURE 14. START-UP SEQUENCE
FN7523.2
September 21, 2005
6
EL7585A
Typical Performance Curves (Continued)
AVDD
V
LOGIC
V
OFF
V
V
=5V
IN
OUT
=30mA
=13V
V
C
=220nF
DLY
ON
I
OUT
TIME (400ns/DIV)
TIME (10ms/DIV)
FIGURE 15. START-UP SEQUENCE
FIGURE 16. LX WAVEFORM - DISCONTINUOUS MODE
JEDEC JESD51-3 AND SEMI G42-88
(SINGLE LAYER) TEST BOARD
0.8
714mW
0.7
667mW
0.6
QFN24
0.5
0.4
0.3
0.2
0.1
0
θ
=140°C/W
JA
QFN16
=150°C/W
θ
JA
V
V
=5V
IN
OUT
=200mA
=13V
0
25
50
75 85 100
125
150
I
OUT
AMBIENT TEMPERATURE (°C)
TIME (400ns/DIV)
FIGURE 17. LX WAVEFORM - CONTINUOUS MODE
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3
2.5
2
2.703W
2.500W
QFN24
θ
=37°C/W
JA
QFN16
=40°C/W
1.5
1
θ
JA
0.5
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FN7523.2
7
September 21, 2005
EL7585A
V
REF
REFERENCE
OSCILLATOR
SLOPE COMP OSC
COMPENSATION
LX
PWM
LOGIC
Σ
BUFFER
CONTROLLER
VOLTAGE
FBB
AMPLIFIER
GM
AMPLIFIER
C
INT
CURRENT
PGND
AMPLIFIER
UVLO
COMPARATOR
CURRENT REF
CURRENT
LIMIT COMPARATOR
SS
+
-
SHUTDOWN
& START-UP
CONTROL
V
DRVP
FBP
REF
BUFFER
BUFFER
THERMAL
SHUTDOWN
UVLO
COMPARATOR
SS
+
-
SS
+
-
DRVN
FBN
0.2V
V
DRVL
FBL
REF
BUFFER
0.4V
UVLO
UVLO
COMPARATOR
COMPARATOR
FIGURE 20. BLOCK DIAGRAM
TABLE 1. RECOMMENDED COMPONENTS (Continued)
Applications Information
DESIGNATION
DESCRIPTION
The EL7585A is a highly integrated multiple output power
solution for TFT-LCD applications. The system consists of
one high efficiency boost converter and three linear-
D
1A 20V low leakage Schottky rectifier (CASE 457-
04) ON SEMI MBRM120ET3
1
regulator controllers (V , V
, and V
) with multiple
ON OFF
LOGIC
D
, D , D
200mA 30V Schottky barrier diode (SOT-23)
Fairchild BAT54S
11 12 21
protection functions. A block diagram is shown in Figure 20.
Table 1 lists the recommended components.
L
6.8µH 1.3A Inductor
TDK SLF6025T-6R8M1R3-PF
1
The EL7585A integrates an N-channel MOSFET boost
converter to minimize external component count and cost.
Q
Q
Q
Q
Q
-2.4 -20V P-channel 1.8V specified PowerTrench
MOSFET (SuperSOT-3) Fairchild FDN304P
1
4
3
2
5
The A
, V , V
, and V
output voltages are
VDD ON OFF
LOGIC
independently set using external resistors. V , V
ON OFF
-2A -30V single P-channel logic level PowerTrench
MOSFET (SuperSOT-3) Fairchild FDN360P
voltages require external charge pumps which are post
regulated using the integrated LDO controllers.
200mA 40V PNP amplifier (SOT-23)
Fairchild MMBT3906
TABLE 1. RECOMMENDED COMPONENTS
200mA 40V NPN amplifier (SOT-23)
Fairchild MMBT3904
DESIGNATION
C , C , C
DESCRIPTION
10µF, 16V X5R ceramic capacitor (1206)
TDK C3216X5R0J106K
1
2
3
1A 30V PNP low saturation amplifier (SOT-23)
Fairchild FMMT549
C
, C
4.7µF, 25V X5R ceramic capacitor (1206)
TDK C3216X5R1A475K
20 31
FN7523.2
8
September 21, 2005
EL7585A
An external resistor divider is required to divide the output
Boost Converter
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by the
following equation:
The main boost converter is a current mode PWM converter at
a fixed frequency of 1MHz which enables the use of low profile
inductors and multilayer ceramic capacitors. This results in a
compact, low cost power system for LCD panel design.
The EL7585A is designed for continuous current mode, but
they can also operate in discontinuous current mode at light
load. In continuous current mode, current flows continuously
in the inductor during the entire switching cycle in steady
state operation. The voltage conversion ratio in continuous
current mode is given by:
R
+ R
1
2
--------------------
A
=
× V
VDD
REF
R
1
The current through the MOSFET is limited to 3.5A peak.
This restricts the maximum output current based on the
following equation:
A
V
1
VDD
--------------- = -------------
1 – D
IN
V
V
∆I
2
Where D is the duty cycle of the switching MOSFET.
IN
L
---------
I
=
I
– --------
×
OMAX
LMT
O
Figure 21 shows the block diagram of the boost regulator. It
uses a summing amplifier architecture consisting of GM
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.
Where ∆IL is peak to peak inductor ripple current, and is set by:
V
D
IN
×
--------- ----
∆I
=
L
L
f
S
where f is the switching frequency.
S
SHUTDOWN
& START-UP
CONTROL
CLOCK
SLOPE
COMPENSATION
Ifb
CURRENT
AMPLIFIER
PWM
LOGIC
Iref
LX
BUFFER
Ifb
FBB
GM
AMPLIFIER
Iref
VOLTAGE
AMPLIFIER
REFERENCE
GENERATOR
PGND
CINT
FIGURE 21. BLOCK DIAGRAM OF THE BOOST REGULATOR
FN7523.2
9
September 21, 2005
EL7585A
The following table gives typical values (margins are
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
considered 10%, 3%, 20%, 10%, and 15% on V , V , L, f ,
IN
O
S
and I
:
OMAX
NOTE: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
TABLE 2.
C
in the equation above assumes the effective value of the
OUT
f
S
capacitor at a particular voltage and not the manufacturer’s stated
value, measured at zero volts.
V
(V)
V
(V)
L (µH)
6.8
(MHz)
I
OMAX
IN
O
3.3
3.3
3.3
5
9
1
1
1
1
1
1
1.040686
0.719853
0.527353
1.576797
1.090686
0.79902
Compensation
The EL7585A can operate in either P mode or PI mode.
12
15
9
6.8
Connecting the C
pin directly to V will enable P mode;
6.8
INT
For better load regulation, use PI mode with a 4.7nF
capacitor in series with a 10K resistor between C
IN
6.8
and
INT
5
12
15
6.8
ground. This value may be reduced to improve transient
performance, however, very low values will reduce loop
stability.
5
6.8
Input Capacitor
Boost feedback resistors
An input capacitor is used to supply the peak charging
As the boost output voltage, A
, is reduced below 12V the
VDD
current to the converter. It is recommended that C be
effective voltage feedback in the IC increases the ratio of
voltage to current feedback at the summing comparator
because R decreases relative to R . To maintain stable
IN
larger than 10µF. The reflected ripple voltage will be smaller
with larger C . The voltage rating of input capacitor should
IN
2
1
be larger than maximum input voltage.
operation over the complete current range of the IC, the
voltage feedback to the FBB pin should be reduced
Boost Inductor
proportionally, as A
is reduced, by means of a series
resistor-capacitor network (R and C ) in parallel with R ,
VDD
The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH are to match the internal slope
compensation. The inductor must be able to handle the
following average and peak current:
7
7
1
with a pole frequency (f ) set to approximately 10kHz for C
effective = 10µF and 4kHz for C (effective) = 30µF.
2
p
2
R = ((1/0.1 x R ) - 1/R )^-1
7
2
1
C = 1/(2 x 3.142 x f x R )
I
7
p
7
O
I
I
= -------------
LAVG
LPK
1 – D
PI mode C
(C ) and R
INT 23
(R )
INT 10
∆I
2
L
The IC is designed to operate with a minimum C capacitor
23
= I
+ --------
LAVG
of 4.7nF and a minimum C (effective) = 10µF.
2
Note that, for high voltage A
, the voltage coefficient of
VDD
Rectifier Diode
ceramic capacitors (C ) reduces their effective capacitance
2
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The rectifier
diode must meet the output current and peak inductor
current requirements.
greatly; a 16V 10µF ceramic can drop to around 3µF at 15V.
To improve the transient load response of A
in PI mode,
VDD
a resistor may be added in series with the C capacitor. The
23
larger the resistor the lower the overshoot but at the expense
of stability of the converter loop - especially at high currents.
Output Capacitor
With L = 10µH, A
VDD
= 15V, C = 4.7nF, C (effective)
23
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage
consists of two components: the voltage drop due to the
inductor ripple current flowing through the ESR of output
capacitor, and the charging and discharging of the output
capacitor.
2
should have a capacitance of greater than 10µF. R
(R )
7
INT
can have values up to 5kΩ for C (effective) up to 20µF and
up to 10K for C (effective) up to 30µF.
2
2
Larger values of R
INT
(R ) may be possible if maximum
7
A
load currents less than the current limit are used. To
VDD
V
– V
I
O
ensure A
stability, the IC should be operated at the
VDD
maximum desired current and then the transient load
response of A should be used to determine the
1
×
O
IN
----------------------- --------------- ----
V
= I
× ESR +
LPK
×
RIPPLE
V
C
f
S
O
OUT
VDD
maximum value of R
.
INT
For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output
FN7523.2
10
September 21, 2005
EL7585A
The base-emitter saturation voltage is: Vbe_max = 1.25V
Cascaded MOSFET Application
(note this is normally a Vbe ~ 0.7V, however, for the Q5
transistor an internal Darlington arrangement is used to
increase it's current gain, giving a 'base-emitter' voltage of
A 20V N-channel MOSFET is integrated in the boost
regulator. For the applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed
as shown in Figure 22. The voltage rating of the external
2 x V ).
BE
MOSFET should be greater than V
.
BOOST
(Note that using a high current Darlington PNP transistor for
Q5 requires that V > V
+ 2V. Should a lower input
IN LOGIC
V
V
BOOST
IN
voltage be required, then an ordinary high gain PNP
transistor should be selected for Q5 so as to allow a lower
collector-emitter saturation voltage).
LX
For the EL7585A, the minimum drive current is:
I_DRVL_min = 8mA
FB
The minimum base-emitter resistor, R , can now be
BL
calculated as:
EL7585A
R
_min = V _max/(I_DRVL_min - Ic/Hfe_min) =
BE
BL
1.25V/(8mA - 500mA/100) = 417Ω
FIGURE 22. CASCADED MOSFET TOPOLOGY FOR HIGH
OUTPUT VOLTAGE APPLICATIONS
This is the minimum value that can be used - so, we now
choose a convenient value greater than this minimum value;
say 500Ω. Larger values may be used to reduce quiescent
current, however, regulation may be adversely affected, by
Linear-Regulator Controllers (V , V
OFF
The EL7585A includes three independent linear-regulator
controllers, in which two are positive output voltage (V
, and
ON LOGIC
V
)
supply noise if R is made too high in value.
BL
ON
, and
and V
LOGIC
), and one is negative. The V , V
V
LOGIC
ON OFF
linear-regulator controller functional diagrams,
BOOST
LX
V
0.1µF
applications circuits are shown in Figures 23, 24, and 25
respectively.
LDO_ON
0.9V
Calculation of the Linear Regulator Base-Emitter
PG_LDOP
CP (TO 36V)
0.1µF
+
-
36V
ESD
Resistors (R , R
and R
)
BN
BL BP
CLAMP
R
BP
7kΩ
For the pass transistor of the linear regulator, low frequency
Q3
gain (Hfe) and unity gain freq. (f ) are usually specified in the
T
DRVP
FBP
V
(TO 35V)
ON
datasheet. The pass transistor adds a pole to the loop
R
R
P1
P2
transfer function at f =f /Hfe. Therefore, in order to maintain
p
T
C
ON
phase margin at low frequency, the best choice for a pass
device is often a high frequency low gain switching
+
-
20kΩ
transistor. Further improvement can be obtained by adding a
GMP
base-emitter resistor R (R , R , R
in the Functional
BE BP BL BN
Block Diagram), which increase the pole frequency to:
1: Np
f =f *(1+ Hfe *re/R )/Hfe, where re=KT/qIc. So choose the
p
T
BE
lowest value R in the design as long as there is still
BE
FIGURE 23. V
FUNCTIONAL BLOCK DIAGRAM
enough base current (I ) to support the maximum output
B
current (I ).
C
ON
We will take as an example the V
Fairchild FMMT549 PNP transistor is used as the external
pass transistor, Q5 in the application diagram, then for a
linear regulator. If a
LOGIC
maximum V
operating requirement of 500mA the data
LOGIC
sheet indicates Hfe_min = 100.
FN7523.2
September 21, 2005
11
EL7585A
consists of an external diode-capacitor charge pump
LX
powered from the inductor (LX) of the boost converter,
followed by a low dropout linear regulator (LDO_OFF). The
LDO_OFF regulator uses an external NPN transistor as the
pass element. The onboard LDO controller is a wide band
(>10MHz) transconductance amplifier capable of 4mA drive
current, which is sufficient for up to 40mA or more output
current under the low dropout condition (forced beta of 10).
0.1µF
CP (TO -26V)
0.1µF
LDO_OFF
V
REF
PG_LDON
0.4V
-
+
R
N2
20kΩ
Typical V
voltage supported by EL7585A ranges from
OFF
FBN
-5V to -20V. A fault comparator is also included for
monitoring the output voltage. The undervoltage threshold is
set at 200mV above the 0.2V reference level.
1: Nn
R
N1
V
(TO -20V)
OFF
The V
power supply is used to power the logic circuitry
LOGIC
-
+
DRVN
within the LCD panel. The DC-DC may be powered directly
from the low voltage input, 3.3V or 5.0V, or it may be
powered through the fault protection switch. The
C
Q2
OFF
GMN
R
BN
36V
ESD
CLAMP
3kΩ
LDO_LOGIC regulator uses an external PNP transistor as
the pass element. The onboard LDO controller is a wide
band (>10MHz) transconductance amplifier capable of
16mA drive current, which is sufficient for up to 160mA or
more output current under the low dropout condition (forced
FIGURE 24. V
FUNCTIONAL BLOCK DIAGRAM
OFF
V
OR V
PROT
IN
(3V TO 6V)
beta of 10). Typical V
voltage supported by EL7585A
LOGIC
ranges from +1.3V to V -0.2V. A fault comparator is also
DD
LDO_LOG
0.9V
PG_LDOL
included for monitoring the output voltage. The undervoltage
threshold is set at 25% below the 1.2V reference.
R
BL
500Ω
+
-
Set-Up Output Voltage
Refer to the Typical Application Diagram, the output voltages
Q5
V
LOGIC
(1.3V TO 3.6V)
DRVL
C
of V , V
, and V
are determined by the following
LOG
ON OFF
LOGIC
R
R
10µF
L1
L2
equations:
FBL
R
R
12
V
= V
× 1 + ---------
ON
REF
-
+
11
20kΩ
GML
R
R
22
---------
V
= V
+
× (V
– V
REF
)
1: N1
OFF
REFN
REFN
21
R
R
42
V
= V
× 1 + ---------
FIGURE 25. V
FUNCTIONAL BLOCK DIAGRAM
LOGIC
REF
LOGIC
41
The V
ON
power supply is used to power the positive supply
Where V
= 1.2V, V
= 0.2V.
REF
REFN
of the row driver in the LCD panel. The DC-DC consists of an
external diode-capacitor charge pump powered from the
inductor (LX) of the boost converter, followed by a low
dropout linear regulator (LDO_ON). The LDO_ON regulator
uses an external PNP transistor as the pass element. The
onboard LDO controller is a wide band (>10MHz)
Resistor networks in the order of 250kΩ, 120kΩ and 10kΩ
are recommended for V , V
ON OFF
and V
, respectively.
, single or
LOGIC
Charge Pump
To generate an output voltage higher than V
multiple stages of charge pumps are needed. The number of
stage is determined by the input and output voltage. For
positive charge pump stages:
BOOST
transconductance amplifier capable of 4mA drive current,
which is sufficient for up to 40mA or more output current
under the low dropout condition (forced beta of 10). Typical
V
voltage supported by EL7585A ranges from +15V to
ON
V
+ V
– V
CE INPUT
OUT
-------------------------------------------------------------
≥
N
+36V. A fault comparator is also included for monitoring the
output voltage. The under-voltage threshold is set at 25%
below the 1.2V reference.
POSITIVE
V
– 2 × V
INPUT
F
where V
CE
is the dropout voltage of the pass component of
the linear regulator. It ranges from 0.3V to 1V depending on
The V
OFF
power supply is used to power the negative
supply of the row driver in the LCD panel. The DC-DC
FN7523.2
12
September 21, 2005
EL7585A
the transistor. V is the forward-voltage of the charge pump
Discontinuous/Continuous Boost Operation and
its Effect on the Charge Pumps
F
rectifier diode.
The EL7585A V
and V architecture uses LX switching
ON
OFF
The number of negative charge pump stages is given by:
edges to drive diode charge pumps from which LDO
regulators generate the V and V supplies. It can be
V
V
+ V
CE
OUTPUT
------------------------------------------------
≥
N
ON
OFF
NEGATIVE
– 2 × V
INPUT
F
appreciated that should a regular supply of LX switching
edges be interrupted, for example during discontinuous
To achieve high efficiency and low material cost, the lowest
number of charge pump stages which can meet the above
requirements, is always preferred.
operation at light A
boost load currents, then this may
affect the performance of V and V regulation -
VDD
ON
OFF
depending on their exact loading conditions at the time.
High Charge Pump Output Voltage (>36V)
Applications
To optimize V /V
regulation, the boundary of
ON OFF
discontinuous/continuous operation of the boost converter
can be adjusted, by suitable choice of inductor given V
In the applications where the charge pump output voltage is
over 36V, an external npn transistor need to be inserted into
between DRVP pin and base of pass transistor Q3 as shown
in Figure 26; or the linear regulator can control only one
stage charge pump and regulate the final charge pump
output as shown in Figure 27.
,
IN
current loading, to
V
, switching frequency and the A
OUT VDD
be in continuous operation.
The following equation gives the boundary between
discontinuous and continuous boost operation. For
continuous operation (LX switching every clock cycle) we
require that:
CHARGE PUMP
V
IN
OUTPUT
OR A
VDD
I(A
_load) > D*(1-D)*V /(2*L*F
IN
)
OSC
VDD
7kΩ
where the duty cycle, D = (A
VDD
- V )/A
IN VDD
Q3
DRVP
FBP
NPN
For example, with V = 5V, F
IN OSC
12V we find continuous operation of the boost converter can
be guaranteed for:
= 1.0MHz and A
=
VDD
CASCODE
V
ON
TRANSISTOR
EL7585A
L = 10µH and I(A
) > 61mA
VDD
L = 6.8µH and I(A
L = 3.3µH and I(A
) > 89mA
VDD
) > 184mA
VDD
Charge Pump Output Capacitors
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:
FIGURE 26. CASCODE NPN TRANSISTOR CONFIGURATION
FOR HIGH CHARGE PUMP OUTPUT VOLTAGE
(>36V)
I
OUT
LX
------------------------------------------------------
C
≥
OUT
2 × V
× f
OSC
RIPPLE
0.1µF
where f
is the switching frequency.
A
OSC
VDD
0.1µF
Start-Up Sequence
7kΩ
Figure 28 shows a detailed start-up sequence waveform. For
0.1µF
0.1µF
a successful power-up, there should be six peaks at V
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
.
CDLY
DRVP
FBP
Q3
V
ON
0.47µF
(>36V)
0.1µF
EL7585A
When the input voltage (V ) exceeds 2.5V, V
and
REF
DD
V
turn on. At the same time, if EN is tied to V , an
DD
LOGIC
0.22µF
internal current source starts to charge C
to an upper
DLY
threshold using a fast ramp followed by a slow ramp. If EN is
low at this point, the C
goes high.
ramp will be delayed until EN
DLY
FIGURE 27. THE LINEAR REGULATOR CONTROLS ONE
STAGE OF CHARGE PUMP
The first four ramps on C
(two up, two down) are used to
initialize the fault protection switch and to check whether
DLY
FN7523.2
September 21, 2005
13
EL7585A
there is a fault condition on C
DLY
or V
. If a fault is
C
has an internal current-limited clamp to keep the
REF
INT
voltage within its normal range. If C
detected, the outputs and the input protection will turn off,
but V will stay on. If no fault is found, C continues
is shorted low, the
INT
boost regulator will attempt to regulate to 0V. If C
shorted H, the regulator switches to P mode.
is
REF
ramping up and down.
CDLY
INT
During the second ramp, the device checks the status of
and over temperature. At the peak of the second ramp,
PG output goes low and enables the input protection PMOS
Q1. Q1 is a controlled FET used to prevent in-rush current into
If any of the regulated outputs (V
LOGIC
circuitry will switch off until the output returns to its expected
value.
, V , V
or
BOOST ON OFF
V
V
) are driven above their target levels the drive
REF
V
before V is enabled internally. Its rate of turn
BOOST
BOOST
If V
BOOST
is excessively loaded, the current limit will
on is controlled by C . When a fault is detected, M1 will turn
o
prevent damage to the chip. While in current limit, the part
acts like a current source and the regulated output will drop.
If the output drops below the fault threshold, a ramp will be
off and disconnect the inductor from V .
IN
With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~V . Initially the boost is not
initiated on C
and, provided that the fault is sustained,
IN
DELAY
enabled so V
rises to V -V
IN DIODE
through the output
the chip will be disabled on completion of the ramp.
BOOST
diode. Hence, there is a step at V
during this part of the
BOOST
In some circumstances, (depending on ambient temperature
and thermal design of the board), continuous operation at
current limit may result in the over-temperature threshold
being exceeded, which will cause the part to disable
immediately.
start-up sequence. If this step is not desirable, an external
PMOS FET can be used to delay the output until the boost is
enabled internally. The delayed output appears at A
.
VDD
For EL7585A, V
soft-start at the beginning of the third
DLY
of 220nF, the soft-start time is ~2ms.
BOOST
ramp. The soft-start ramp depends on the value of the C
All I/O also have ESD protection, which in many cases will
also provide overvoltage protection, relative to either ground
capacitor. For C
DLY
V
turns on at the start of the fourth peak. At the fifth
or V . However, these will not generally operate unless
OFF
peak, DELB gate goes low to turn on the external PMOS Q4
to generate a delayed V output.
DD
abs max ratings are exceeded.
BOOST
Component Selection for Start-Up Sequencing and
Fault Protection
V
is enabled at the beginning of the sixth ramp. A
OFF ON
,
ON
PG, V
VDD
are checked at end of this ramp.
, DELB and V
The C
capacitor is typically set at 220nF and is required
to stabilize the V output. The range of C is from
REF
REF
22nF to 1µF and should not be more than five times the
capacitor on C to ensure correct start-up operation.
REF
Fault Protection
During the startup sequence, prior to BOOST soft-start,
is checked to be within ±20% of its final value and the
DEL
capacitor is typically 220nF and has a usable
V
REF
device temperature is checked. If either of these are not
within the expected range, the part is disabled until the
power is recycled or EN is toggled.
The C
DEL
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching µA levels.
If C
DELAY
is shorted low, then the sequence will not start,
C
should be at least 1/5 of the value of C
(See
the fault time-out will be
DEL
DEL
above). Note with 220nF on C
REF
while if C
is shorted H, the first down ramp will not
DELAY
occur and the sequence will not complete.
typically 50ms and the use of a larger/smaller value will vary
this time proportionally (e.g. 1µF will give a fault time-out
period of typically 230ms).
Once the start-up sequence is completed, the chip
continuously monitors C
, DELB, FBP, FBL, FBN, V ,
DLY
REF
FBB and PG and checks for faults. During this time, the
voltage on the C capacitor remains at 1.15V until either a
Fault Sequencing
The EL7585A has an advanced fault detection system which
protects the IC from both adjacent pin shorts during
operation and shorts on the output supplies.
DLY
fault is detected, or the EN pin is pulled low.
A fault on C , V or temperature will shut down the
DELAY REF
chip immediately. If a fault on any other output is detected,
will ramp up linearly with a 5µA (typical) current to
A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the layout guidelines
and component selection sections to avoid problems during
initial evaluation and prototype PCB generation.
C
DELAY
the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
the voltage on the C
capacitor returns to 1.15V.
DLY
Typical fault thresholds for FBP, FBL, FBN and FBB are
included in the tables. PG and DELB fault thresholds are
typically 0.6V.
FN7523.2
14
September 21, 2005
EL7585A
V
CDLY
V
IN
EN
V
REF
V
BOOST
t
ON
t
OS
V
LOGIC
V
OFF
t
DEL1
DELAYED
V
BOOST
t
DEL2
V
t
ON
DEL3
START-UP SEQUENCE
TIMED BY C
DLY
FIGURE 28. START-UP SEQUENCE
FN7523.2
15
September 21, 2005
EL7585A
6. The exposed die plate, on the underneath of the
Over-Temperature Protection
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of 140°C, the device will shut
down.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
Layout Recommendation
The device's performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
connections for feedback resistor networks (R , R
,
1
11
R
) and the V
capacitor, C , the C
22 DELAY
capacitor
41
REF
C and the integrator capacitor C
.
23
7
2. Place V
and V
bypass capacitors close to the pins.
REF
DD
9. Minimize feedback input track lengths to avoid switching
3. Minimize the length of traces carrying fast signals and
noise pick-up.
high current.
A two-layer demo board is available to illustrate the proper
layout implementation. A four-layer demo board can be used
to further optimize the layout recommendations.
4. All feedback networks should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point near the main
decoupling capacitors.
Demo Board Layout
FIGURE 29. TOP LAYER
FIGURE 30. BOTTOM LAYER
FN7523.2
16
September 21, 2005
EL7585A
Typical Application Diagram
LX
A
VDD
(12V)
L
D
1
1
Q
NODE 1
Q
4
1
V
IN
C
0.1µF
9
C
1nF
C
6.8µH
0
1
C
10µF
X2
R
1MΩ
C
2
9
16
22nF
46.5kΩ
R
2
10µF
x2
PG
LX
FBB
R
C
OPEN
7
R
1
R
10kΩ
8
C
7
5kΩ
OPEN
7
CDELAY
C
10
0.22µF
4.7µF
DELB
CINT
R
10Ω
6
6
7
VDD
LX
R
10
4.7nF
1nF
C
23
C
R
4.7µF
10kΩ
10kΩ
C
P
C
0.1µF
C
11
13
0.1µF
EN
R
13
V
0.1µF
REF
C
41
C
C
14
0.1µF
12
0.1µF
7kΩ
NODE 1
VREF
C
D
D
D
11
22
0.1µF
12
21
R
DRVP
FBP
Q
Q
43
3
V
ON
(15V)
R
230kΩ
12
500Ω
R
C
15
11
20kΩ
C
24
Q
DRVL
FBL
5
0.47µF
R
LX
42
V
LOGIC
(2.5V)
0.1µF
R
41
5kΩ
C
5.4kΩ
31
4.7µF
R
23
C
25
0.1µF
3kΩ
DRVN
FBN
V
2
OFF
(-5V)
R
104K
22
R
C
21
20K
20
4.7µF
SGND
PGND
V
REF
NOTE: The SGND should be connected to the exposed die plate and connected to the PGND at one point only.
FN7523.2
September 21, 2005
17
EL7585A
QFN Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7523.2
18
September 21, 2005
相关型号：
EL7585ILZ
3.5A SWITCHING REGULATOR, 1100kHz SWITCHING FREQ-MAX, QCC20, 4 X 4 MM, ROHS COMPLIANT, MO-220, QFN-20
RENESAS
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