HA3-5330-5 [INTERSIL]
650ns Precision Sample and Hold Amplifier; 650ns精密采样保持放大器
| 型号： | HA3-5330-5 |
| 厂家： | 
Intersil |
| 描述： | 650ns Precision Sample and Hold Amplifier |
| 文件： | 总5页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5330
Data Sheet
September 1998
File Number 2858.3
650ns Precision Sample and Hold
Amplifier
Features
• Very Fast Acquisition . . . . . . 500ns (0.1%) 650ns (0.01%)
• Low Droop Rate . . . . . . . . . . . . . . . . . . . . . . . . 0.01µV/µs
• Very Low Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2mV
• High Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90V/µs
• Wide Supply Range. . . . . . . . . . . . . . . . . . . . . ±10V to ±20V
• Internal Hold Capacitor
The HA-5330 is a very fast sample and hold amplifier
designed primarily for use with high speed A/D converters. It
utilizes the Intersil Dielectric Isolation process to achieve a
650ns acquisition time to 12-bit accuracy and a droop rate of
0.01µV/µs. The circuit consists of an input transconductance
amplifier capable of producing large amounts of charging
current, a low leakage analog switch, and an integrating
output stage which includes a 90pF hold capacitor.
• Fully Differential Input
The analog switch operates into a virtual ground, so charge
injection on the hold capacitor is constant and independent
• TTL/CMOS Compatible
of V . Charge injection is held to a low value by
Applications
IN
compensation circuits and, if necessary, the resulting 0.5mV
hold step error can be adjusted to zero via the Offset Adjust
terminals. Compensation is also used to minimize leakage
currents which cause voltage droop in the Hold mode.
• Precision Data Acquisition Systems
• D/A Converter Deglitching
• Auto-Zero Circuits
The HA-5330 will operate at reduced supply voltages (to
±10V) with a reduced signal range. The MIL-STD-883 data
sheet for this device is available on request.
• Peak Detectors
Functional Diagram
OFFSET
ADJUST
Ordering Information
V+
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
3
4
10
90pF
HA-5330
HA1-5330-2
HA1-5330-5
HA3-5330-5
-55 to 125 14 Ld CERDIP
F14.3
0 to 75
0 to 75
14 Ld CERDIP
14 Ld PDIP
F14.3
E14.3
14
1
- IN
+IN
7
OUT
Pinout
8
S/H
CONTROL
HA-5330
(PDIP, CERDIP)
TOP VIEW
12
11
5
V-
SUPPLY
GND
SIGNAL
GND
+IN
NC
1
2
3
4
5
6
7
14 -IN
13 NC
OFFSET ADJ.
OFFSET ADJ.
V-
12 SIGNAL GND
11 SUPPLY GND
10 V+
NC
9
8
NC
S/H CONTROL
OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
HA-5330
Absolute Maximum Ratings
Thermal Information
o
o
Voltage between V+ and SUPPLY/SIG GND. . . . . . . . . . . . . . +20V
Voltage between V- and SUPPLY/SIG GND . . . . . . . . . . . . . . . -20V
Voltage between SUPPLY GND and SIG GND . . . . . . . . . . . . ±2.0V
Voltage between S/H Control and SUPPLY/SIG GND. . . . +8V, -6V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V
Output Current, Continuous (Note 1). . . . . . . . . . . . . . . . . . . ±17mA
Thermal Resistance (Typical, Note 3)
CERDIP Package. . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
66
90
16
N/A
o
Maximum Junction Temperature (Ceramic Package, Note 2) . . .175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
o
o
Operating Conditions
Temperature Range
HA-5330-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HA-5330-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
o
o
o
o
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . ±10V to ±20V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Internal Power Dissipation may limit Output Current below ±17mA.
o
2. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175 C for the ceramic package,
o
and below 150 C for the plastic package.
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= ±15V; S/H Control V = +0.8V (Sample): V = +2.0V (Hold); SIG GND = SUPPLY GND,
IL IH
SUPPLY
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified
HA-5330-2
HA-5330-5
TYP
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance (Note 4)
Input Capacitance
MIN
TYP
MAX
MIN
MAX
UNITS
Full
25
±10
-
15
3
-
±10
-
15
3
-
V
5
-
5
-
MΩ
pF
25
-
-
-
-
Offset Voltage
25
-
0.2
-
-
-
0.2
-
-
mV
mV
Full
Full
25
-
2.0
-
1.5
o
Offset Voltage Temperature Coefficient
Bias Current
-
1
10
-
1
10
µV/ C
-
-
±20
-
-
-
-
±20
-
-
nA
nA
nA
nA
V
Full
25
±500
±300
Offset Current
-
20
-
-
-
20
-
-
Full
Full
Full
-
500
-
300
Common Mode Range
CMRR
±10
86
-
-
-
±10
86
-
-
-
V
= ±10V
100
100
dB
CM
TRANSFER CHARACTERISTICS
Gain
6
7
6
7
DC
Full
25
2 x 10
-
2 x 10
-
-
2 x 10
-
2 x 10
-
-
V/V
Gain Bandwidth Product
OUTPUT CHARACTERISTICS
Output Voltage
Note 12
4.5
4.5
MHz
Full
Full
25
±10
-
-
±10
-
-
V
mA
MHz
Ω
Output Current
±10
-
-
±10
-
-
Full Power Bandwidth (Note 6)
Output Resistance
-
-
-
1.4
0.2
-
-
-
-
-
1.4
0.2
-
-
Hold Mode
25
-5
-5
Sample Mode
25
10
0.001
10
0.001
Ω
2
HA-5330
Electrical Specifications
V
= ±15V; S/H Control V = +0.8V (Sample): V = +2.0V (Hold); SIG GND = SUPPLY GND,
SUPPLY
IL
IH
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified (Continued)
HA-5330-2
TYP
HA-5330-5
TYP
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
MIN
MAX
MIN
MAX
UNITS
Total Output Noise, DC to 4MHz
Sample Mode
-
-
230
-
-
-
-
230
-
-
µV
µV
RMS
RMS
Hold Mode
25
190
190
TRANSIENT RESPONSE
Rise Time
Note 5
Note 5
Note 7
25
25
25
-
-
-
70
10
90
-
-
-
-
-
-
70
10
90
-
-
-
ns
%
Overshoot
Slew Rate
V/µs
DIGITAL INPUT CHARACTERISTICS
Input Voltage
V
V
V
V
Full
Full
Full
Full
2.0
-
-
2.0
-
-
V
V
IH
IL
IL
IH
-
-
-
-
0.8
40
40
-
-
-
-
0.8
40
40
Input Current
= 0V
= 5V
10
10
10
10
µA
µA
SAMPLE/HOLD CHARACTERISTICS
Acquisition Time
To 0.1%, Note 8
To 0.01%, Note 8
25
Full
25
-
500
-
-
-
500
-
-
ns
ns
-
700
-
700
-
650
-
-
-
650
-
-
ns
Full
25
-
900
-
900
ns
Aperture Time (Note 4)
Effective Aperture Delay Time
Aperture Uncertainty
-
20
-
-
20
-
ns
25
-50
-25
0.1
0.01
-
0
-50
-25
0.1
0.01
-
0
ns
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
Droop Rate (Note 9)
25
-
100
-
µV/µs
µV/µs
mV
ns
Full
25
10
-
Hold Step Error
Note 10
0.5
100
-88
0.5
100
-88
Hold Mode Settling Time
Hold Mode Feedthrough
POWER SUPPLY CHARACTERISTICS
Positive Supply Current
Negative Supply Current
Power Supply Rejection
NOTES:
To 0.01%
25
200
-
200
-
20V
, 100kHz
P-P
Full
dB
Full
Full
Full
-
-
18
19
22
23
-
-
-
18
19
24
25
-
mA
mA
dB
Note 11
86
100
86
100
4. Derived from computer simulation only; not tested.
5. V = 200mV Step; R = 2kΩ; C = 50pF.
I
L
L
Slew Rate
6. Full power bandwidth based on slew rate measurement using: FPBW = --------------------------- . Distortion of wave shape occurs beyond 100kHz due to
2πV
PEAK
slew rate enhancement circuitry.
7. V = 20V Step; R = 2kΩ; C = 50pF.
O
L
L
8. V = 10V Step; R = 2kΩ; C = 50pF.
O
L
L
9. This parameter is measured at ambient temperature extremes in a high speed test environment. Consequently, steady state heating effects from
internal power dissipation are not included.
10. V = 0V; V = +3.5V; t = 22ns (V to V ). See graph.
IN IH IL IH
R
11. Based on a 3V delta in each supply, i.e. 15V ±1.5V
.
DC
12. V
OUT
= 200mV , R = 2kΩ, C = 50pF.
P-P L L
3
HA-5330
Output Stage
Application Information
The HA-5330 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load
current which occur during an A/D conversion are absorbed
at the S/H output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output is not
designed to tolerate a short of indefinite duration.
The HA-5330 has the uncommitted differential inputs of an
op amp, allowing the Sample/Hold function to be combined
with many conventional op amp circuit ideas. See the Intersil
Application Note AN517 for a collection of circuit ideas.
Layout
A printed circuit board with ground plane is recommended
for best performance. Bypass capacitors (0.01µF to 0.1µF,
ceramic) should be provided from each power supply
terminal to the Supply GND Terminal on pin 11.
Glossary of Terms
Acquisition Time
The time required following a “sample” command, for the
output to reach its final value within ±0.1% or ±0.01%. This is
the minimum sample time required to obtain a given
accuracy, and includes switch delay time, slewing time and
settling time.
Typical Applications
The HA-5330 is configured as a unity gain noninverting
amplifier by simply connecting the output (pin 7) to the
inverting input (pin 14). As an input device for a fast
successive - approximation A/D converter, it offers an
extremely high throughput rate. Also, the HA-5330’s
pedestal error is adjustable to zero by using an Offset Adjust
potentiometer (10K to 50K) center tapped to V-.
Aperture Time
The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is that interval
between the conditions of 10% open and 90% open.
V-
10kΩ - 50kΩ
Hold Step Error
Hold step error is the output shift due to charge transfer from
the sample to the hold mode. It is also referred to as “offset
step” or “pedestal error”.
3
4
3.0
2.0
FIGURE 1. HA-5330 OFFSET ADJUST
The ideal ground connections are pin 11 (Supply Ground)
directly to the system Supply Common, and pin 12 (Signal
Ground) directly to the system Signal Ground (Analog
Ground).
1.0
0.0
-1.0
-2.0
Hold Capacitor
20
40
60
80
100
The HA-5330 includes a 90pF MOS hold capacitor, sufficient
for most high speed applications (the Electrical
Specifications section is based on the internal capacitor).
RISE TIME (ns) 0V TO 3.5V
FIGURE 3. HOLD STEP ERROR vs S/H CONTROL RISE TIME
Effective Aperture Delay Time (EADT)
MAGNITUDE
40
The difference between the digital delay time from the Hold
command to the opening of the S/H switch, and the
propagation time from the analog input to the switch.
20
EADT may be positive, negative or zero. If zero, the S/H
PHASE
0
-20
-40
amplifier will output a voltage equal to V at the instant the
Hold command was received. For negative EADT, the output
in Hold (exclusive of pedestal and droop errors) will
0
IN
±15V SUPPLIES
90
180
correspond to a value of V that occurred before the Hold
IN
command.
±12V SUPPLIES
Aperture Uncertainty
1K
10K
100K
FREQUENCY (Hz)
1M
10M
The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay Uncertainty,
Aperture Time Jitter, etc.) sets a limit on the accuracy with
which a waveform can be reconstructed from sample data.
FIGURE 2. MAGNITUDE AND PHASE RESPONSE
(CLOSED LOOP GAIN = 100)
4
HA-5330
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Type: Nitride (Si N ) over Silox (SiO , 5% Phos.)
99 mils x 166 mils x 19 mils
3
4
2
2510µm x 4210µm x 483µm
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
METALLIZATION:
SUBSTRATE POTENTIAL (Powered Up):
Type: Al, 1% Cu
Signal GND
Thickness: 16kÅ ±2kÅ
TRANSISTOR COUNT:
205
PROCESS:
Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5330
-IN
+IN
SIGNAL GND
SUPPLY GND
V+
OFFSET ADJ
OFFSET ADJ
V-
S/H CONTROL
OUTPUT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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