HA9P5020-5ZX96 [INTERSIL]
100MHz Current Feedback Video Amplifier With Disable; 100MHz的电流反馈视频放大器具有禁用
| 型号： | HA9P5020-5ZX96 |
| 厂家： | 
Intersil |
| 描述： | 100MHz Current Feedback Video Amplifier With Disable |
| 文件： | 总23页 (文件大小：565K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5020
®
Data Sheet
June 5, 2006
FN2845.11
100MHz Current Feedback
Video Amplifier With Disable
Features
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800V/µs
• Output Current . . . . . . . . . . . . . . . . . . . . . . . ±30mA (Min)
• Drives 3.5V into 75Ω
The HA-5020 is a wide bandwidth, high slew rate amplifier
optimized for video applications and gains between 1 and
10. Manufactured on Intersil’s Reduced Feature
Complementary Bipolar DI process, this amplifier uses
current mode feedback to maintain higher bandwidth at a
given gain than conventional voltage feedback amplifiers.
Since it is a closed loop device, the HA-5020 offers better
gain accuracy and lower distortion than open loop buffers.
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03%
• Differential Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . .0.03°
• Low Input Voltage Noise . . . . . . . . . . . . . . . . . 4.5nV/√Hz
• Low Supply Current . . . . . . . . . . . . . . . . . . . . 10mA (Max)
• Wide Supply Range . . . . . . . . . . . . . . . . . . . ±5V to ±15V
• Output Enable/Disable
The HA-5020 features low differential gain and phase and
will drive two double terminated 75Ω coax cables to video
levels with low distortion. Adding a gain flatness
performance of 0.1dB makes this amplifier ideal for
demanding video applications. The bandwidth and slew rate
of the HA-5020 are relatively independent of closed loop
gain. The 100MHz unity gain bandwidth only decreases to
60MHz at a gain of 10. The HA-5020 used in place of a
conventional op amp will yield a significant improvement in
the speed power product. To further reduce power, HA-5020
has a disable function which significantly reduces supply
current, while forcing the output to a true high impedance
state. This allows the outputs of multiple amplifiers to be
wire-OR’d into multiplexer configurations. The device also
includes output short circuit protection and output offset
voltage adjustment.
• High Performance Replacement for EL2020
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Unity Gain Video/Wideband Buffer
• Video Gain Block
• Video Distribution Amp/Coax Cable Driver
• Flash A/D Driver
• Waveform Generator Output Driver
• Current to Voltage Converter; D/A Output Buffer
• Radar Systems
For multi channel versions of the HA-5020 see the HA5022
dual with disable, HA5023 dual, HA5013 triple and HA5024
quad with disable op amp data sheets.
• Imaging Systems
Pinout
HA-5020
(PDIP, SOIC)
TOP VIEW
BAL
IN-
1
2
3
4
8
7
6
5
DISABLE
V+
-
+
IN+
V-
OUT
BAL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005-2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HA-5020
Ordering Information
PART NUMBER
PART MARKING
HA3-5020-5
HA3-5020-5Z
TEMP. RANGE (°C)
0 to 75
PACKAGE
PKG. DWG. #
E8.3
HA3-5020-5
8 Ld PDIP
HA3-5020-5Z (Note)
HA9P5020-5
0 to 75
8 Ld PDIP (Pb-free)
8 Ld SOIC
E8.3
50205
0 to 75
M8.15
M8.15
M8.15
M8.15
HA9P5020-5Z (Note)
HA9P5020-5X96
HA9P5020-5ZX96 (Note)
50205Z
50205
0 to 75
8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel
0 to 75
50205Z
0 to 75
8 Ld SOIC Tape and Reel
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN2845.11
June 5, 2006
2
HA-5020
Absolute Maximum Ratings (Note 1)
Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 36V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
Thermal Resistance (Typical, Note 2)
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
θ
(°C/W)
120
165
θ
(°C/W)
N/A
N/A
JA
JC
SUPPLY
Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected
Maximum Junction Temperature (Plastic Packages, Note 1) . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range
HA-5020-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 150°C for plastic packages.
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications
V
= ±15V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF,
SUPPLY
F
V
L
L
Unless Otherwise Specified
TEMP.
(°C)
PARAMETER
INPUT CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Offset Voltage (Notes 3, 14)
25
Full
Full
25
-
-
2
-
8
10
-
mV
mV
Average Input Offset Voltage Drift
-
10
-
µV/°C
dB
V
Common Mode Rejection Ratio (Note 14)
V
= ±10V
CM
60
50
64
60
-
-
IO
Full
25
-
-
dB
V
Power Supply Rejection Ratio (Note 14)
±4.5V ≤ V ≤ ±18V
-
-
dB
IO
S
Full
25
-
-
dB
Non-Inverting Input (+IN) Current (Note 14)
+IN Common Mode Rejection
+IN Power Supply Rejection
3
-
8
µA
Full
25
-
20
0.1
0.5
0.06
0.2
20
50
0.4
0.5
0.2
0.5
µA
V
= ±10V
-
-
µA/V
µA/V
µA/V
µA/V
µA
CM
Full
25
-
-
±4.5V ≤ V ≤ ±18V
-
-
S
Full
25
-
-
Inverting Input (-IN) Current (Note 14)
-IN Common Mode Rejection
-
12
25
-
Full
25
-
µA
V
= ±10V
-
µA/V
µA/V
µA/V
µA/V
CM
Full
25
-
-
-IN Power Supply Rejection
±4.5V ≤ V ≤ ±18V
-
-
S
Full
-
-
TRANSFER CHARACTERISTICS
Transimpedance (Notes 9, 14)
25
Full
25
3500
1000
70
-
-
-
-
-
-
-
-
-
-
-
-
V/mA
V/mA
dB
Open Loop DC Voltage Gain (Note 9)
Open Loop DC Voltage Gain
R = 400Ω,
L
V
= ±10V
OUT
Full
25
65
dB
R
= 100Ω,
60
dB
L
V
= ±2.5V
OUT
Full
55
dB
FN2845.11
June 5, 2006
3
HA-5020
Electrical Specifications
V
= ±15V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF,
SUPPLY
F
V
L
L
Unless Otherwise Specified (Continued)
TEMP.
(°C)
PARAMETER
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 14)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
R
= 150Ω
25 to 85
-40 to 0
25
±12
±11
±12.7
±11.8
±31.7
-
-
-
-
-
V
V
L
Output Current (Guaranteed by Output Voltage Test)
±30
mA
mA
Full
±27.5
POWER SUPPLY CHARACTERISTICS
Quiescent Supply Current (Note 14)
Supply Current, Disabled (Note 14)
Disable Pin Input Current
Full
Full
Full
Full
Full
-
7.5
5
10
7.5
1.5
-
mA
mA
mA
µA
DISABLE = 0V
DISABLE = 0V
-
-
350
-
1.0
-
Minimum Pin 8 Current to Disable (Note 4)
Maximum Pin 8 Current to Enable (Note 5)
-
20
µA
AC CHARACTERISTICS (A = +1)
V
Slew Rate (Note 6)
25
Full
25
600
800
700
12.7
11.1
5
-
-
-
-
-
-
-
-
-
-
V/µs
V/µs
MHz
MHz
ns
500
Full Power Bandwidth (Note 7)
(Guaranteed by Slew Rate Test)
9.6
Full
25
8.0
Rise Time (Note 8)
-
-
-
-
-
-
Fall Time (Note 8)
25
5
ns
Propagation Delay (Notes 8, 14)
-3dB Bandwidth (Note 14)
Settling Time to 1%
25
6
ns
V
= 100mV
25
100
45
MHz
ns
OUT
10V Output Step
10V Output Step
25
Settling Time to 0.25%
25
100
ns
AC CHARACTERISTICS (A = +10, R = 383Ω)
V
F
Slew Rate (Notes 6, 9)
25
Full
25
900
1100
-
-
-
-
-
-
-
-
-
-
-
V/µs
V/µs
MHz
MHz
ns
700
Full Power Bandwidth (Note 7)
(Guaranteed by Slew Rate Test)
14.3
17.5
-
Full
25
11.1
Rise Time (Note 8)
-
-
-
-
-
-
8
Fall Time (Note 8)
25
8
ns
Propagation Delay (Notes 8, 14)
-3dB Bandwidth
25
9
ns
V
= 100mV
25
60
55
90
MHz
ns
OUT
Settling Time to 1%
Settling Time to 0.1%
10V Output Step
10V Output Step
25
25
ns
INTERSIL VALUE ADDED SPECIFICATIONS
Input Noise Voltage (Note 14)
f = 1kHz
f = 1kHz
f = 1kHz
25
25
-
4.5
2.5
25
-
-
-
-
-
-
nV/√Hz
pA/√Hz
pA/√Hz
V
+Input Noise Current (Note 14)
-Input Noise Current (Note 14)
Input Common Mode Range
-
-
25
Full
Full
25
±10
±25
-
±12
±40
7
-I
Adjust Range (Note 3)
µA
BIAS
Overshoot (Note 14)
%
FN2845.11
June 5, 2006
4
HA-5020
Electrical Specifications
V
= ±15V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF,
SUPPLY
F
V
L
L
Unless Otherwise Specified (Continued)
TEMP.
(°C)
PARAMETER
TEST CONDITIONS
MIN
±50
-
TYP
±65
-
MAX
UNITS
mA
Output Current, Short Circuit (Note 14)
Output Current, Disabled (Note 14)
V
= ±10V, V
OUT
= 0V
Full
Full
-
IN
DISABLE = 0V,
= ±10V
1
µA
V
OUT
Output Disable Time (Notes 10, 14)
Output Enable Time (Notes 11, 14)
Supply Voltage Range
25
25
25
25
-
-
10
200
-
-
µs
ns
V
-
±15
-
±5
-
Output Capacitance, Disabled (Note 12)
VIDEO CHARACTERISTICS
Differential Gain (Notes 13, 14)
Differential Phase (Notes 13, 14)
Gain Flatness
DISABLE = 0V
6
pF
R
R
= 150Ω
= 150Ω
25
25
25
-
-
-
0.03
0.03
0.1
-
-
-
%
°
L
L
To 5MHz
dB
Electrical Specifications V+ = +5V, V- = -5V, R = 1kΩ, A = +1, R = 400Ω, C ≤10pF, Unless Otherwise Specified.
F
V
L
L
Parameters are not tested. The limits are guaranteed based on lab characterizations, and reflect
lot-to-lot variation.
TEMP.
PARAMETER
INPUT CHARACTERISTICS
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
Input Offset Voltage (Notes 3, 14)
25
Full
Full
25
-
-
2
-
8
10
-
mV
mV
Average Input Offset Voltage Drift
-
10
-
µV/°C
dB
V
V
Common Mode Rejection Ratio (Notes 14, 15)
Power Supply Rejection Ratio (Note 14)
50
35
55
50
-
-
IO
Full
25
-
-
dB
±3.5V ≤ V ≤ ±6.5V
-
-
dB
IO
S
Full
25
-
-
dB
Non-Inverting Input (+IN) Current (Note 14)
+IN Common Mode Rejection (Note 15)
+IN Power Supply Rejection
3
-
8
µA
Full
25
-
20
0.1
0.5
0.06
0.2
20
50
0.4
0.5
0.2
0.5
µA
-
-
µA/V
µA/V
µA/V
µA/V
µA
Full
25
-
-
±3.5V ≤ V ≤ ±6.5V
-
-
S
Full
25
-
-
Inverting Input (-IN) Current (Note 14)
-IN Common Mode Rejection (Note 15)
-IN Power Supply Rejection
-
12
25
-
Full
25
-
µA
-
µA/V
µA/V
µA/V
µA/V
Full
25
-
-
±3.5V ≤ V ≤ ±6.5V
-
-
S
Full
-
-
TRANSFER CHARACTERISTICS
Transimpedance (Notes 9, 14)
25
Full
25
1000
850
65
-
-
-
-
-
-
-
-
V/mA
V/mA
dB
Open Loop DC Voltage Gain
R = 400Ω,
L
V
= ±2.5V
OUT
Full
60
dB
FN2845.11
June 5, 2006
5
HA-5020
Electrical Specifications V+ = +5V, V- = -5V, R = 1kΩ, A = +1, R = 400Ω, C ≤10pF, Unless Otherwise Specified.
F
V
L
L
Parameters are not tested. The limits are guaranteed based on lab characterizations, and reflect
lot-to-lot variation. (Continued)
TEMP.
PARAMETER
Open Loop DC Voltage Gain
TEST CONDITIONS
= 100Ω,
(°C)
MIN
50
TYP
MAX
UNITS
dB
R
V
25
-
-
-
-
L
= ±2.5V
OUT
Full
45
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 14)
25 to 85
-40 to 0
25
±2.5
±2.5
±3.0
±3.0
±20
±20
-
-
-
-
V
V
Output Current
(Guaranteed by Output Voltage Test)
R
= 100Ω
±16.6
±16.6
mA
mA
L
Full
POWER SUPPLY CHARACTERISTICS
Quiescent Supply Current (Note 14)
Supply Current, Disabled (Note 14)
Full
Full
Full
-
-
-
7.5
5
10
7.5
1.5
mA
mA
mA
DISABLE = 0V
DISABLE = 0V
1.0
Disable Pin Input Current
Minimum Pin 8 Current to Disable (Note 16)
Maximum Pin 8 Current to Enable (Note 5)
Full
Full
350
-
-
-
-
µA
µA
20
AC CHARACTERISTICS (A = +1)
V
Slew Rate (Note 17)
Full Power Bandwidth (Note 18)
Rise Time (Note 8)
25
25
25
25
25
25
25
25
25
215
400
28
6
-
-
-
-
-
-
-
-
-
V/µs
MHz
ns
22
-
Fall Time (Note 8)
-
6
ns
Propagation Delay (Note 8)
Overshoot
-
6
ns
-
4.5
125
50
75
%
-3dB Bandwidth (Note 14)
Settling Time to 1%
V
= 100mV
-
MHz
ns
OUT
2V Output Step
2V Output Step
-
Settling Time to 0.25%
-
ns
AC CHARACTERISTICS (A = +2, R = 681Ω)
V
F
Slew Rate (Note 17)
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
475
26
6
-
-
-
-
-
-
-
-
-
V/µs
MHz
ns
Full Power Bandwidth (Note 18)
Rise Time (Note 8)
Fall Time (Note 8)
6
ns
Propagation Delay (Note 8)
Overshoot
6
ns
12
95
50
100
%
-3dB Bandwidth (Note 14)
Settling Time to 1%
V
= 100mV
MHz
ns
OUT
2V Output Step
2V Output Step
Settling Time to 0.25%
ns
AC CHARACTERISTICS (A = +10, R = 383Ω)
V
F
Slew Rate (Note 17)
25
25
25
25
25
25
350
475
38
8
-
-
-
-
-
-
V/µs
MHz
ns
Full Power Bandwidth (Note 18)
Rise Time (Note 8)
28
-
Fall Time (Note 8)
-
9
ns
Propagation Delay (Note 8)
Overshoot
-
9
ns
-
1.8
%
FN2845.11
June 5, 2006
6
HA-5020
Electrical Specifications V+ = +5V, V- = -5V, R = 1kΩ, A = +1, R = 400Ω, C ≤10pF, Unless Otherwise Specified.
F
V
L
L
Parameters are not tested. The limits are guaranteed based on lab characterizations, and reflect
lot-to-lot variation. (Continued)
TEMP.
PARAMETER
-3dB Bandwidth (Note 14)
TEST CONDITIONS
= 100mV
(°C)
MIN
TYP
65
MAX
UNITS
MHz
ns
V
25
-
-
-
-
-
-
OUT
Settling Time to 1%
2V Output Step
2V Output Step
25
75
Settling Time to 0.25%
25
130
ns
INTERSIL VALUE ADDED SPECIFICATIONS
Input Noise Voltage (Note 14)
+Input Noise Current (Note 14)
-Input Noise Current (Note 14)
Input Common Mode Range
Output Current, Short Circuit
Output Current, Disabled (Note 14)
f = 1kHz
f = 1kHz
f = 1kHz
25
25
-
4.5
2.5
25
−
-
-
nV/√Hz
pA/√Hz
pA/√Hz
V
-
25
-
±2.5V
±40
-
-
Full
Full
Full
-
V
= ±2.5V, V
OUT
= 0V
±60
-
-
mA
IN
DISABLE = 0V,
= ±2.5V, V = 0V
2
µA
V
OUT
IN
Output Disable Time (Notes 14, 20)
Output Enable Time (Notes 14, 21)
Supply Voltage Range
25
25
25
25
-
-
40
40
-
-
µs
ns
V
-
±15
-
±5
-
Output Capacitance, Disabled (Note 19)
VIDEO CHARACTERISTICS
Differential Gain (Notes 13, 14)
Differential Phase (Notes 13, 14)
Gain Flatness
DISABLE = 0V
6
pF
R
R
= 150Ω
= 150Ω
25
25
25
-
-
-
0.03
0.03
0.1
-
-
-
%
°
L
L
To 5MHz
dB
NOTES:
2. Suggested V
Adjust Circuit: The inverting input current (-I
) can be adjusted with an external 10kΩ pot between pins 1 and 5, wiper
BIAS
OS
connected to V+. Since -I
flows through the feedback resistor (R ), the result is an adjustment in offset voltage. The amount of offset voltage
BIAS
adjustment is determined by the value of R (∆V
F
= ∆-I
*R ).
F
OS
BIAS
F
3. R = 100Ω, V = 10V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output is
L
IN
considered disabled when -10mV ≤ V
≤ +10mV.
OUT
4. V = 0V. This is the maximum current that can be pulled out of the Disable pin with the HA-5020 remaining enabled. The HA-5020 is considered
IN
disabled when the supply current has decreased by at least 0.5mA.
5. V
switches from -10V to +10V, or from +10V to -10V. Specification is from the 25% to 75% points.
OUT
Slew Rate
--------------------------
6.
FPBW =
; V
= 10V.
PEAK
2πV
PEAK
7. R = 100Ω, V
= 1V. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay.
L
OUT
8. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-lot variation.
9. V = +10V, Disable = +15V to 0V. Measured from the 50% point of Disable to V
IN
= 0V.
OUT
OUT
10. V = +10V, Disable = 0V to +15V. Measured from the 50% point of Disable to V
= 10V.
IN
11. V = 0V, Force V
IN OUT
from 0V to ±10V, t = t = 50ns.
R F
12. Measured with a VM700A video tester using a NTC-7 composite VITS.
13. See “Typical Performance Curves” for more information.
14. V
= ±2.5V. At -40°C product is tested at V
= ±2.25V because short test duration does not allow self heating.
CM
CM
15. R = 100Ω. V = 2.5V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output is
L
IN
considered disabled when -10mV ≤ V
≤ +10mV.
OUT
16. V
switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points.
Slew Rate
OUT
--------------------------
17. FPBW =
; V
= 2V .
PEAK
2πV
PEAK
18. V = 0V, Force V
from 0V to ±2.5V, t = t = 50ns.
R F
IN OUT
19. V = +2V, Disable = +5V to 0V. Measured from the 50% point of Disable to V
= 0V.
= 2V.
IN
OUT
OUT
20. V = +2V, Disable = 0V to +5V. Measured from the 50% point of Disable to V
IN
FN2845.11
June 5, 2006
7
HA-5020
Test Circuits and Waveforms
+
-
DUT
50Ω
HP4195
NETWORK
ANALYZER
50Ω
FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS
DUT
V
+
-
IN
V
OUT
50Ω
R
400Ω
L
DUT
V
+
-
IN
V
OUT
R , 681Ω
F
50Ω
R
100Ω
L
R
I
681Ω
R , 1kΩ
F
FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT
FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT
V
V
IN
IN
V
V
OUT
OUT
Vertical Scale: V = 100mV/Div., V
IN
Horizontal Scale: 20ns/Div.
= 100mV/Div.
Vertical Scale: V = 1V/Div., V
Horizontal Scale: 50ns/Div.
= 1V/Div.
OUT
OUT
IN
FIGURE 4. SMALL SIGNAL RESPONSE
FIGURE 5. LARGE SIGNAL RESPONSE
FN2845.11
June 5, 2006
8
HA-5020
Schematic Diagram
FN2845.11
June 5, 2006
9
HA-5020
Driving Capacitive Loads
Application Information
Capacitive loads will degrade the amplifier’s phase margin
resulting in frequency response peaking and possible
oscillations. In most cases the oscillation can be avoided by
placing an isolation resistor (R) in series with the output as
shown in Figure 6.
Optimum Feedback Resistor
The plots of inverting and non-inverting frequency response
illustrate the performance of the HA-5020 in various closed
loop gain configurations. Although the bandwidth dependency
on closed loop gain isn’t as severe as that of a voltage
feedback amplifier, there can be an appreciable decrease in
bandwidth at higher gains. This decrease may be minimized
by taking advantage of the current feedback amplifier’s unique
R
V
+
-
IN
V
OUT
R
C
L
T
R
F
R
I
relationship between bandwidth and R . All current feedback
F
amplifiers require a feedback resistor, even for unity gain
FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION
RESISTOR, R
applications, and R , in conjunction with the internal
compensation capacitor, sets the dominant pole of the
frequency response. Thus, the amplifier’s bandwidth is
F
The selection criteria for the isolation resistor is highly
dependent on the load, but 27Ω has been determined to be
a good starting value.
inversely proportional to R . The HA-5020 design is optimized
F
for a 1000Ω R at a gain of +1. Decreasing R in a unity gain
F
F
application decreases stability, resulting in excessive peaking
Enable/Disable Function
and overshoot. At higher gains the amplifier is more stable, so
R can be decreased in a trade-off of stability for bandwidth.
F
When enabled the amplifier functions as a normal current
feedback amplifier with all of the data in the electrical
specifications table being valid and applicable. When
disabled the amplifier output assumes a true high
impedance state and the supply current is reduced
significantly.
The table below lists recommended R values for various
F
gains, and the expected bandwidth.
BANDWIDTH
GAIN (A
-1
)
R
(Ω)
(MHz)
100
125
95
CL
F
750
1000
681
The circuit shown in Figure 7 is a simplified schematic of the
enable/disable function. The large value resistors in series
with the DISABLE pin makes it appear as a current source to
the driver. When the driver pulls this pin low current flows out
of the pin and into the driver. This current, which may be as
large as 350µA when external circuit and process variables
are at their extremes, is required to insure that point “A”
achieves the proper potential to disable the output. The
driver must have the compliance and capability of sinking all
of this current.
+1
+2
+5
1000
383
52
+10
-10
65
750
22
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The use
of low inductance components such as chip resistors and
chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short
especially for the power supply decoupling components and
those components connected to the inverting input.
+V
CC
R
R
33
6
R
10
15K
D
Q
P18
1
R
R
7
8
15K
A
ENABLE/
DISABLE INPUT
Q
P3
Attention must be given to decoupling the power supplies. A
large value (10µF) tantalum or electrolytic capacitor in
parallel with a small value (0.1µF) chip capacitor works well
in most cases.
FIGURE 7. SIMPLIFIED SCHEMATIC OF ENABLE/DISABLE
FUNCTION
When V
CC
is +5V the DISABLE pin may be driven with a
A ground plane is strongly recommended to control noise. Care
must also be taken to minimize the capacitance to ground seen
by the amplifier’s inverting input (-IN). The larger this
dedicated TTL gate. The maximum low level output voltage
of the TTL gate, 0.4V, has enough compliance to insure that
the amplifier will always be disabled even though D will not
1
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. It is recommended that the
ground plane be removed under traces connected to -IN, and
that connections to -IN be kept as short as possible to minimize
the capacitance from this node to ground.
turn on, and the TTL gate will sink enough current to keep
point “A” at its proper voltage. When V
is greater than +5V
CC
the DISABLE pin should be driven with an open collector
device that has a breakdown rating greater than V
.
CC
FN2845.11
June 5, 2006
10
HA-5020
Referring to Figure 7, it can be seen that R will act as a pull-up
such as an A/D converter. The first problem is the low source
impedance which tends to make amplifiers oscillate and
causes gain errors. The second problem is the multiplexer
which supplies no gain, introduces all kinds of distortion and
limits the frequency response. Using op amps which have an
enable/disable function, such as the HA-5020, eliminates the
multiplexer problems because the external mux chip is not
needed, and the HA-5020 can drive low impedance (large
capacitance) loads if a series isolation resistor is used.
6
resistor to +V if the DISABLE pin is left open. In those cases
CC
where the enable/disable function is not required on all circuits
some circuits can be permanently enabled by letting the
DISABLE pin float. If a driver is used to set the enable/disable
level, be sure that the driver does not sink more than 20µA
when the DISABLE pin is at a high level. TTL gates, especially
CMOS versions, do not violate this criteria so it is permissible to
control the enable/disable function with TTL.
Referring to Figure 9, both inputs are terminated in their
characteristic impedance; 75Ω is typical for video
Typical Applications
Two Channel Video Multiplexer
applications. Since the drivers usually are terminated in their
characteristic impedance the input gain is 0.5, thus the
Referring to the amplifier U in Figure 8, R terminates the
1A
cable in its characteristic impedance of 75Ω, and R back
terminates the cable in its characteristic impedance. The
amplifier is set up in a gain configuration of +2 to yield an
overall network gain of +1 when driving a double terminated
1
amplifiers, U , are configured in a gain of +2 to set the circuit
2
4
gain equal to one. Resistors R and R determine the
2
3
amplifier gain, and if a different gain is desired R should be
2
changed according to the equation G = (1 + R /R ). R sets
3
2
3
the frequency response of the amplifier so you should refer
to the manufacturers data sheet before changing its value.
R , C and D are an asymmetrical charge/discharge time
cable. The value of R can be changed if a different network
3
gain is desired. R holds the disable pin at ground thus
5
inhibiting the amplifier until the switch, S , is thrown to
1
5
1
1
circuit which configures U as a break before make switch to
position 1. At position 1 the switch pulls the disable pin up to
the plus supply rail thereby enabling the amplifier. Since all
of the actual signal switching takes place within the amplifier,
it’s differential gain and phase parameters, which are 0.03%
and 0.03° respectively, determine the circuit’s performance.
1
prevent both amplifiers from being active simultaneously. If
this design is extended to more channels the drive logic
must be designed to be break before make. R is enclosed
4
in the feedback loop of the amplifier so that the large open
loop amplifier gain of U will present the load with a small
closed loop output impedance while keeping the amplifier
stable for all values of load capacitance.
The other circuit, U , operates in a similar manner.
1B
2
When the plus supply rail is 5V the disable pin can be driven
by a dedicated TTL gate as discussed earlier. If a multiplexer
IC or its equivalent is used to select channels its logic must be
break before make. When these conditions are satisfied the
HA-5020 is often used as a remote video multiplexer, and the
multiplexer may be extended by adding more amplifier ICs.
The circuit shown in Figure 9 was tested for the full range of
capacitor values with no oscillations being observed; thus,
problem one has been solved. The frequency and gain
characteristics of the circuit are now those of the amplifier
and independent of any multiplexing action; thus, problem
two has been solved. The multiplexer transition time is
approximately 15µs with the component values shown.
Low Impedance Multiplexer
Two common problems surface when you try to multiplex
multiple high speed signals into a low impedance source
VIDEO INPUT #1
R
75
4
U
1A
+5V IN
0.1µF
+5V
10µF
VIDEO OUTPUT
TO 75Ω LOAD
+
-
+
R
1
75
R
2000
5
R
681
2
R
681
3
1
R
100
2
11
-5V IN
0.1µF
-5V
10µF
R
75
VIDEO INPUT #2
9
U
1B
3
+5V
S
1
+
ALL
OFF
NOTES:
21. U is HA-5020.
R
6
75
1
R
10
2000
R
22. All resistors in Ω.
7
R
681
8
681
23. S is break before make.
1
24. Use ground plane.
FIGURE 8. TWO CHANNEL HIGH IMPEDANCE MULTIPLEXER
FN2845.11
June 5, 2006
11
HA-5020
R
INPUT B
INPUT A
3A
R
R
681
1A
75
2A
681
R
4A
27
U
2A
-
+
D
-5V
1A
1N4148
R
1B
75
0.01µF
R
5A
R
681
U
3B
1C
2000
R
2B
681
U
2B
CHANNEL
SWITCH
R
4B
C
1A
0.047µF
-
OUTPUT
+
27
+5V
0.01µF
R
5B
U
1D
NOTES:
25. U : HA-5020.
U
1B
2000
U
C
1A
1B
0.047µF
INHIBIT
2
R
100K
6
26. U : CD4011.
1
D
1B
1N4148
FIGURE 8. LOW IMPEDANCE MULTIPLEXER
V = ±15V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C, unless otherwise specified
SUPPLY
Typical Performance Curves
V
F
L
A
100
100
2.5
2.0
1.5
1.0
A
= +10
V
-INPUT NOISE CURRENT
INPUT NOISE VOLTAGE
V
= ±15V
SUPPLY
10
10
V
= ±4.5V
SUPPLY
V
= ±10V
0.5
0.0
SUPPLY
+INPUT NOISE CURRENT
1
10
1
100k
100
1k
10k
-60
-40
-20
0
20
40
60
80 100 120 140
FREQUENCY (Hz)
TEMPERATURE (°C)
FIGURE 9. INPUT NOISE vs FREQUENCY (AVERAGE OF 18
UNITS FROM 3 LOTS)
FIGURE 10. INPUT OFFSET VOLTAGE vs TEMPERATURE
(ABSOLUTE VALUE AVERAGE OF 30 UNITS
FROM 3 LOTS)
0
-0.5
-1.0
2.0
1.8
V
= ±15V
SUPPLY
1.6
1.4
V
V
= ±15V
= ±10V
SUPPLY
SUPPLY
V
= ±10V
SUPPLY
-1.5
V
= ±4.5V
SUPPLY
-2.0
-2.5
1.2
1.0
V
= ±4.5V
SUPPLY
-60
-40
-20
0
20
40
60
80 100 120 140
-60
-40
-20
0
20
40
60
80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. +INPUT BIAS CURRENT vs TEMPERATURE
(AVERAGE OF 30 UNITS FROM 3 LOTS)
FIGURE 12. -INPUT BIAS CURRENT vs TEMPERATURE
(ABSOLUTE VALUE AVERAGE OF 30 UNITS
FROM 3 LOTS)
FN2845.11
June 5, 2006
12
HA-5020
Typical Performance Curves
V
= ±15V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C, unless otherwise specified (Continued)
SUPPLY
V
F
L
A
8
7
6
5
4
6
125°C
5
V
= ±15V
SUPPLY
25°C
-55°C
V
= ±10V
SUPPLY
4
3
2
1
V
= ±4.5V
SUPPLY
3
5
7
9
11
13
15
-60
-40
-20
0
20
40
60
80
100 120 140
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
FIGURE13. TRANSIMPEDANCEvsTEMPERATURE(AVERAGE
OF 30 UNITS FROM 3 LOTS)
FIGURE 14. SUPPLY CURRENT vs SUPPLY VOLTAGE
(AVERAGE OF 30 UNITS FROM 3 LOTS)
7
9
8
DISABLE = 0V
V
= ±4.5V
V
= ±10V
V
= ±15V
SUPPLY
6
SUPPLY
SUPPLY
-55°C
7
6
5
4
3
2
1
0
5
25°C
4
125°C
3
2
1
0
1
3
5
7
9
11
13
15
3
5
7
9
11
13
15
SUPPLY VOLTAGE (±V)
DISABLE INPUT VOLTAGE (V)
FIGURE 15. DISABLE SUPPLY CURRENT vs SUPPLY VOLTAGE
(AVERAGE OF 30 UNITS FROM 3 LOTS)
FIGURE 16. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE
0
1.0
DISABLE = 0V
-10
-20
-30
-40
-50
-60
-70
-80
V
= 5V
IN
P-P
V
= +10V
= -10V
0.5
0
OUT
R
= 750Ω
F
V
OUT
-0.5
-1.0
0
2M 4M
6M 8M 10M 12M 14M 16M 18M 20M
FREQUENCY (Hz)
-60 -40 -20
0
20
40
60
80 100 120 140
TEMPERATURE (°C)
FIGURE 17. DISABLE MODE FEEDTHROUGH vs FREQUENCY
FIGURE 18. DISABLED OUTPUT LEAKAGE vs TEMPERATURE
(AVERAGE OF 30 UNITS FROM 3 LOTS)
FN2845.11
June 5, 2006
13
HA-5020
Typical Performance Curves
V
= ±15V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C, unless otherwise specified (Continued)
SUPPLY
V
F
L
A
3
2
2.0
1.8
1.6
1.4
1.2
1.0
20
18
16
14
12
10
8
V
= 0.2V
P-P
= 10pF
OUT
C
L
1
0
A
= +1
V
-1
-2
-3
-4
-5
-6
-7
ENABLE TIME
A
= +2
V
0.8
0.6
6
0.4
4
DISABLE TIME
A
= +6
V
A = +10
V
0.2
0.0
2
0
-10 -8
-6
-4
-2
0
2
4
6
8
10
0
24M
48M
72M
96M
120M
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
FIGURE 19. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE
(AVERAGE OF 9 UNITS FROM 3 LOTS)
FIGURE 20. NON-INVERTING GAIN vs FREQUENCY
2
+180
1
0
V
= 0.2V
P-P
= 10pF
= 750Ω
OUT
C
R
+135
+90
+45
0
A
= -1
L
F
V
A
= -2
V
+45
0
-1
-2
-3
-4
-5
-6
-7
-8
A
= -1
V
A
= -6
V
A
= -10
V
-45
A
= -2
V
-45
-90
A
= +1
V
-90
-135
-180
-225
-270
A
= +2
= +6
V
V
A = -6
V
-135
-180
A
= -10
24M
V
A
A
= +10
48M
V
0
48M
72M
96M
120M
0
24M
72M
96M
120M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 21. INVERTING FREQUENCY RESPONSE
FIGURE 22. PHASE vs FREQUENCY
105
100
95
20
15
10
5
110
100
5
4
C
= 10pF
L
C
= 10pF
L
-3dB BANDWIDTH
GAIN PEAKING
V
= 0.2V
P-P
OUT
V
= 0.2V
P-P
OUT
-3dB BANDWIDTH
90
3
80
70
60
2
1
0
90
GAIN PEAKING
85
0
1.5k
700
900
1.1k
1.3k
0
200
400
600
800
1000
LOAD RESISTANCE (Ω)
FEEDBACK RESISTOR (Ω)
FIGURE 23. BANDWIDTH AND GAIN PEAKING vs LOAD
RESISTANCE
FIGURE 24. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
FN2845.11
June 5, 2006
14
HA-5020
Typical Performance Curves
V
= ±15V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C, unless otherwise specified (Continued)
SUPPLY
V
F
L
A
80
70
60
50
40
30
20
10
100
20
15
10
5
C
= 10pF, A = +10
V
L
C
= 10pF, A = +2
V
L
V
= 0.2V
OUT
P-P
V
= 0.2V
P-P
OUT
95
90
85
80
GAIN PEAKING = 0dB
-3dB BANDWIDTH
GAIN PEAKING
0
1.2k
200
400
600
800
1000
400
600
800
1.0k
FEEDBACK RESISTOR (Ω)
FEEDBACK RESISTOR (Ω)
FIGURE 25. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
FIGURE 26. BANDWIDTH vs FEEDBACK RESISTANCE
75
70
0
A
= +10
V
-10
-20
-30
-40
-50
-60
-70
-80
-90
PSRR
65
CMRR
+PSRR
60
CMRR
-PSRR
1M
55
-60 -40 -20
0
20
40
60
80 100 120 140
10k
100k
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
FIGURE 27. REJECTION RATIOS vs TEMPERATURE
(AVERAGE OF 30 UNITS FROM 3 LOTS)
FIGURE 28. REJECTION RATIOS vs FREQUENCY
30
25
20
15
10
5
3.5
(±V
) - (±V )
OUT
SUPPLY
V
= ±15V
= ±10V
V
= ±15V
SUPPLY
SUPPLY
3.0
2.5
2.0
1.5
V
= ±10V
SUPPLY
V
SUPPLY
V
= ±4.5V
SUPPLY
V
= ±4.5V
SUPPLY
0
-60 -40 -20
0
20
40
60
80 100 120 140
10
100
1k
10k
LOAD RESISTANCE (Ω)
TEMPERATURE (°C)
FIGURE 29. OUTPUT SWING OVERHEAD vs TEMPERATURE
(AVERAGE OF 30 UNITS FROM 3 LOTS)
FIGURE 30. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
FN2845.11
June 5, 2006
15
HA-5020
Typical Performance Curves
V
= ±15V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C, unless otherwise specified (Continued)
SUPPLY
V
F
L
A
7.0
6.5
6.0
5.5
5.0
100
90
R
= 100Ω
LOAD
80
V
= 1V
OUT
P-P
-ISC
70
+ISC
60
50
40
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 31. SHORT CIRCUIT CURRENT LIMIT vs TEMPERATURE
FIGURE 32. PROPAGATION DELAY vs TEMPERATURE
(AVERAGE OF 18 UNITS FROM 3 LOTS)
11.0
15
V
= 100mV
, C = 10pF
OUT
P-P L
A
= +10
V
(R = 383Ω)
V
= ±5V
10.0
9.0
F
SUPPLY
A
= +2
V
10
5
A
= +1
V
8.0
7.0
6.0
5.0
A
A
= +2
= +1
V
= ±15V
V
V
SUPPLY
= +1
A
V
R
V
= 100Ω
LOAD
= 1V
A
= +2
V
OUT
P-P
0
0
200
400
600
800
1000
3
5
7
9
11
13
15
SUPPLY VOLTAGE (±V)
LOAD RESISTANCE (Ω)
FIGURE 33. PROPAGATION DELAY vs SUPPLY VOLTAGE
(AVERAGE OF 18 UNITS FROM 3 LOTS)
FIGURE 34. SMALL SIGNAL OVERSHOOT vs LOAD
RESISTANCE
0.07
-50
FREQUENCY = 3.58MHz
V
= 2V
O
P-P
= 30pF
C
L
0.06
0.05
RD
-60
-70
-80
-90
3
ORDER IMD
HD2 (GEN)
R
R
= 75Ω
LOAD
RD
3
ORDER IMD
0.04
0.03
0.02
0.01
(GENERATOR)
HD3
= 150Ω
LOAD
HD2
R
= 1K
LOAD
HD3 (GEN)
3
5
7
9
11
13
15
1M
FREQUENCY (Hz)
10M
SUPPLY VOLTAGE (±V)
FIGURE 35. DISTORTION vs FREQUENCY
FIGURE 36. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE
(AVERAGE OF 18 UNITS FROM 3 LOTS)
FN2845.11
June 5, 2006
16
HA-5020
Typical Performance Curves
V
= ±15V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C, unless otherwise specified (Continued)
SUPPLY
V
F
L
A
1200
1000
800
0.07
FREQUENCY = 3.58MHz
0.06
0.05
0.04
0.03
0.02
0.01
V
= 20V
P-P
OUT
R
= 75Ω
LOAD
+SLEW RATE
-SLEW RATE
R
= 150Ω
LOAD
R
= 1K
LOAD
600
-60 -40 -20
0
20
40
60
80 100 120 140
3
5
7
9
11
13
15
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
FIGURE 37. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE
(AVERAGE OF 18 UNITS FROM 3 LOTS)
FIGURE 38. SLEW RATE vs TEMPERATURE
(AVERAGE OF 30 UNITS FROM 3 LOTS)
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C, Unless Otherwise Specified
SUPPLY
V
F
L
A
5
4
5
4
3
A
+ 2
V
3
2
1
2
1
A
= -1
V
0
-1
-2
-3
-4
-5
A
+ 1
0
V
A
= -2
V
-1
-2
-3
-4
-5
A
+ 10
V
A
= -10
V
2M
10M
FREQUENCY (Hz)
100M
200M
2M
10M
FREQUENCY (Hz)
100M
200M
FIGURE 39. NON-INVERTING FREQUENCY RESPONSE
FIGURE 40. INVERTING FREQUENCY RESPONSE
140
5
V
C
A
= 0.2V
P-P
= 10pF
= +1
OUT
4
3
2
1
180
135
90
A
+ 1
V
L
V
130
120
A
- 1
V
A
+ 10
45
V
A
- 10
10
-3dB BANDWIDTH
V
0
-1
-2
-3
0
-45
-90
-135
-180
5
0
GAIN PEAKING
-4
-5
500
700
900
1100
1300
1500
2M
10M
FREQUENCY (Hz)
100M
200M
FEEDBACK RESISTOR (Ω)
FIGURE 41. PHASE RESPONSE AS A FUNCTION OF
FREQUENCY
FIGURE 42. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
FN2845.11
June 5, 2006
17
HA-5020
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
A
100
130
V
= 0.2V
P-P
OUT
C
A
= 10pF
= +2
L
V
120
110
95
90
-3dB BANDWIDTH
6
-3dB BANDWIDTH
10
100
4
2
0
5
0
V
C
A
= 0.2V
P-P
= 10pF
= +1
90
80
OUT
GAIN PEAKING
L
V
GAIN PEAKING
0
200
400
600
800
1000
350
500
650
800
950
1100
FEEDBACK RESISTOR (Ω)
LOAD RESISTOR (Ω)
FIGURE 43. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
FIGURE 44. BANDWIDTH AND GAIN PEAKING vs LOAD
RESISTANCE
80
A
= +1
V
V
C
A
= 0.2V
P-P
OUT
L
V
0
= 10pF
= +10
-10
60
-20
-30
-40
-50
40
20
0
CMRR
-60
-70
-80
NEGATIVE PSRR
POSITIVE PSRR
0.1M
200
350
500
650
800
950
0.001M
0.01M
1M
10M 30M
FEEDBACK RESISTOR (Ω)
FREQUENCY (Hz)
FIGURE 45. BANDWIDTH vs FEEDBACK RESISTANCE
FIGURE 46. REJECTION RATIOS vs FREQUENCY
8.0
500
R
V
A
= 100Ω
OUT
= +1
V
= 2V
P-P
L
OUT
= 1.0V
450
400
350
300
250
P-P
V
+ SLEW RATE
7.5
- SLEW RATE
7.0
6.5
6.0
200
150
100
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 47. PROPAGATION DELAY vs TEMPERATURE
FIGURE 48. SLEW RATE vs TEMPERATURE
FN2845.11
June 5, 2006
18
HA-5020
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
A
0.8
0.6
0.4
0.2
0
0.8
V
C
R
= 0.2V
P-P
= 10pF
= 750Ω
OUT
V
C
= 0.2V
P-P
0.6
0.4
0.2
0
OUT
= 10pF
L
F
L
A
= -1
V
A
= +2, R = 681Ω
F
V
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-0.2
-0.4
-0.6
A
= +5, R = 1kΩ
V
F
A
= -5
V
A
= +1, R = 1kΩ
F
V
A
= -10
V
-0.8
-1.0
-1.2
A
= -2
V
A
= 10, R = 383Ω
V
F
5M
10M
15M
20M
25M
30M
5M
10M
15M
20M
25M
30M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 49. NON-INVERTING GAIN FLATNESS vs FREQUENCY
FIGURE 50. INVERTING GAIN FLATNESS vs FREQUENCY
74
100
80
1000
800
A
= 10, R = 383Ω
F
V
+PSRR
72
70
68
66
64
62
60
58
-INPUT NOISE CURRENT
600
60
-PSRR
+INPUT NOISE CURRENT
400
40
+INPUT NOISE VOLTAGE
200
0
20
0
CMRR
-100
-50
0
50
100
150
200
250
0.01k
0.1k
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
FIGURE 51. INPUT NOISE CHARACTERISTICS
FIGURE 52. REJECTION RATIO vs TEMPERATURE
4.0
3.8
32
20
30
18
ENABLE
28
26
24
22
16
14
12
10
ENABLE
20
8
18
16
14
12
6
4
2
0
DISABLE
DISABLE
3.6
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
-60 -40 -20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
FIGURE 53. OUTPUT SWING vs TEMPERATURE
FIGURE 54. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE
FN2845.11
June 5, 2006
19
HA-5020
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C, Unless Otherwise Specified (Continued)
SUPPLY
V
F
L
A
10
1
DISABLE = 0V
0
V
= 5V
R = 100Ω
L
IN P-P
= 750Ω
R
F
-10
-20
-30
0.1
0.01
180
135
90
0.001
-40
-50
-60
-70
-80
45
0
-45
-90
-135
0.1M
1M
10M
20M
0.001M
0.01M
0.1M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 55. DISABLE FEEDTHROUGH vs FREQUENCY
FIGURE 56. TRANSIMPEDANCE vs FREQUENCY
10
1
R
= 400Ω
L
0.1
180
135
90
0.01
0.001
45
0
-45
-90
-135
0.001M
0.01M
0.1M
1M
10M
100M
FREQUENCY (Hz)
FIGURE 57. TRANSIMPEDENCE vs FREQUENCY
FN2845.11
June 5, 2006
20
HA-5020
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
1640µm x 1520µm x 483µm
Type: Nitride over Silox
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1kÅ
METALLIZATION:
Type: Aluminum, 1% Copper
Thickness: 16kÅ ±2kÅ
TRANSISTOR COUNT:
62
SUBSTRATE POTENTIAL (Powered Up):
PROCESS:
V-
High Frequency Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5020
BAL
DISABLE
V+
2
1
8
7
IN-
6
OUT
3
4
5
IN+
V-
BAL
FN2845.11
June 5, 2006
21
HA-5020
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A
A
1
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
English and Metric dimensions, the inch dimensions control.
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
FN2845.11
June 5, 2006
22
HA-5020
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN2845.11
June 5, 2006
23
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