HC5515CMZ [INTERSIL]
ITU CO/PABX SLIC with Low Power Standby; ITU CO / PABX SLIC与低功耗待机
| 型号： | HC5515CMZ |
| 厂家： | 
Intersil |
| 描述： | ITU CO/PABX SLIC with Low Power Standby |
| 文件： | 总20页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC5515
®
Data Sheet
June 6, 2006
FN4235.6
ITU CO/PABX SLIC with Low Power
Standby
Features
• DI Monolithic High Voltage Process
The HC5515 is a subscriber line interface circuit which is
interchangeable with Ericsson’s PBL3860 for distributed
central office applications. Enhancements include immunity
to circuit latch-up during hot plug and absence of false
signaling in the presence of longitudinal currents.
• Programmable Current Feed (20mA to 60mA)
• Programmable Loop Current Detector Threshold and
Battery Feed Characteristics
• Ring Trip Detection
• Compatible with Ericsson’s PBL3860
• Thermal Shutdown
The HC5515 is fabricated in a High Voltage Dielectrically
Isolated (DI) Bipolar Process that eliminates leakage
currents and device latch-up problems normally associated
with junction isolated ICs. The elimination of the leakage
currents results in improved circuit performance for wide
temperature extremes. The latch free benefit of the DI
process guarantees operation under adverse transient
conditions. This process feature makes the HC5515 ideally
suited for use in harsh outdoor environments.
• On-Hook Transmission
• Wide Battery Voltage Range (-24V to -58V)
• Low Standby Power
• -40°C to 85°C Ambient Temperature Range
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Ordering Information
• Digital Loop Carrier Systems
• Fiber-In-The-Loop ONUs
• Wireless Local Loop
• Pair Gain
• POTS
PART
NUMBER
PART
TEMP.
PKG.
MARKING RANGE (°C) PACKAGE DWG. #
HC5515CM HC5515CM
0 to 70
0 to 70
28 Ld PLCC N28.45
• PABX
• Hybrid Fiber Coax
HC5515CMZ HC5515CMZ
(Note)
28 Ld PLCC N28.45
(Pb-free)
• Related Literature
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
- AN9632, Operation of the HC5523/15 Evaluation Board
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HC5515
Block Diagram
RING RELAY
DRIVER
4-WIRE
RINGRLY
V
INTERFACE
TX
VF SIGNAL
PATH
RSN
DT
DR
RING TRIP
DETECTOR
TIP
RING
2-WIRE
INTERFACE
HPT
HPR
LOOP CURRENT
DETECTOR
E0
C1
C2
DIGITAL
MULTIPLEXER
V
BAT
V
CC
DET
V
BIAS
EE
R
R
D
AGND
BGND
DC
RSG
FN4235.6
June 6, 2006
2
HC5515
Absolute Maximum Ratings
Thermal Information
Temperature, Humidity
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
53
JA
Storage Temperature Range . . . . . . . . . . . . . . . . .-65°C to 150°C
Operating Temperature Range. . . . . . . . . . . . . . . . -40°C to 110°C
Operating Junction Temperature Range . . . . . . . .-40°C to 150°C
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . .
Continuous Power Dissipation at 70°C
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
Package Power Dissipation at 70°C, t < 100ms, t > 1s
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W
Derate above . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18.8mW/°C
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18.8mW/°C
Maximum Junction Temperature Range . . . . . . . . . .-40°C to 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(PLCC - Lead Tips Only)
Power Supply (-40°C ≤ T ≤ 85°C)
A
REP
Supply Voltage V
to GND . . . . . . . . . . . . . . . . . . . . 0.5V to 7V
CC
Supply Voltage V to GND. . . . . . . . . . . . . . . . . . . . . -7V to 0.5V
EE
Supply Voltage V
to GND. . . . . . . . . . . . . . . . . . . -80V to 0.5V
BAT
Ground
Voltage between AGND and BGND. . . . . . . . . . . . . -0.3V to 0.3V
Relay Driver
Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 0V to 20V
Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Ring Trip Comparator
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 5mA
Digital Inputs, Outputs (C1, C2, E0, DET)
to 0V
BAT
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . 543 Transistors, 51 Diodes
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to V
Output Voltage (DET Not Active) . . . . . . . . . . . . . . . . . .0V to V
CC
CC
Output Current (DET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Tipx and Ringx Terminals (-40°C ≤ T ≤ 85°C)
A
Tipx or Ringx Voltage, Continuous (Referenced to GND)V
to +2V
BAT
-20V to +5V
Tipx or Ringx, Pulse < 10ms, T
Tipx or Ringx, Pulse < 10µs, T
Tipx or Ringx, Pulse < 250ns, T
> 10s . . . . V
REP
REP
BAT
> 10s. . . . V
-40V to +10V
-70V to +15V
BAT
BAT
> 10s. . . V
REP
Tipx or Ringx Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Typical Operating Conditions
These represent the conditions under which the part was developed and are suggested as guidelines.
PARAMETER
Case Temperature
CONDITIONS
MIN
-40
TYP
MAX
100
UNITS
-
-
-
-
°C
V
V
V
V
with Respect to AGND
-40°C to 85°C
4.75
-5.25
-58
5.25
-4.75
-24
CC
EE
with Respect to AGND
-40°C to 85°C
-40°C to 85°C
V
with Respect to BGND
V
BAT
Electrical Specifications T = 0°C to 70°C, V = +5V ±5%, V = -5V ±5%, V = -48V, AGND = BGND = 0V, R
BAT DC1
= R
DC2
= 41.2kΩ,
A
R
CC
EE
= 39kΩ, R
SG
= 0Ω, R = R = 0Ω, C = 10nF, C
= 1.5µF, Z = 600Ω, Unless Otherwise Specified.
D
F1 F2 HP DC L
PARAMETER
CONDITIONS
MIN
3.1
-
TYP
-
MAX
-
UNITS
Overload Level
1% THD, Z = 600Ω, (Note 2, Figure 1)
V
L
PEAK
Longitudinal Impedance (Tip/Ring)
0 < f < 100Hz (Note 3, Figure 2)
20
35
Ω/Wire
A
V
V
T
TX
19
TIP
27
TX
19
1V
TIP
27
RMS
0 < f < 100Hz
V
300Ω
T
E
L
C
R
T
R
R
L
T
600kΩ
600Ω
600kΩ
V
TRO
2.16µF
I
300Ω
DCMET
23mA
V
R
E
RX
R
RX
R
RX
A
R
RING
28
RSN
16
RING
28
RSN
16
300kΩ
300kΩ
LZ = V /A
LZ = V /A
R R
T
T
T
R
FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT)
FIGURE 2. LONGITUDINAL IMPEDANCE
FN4235.6
June 6, 2006
3
HC5515
Electrical Specifications T = 0°C to 70°C, V = +5V ±5%, V = -5V ±5%, V = -48V, AGND = BGND = 0V, R
= R
= 41.2kΩ,
= 1.5µF, Z = 600Ω, Unless Otherwise Specified.
A
R
CC
EE
BAT DC1
DC2
= 39kΩ, R
SG
= 0Ω, R = R = 0Ω, C = 10nF, C
D
F1 F2 HP DC
L
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LONGITUDINAL CURRENT LIMIT (TIP/RING)
Off-Hook (Active)
No False Detections, (Loop Current),
LB > 45dB (Note 4, Figure 3A)
20
5
-
-
-
-
mA
/
/
PEAK
Wire
On-Hook (Standby), R = ∞
No False Detections (Loop Current) (Note 5,
Figure 3B)
mA
L
PEAK
Wire
368Ω
368Ω
TIP
27
RSN
16
A
TIP
27
RSN
16
A
2.16µF
C
39kΩ
C
39kΩ
R
R
E
DC1
R
D
E
DC1
R
D
L
L
41.2kΩ
41.2kΩ
-5V
A
-5V
A
2.16µF
2.16µF
C
C
R
C
DC
DC2
DC
R
DC2
R
RING
28
R
RING
28
DC
14
DC
368Ω
41.2kΩ
14
368Ω
1.5µF
1.5µF
41.2kΩ
DET
DET
FIGURE 3A. OFF-HOOK
FIGURE 3B. ON-HOOK
FIGURE 3. LONGITUDINAL CURRENT LIMIT
OFF-HOOK LONGITUDINAL BALANCE
Longitudinal to Metallic
IEEE 455 - 1985, R , R = 368Ω
0.2kHz < f < 4.0kHz (Note 6, Figure 4)
53
53
50
70
70
55
-
-
-
dB
LR LT
Longitudinal to Metallic
Metallic to Longitudinal
R
, R = 300Ω, 0.2kHz < f < 4.0kHz
LR LT
dB
dB
(Note 6, Figure 4)
FCC Part 68, Para 68.310
0.2kHz < f < 1.0kHz
1.0kHz < f < 4.0kHz (Note 7)
50
53
50
55
70
55
-
-
-
dB
dB
dB
Longitudinal to 4-Wire
Metallic to Longitudinal
0.2kHz < f < 4.0kHz (Note 8, Figure 4)
R
, R = 300Ω, 0.2kHz < f < 4.0kHz
LR LT
(Note 9, Figure 5)
4-Wire to Longitudinal
0.2kHz < f < 4.0kHz (Note 10, Figure 5)
50
55
-
dB
R
LT
R
LT
V
TIP
27
V
TX
19
TIP
27
TX
19
300Ω
E
2.16µF
L
E
R
T
600kΩ
C
TR
R
T
V
V
TR
TX
600kΩ
C
2.16µF
V
L
E
RX
R
R
R
LR
RX
RX
RSN
16
RING
28
RSN
16
RING
28
R
300kΩ
300kΩ
300Ω
LR
FIGURE 4. LONGITUDINAL TO METALLIC AND
LONGITUDINAL TO 4-WIRE BALANCE
FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO
LONGITUDINAL BALANCE
2-Wire Return Loss
= 20nF
0.2kHz to 0.5kHz (Note 11, Figure 6)
0.5kHz to 1.0kHz (Note 11, Figure 6)
1.0kHz to 3.4kHz (Note 11, Figure 6)
25
27
23
-
-
-
-
-
-
dB
dB
dB
C
HP
TIP IDLE VOLTAGE
Active, I = 0
-
-
-1.5
<0
-
-
V
V
L
Standby, I = 0
L
RING IDLE VOLTAGE
Active, I = 0
-
-
-46.5
>-48
-
-
V
V
L
Standby, I = 0
L
FN4235.6
June 6, 2006
4
HC5515
Electrical Specifications T = 0°C to 70°C, V = +5V ±5%, V = -5V ±5%, V = -48V, AGND = BGND = 0V, R
= R
= 41.2kΩ,
= 1.5µF, Z = 600Ω, Unless Otherwise Specified.
A
R
CC
EE
BAT DC1
DC2
= 39kΩ, R
= 0Ω, R = R = 0Ω, C = 10nF, C
D
SG
F1 F2 HP DC
L
(Continued)
PARAMETER
TIP-RING Open Loop Metallic Voltage, V
CONDITIONS
= 0Ω
MIN
TYP
MAX
UNITS
V
= -52V, R
SG
43
-
47
V
TR
BAT
4-WIRE TRANSMIT PORT (V
Overload Level
)
TX
Z
> 20kΩ, 1% THD (Note 12, Figure 7)
3.1
-60
-
-
-
-
V
L
PEAK
mV
Output Offset Voltage
E
= 0, Z = ∞ (Note 13, Figure 7)
60
G
L
Output Impedance (Guaranteed by Design)
0.2kHz < f < 03.4kHz
5
20
W
2-Wire to 4-Wire (Metallic to V ) Voltage Gain 0.3kHz < f < 03.4kHz (Note 14, Figure 7)
0.98
1.0
1.02
V/V
TX
Z
2.16µF
D
TIP
27
V
V
TX
19
TIP
27
TX
19
R
L
C
600Ω
V
R
R
TR
R
V
T
M
Z
R
600kΩ
T
V
V
TXO
TX
V
Z
L
S
600kΩ
I
DCMET
23mA
E
G
IN
R
R
RX
RX
RING
28
RSN
16
RING RSN
28 16
R
300kΩ
300kΩ
LR
FIGURE 6. TWO-WIRE RETURN LOSS
FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT),
OUTPUT OFFSET VOLTAGE, 2-WIRE TO 4-WIRE
VOLTAGE GAIN AND HARMONIC DISTORTION
4-WIRE RECEIVE PORT (RSN)
DC Voltage
I
= 0mA
-
-
0
-
-
V
W
RSN
R
Sum Node Impedance (Gtd by Design)
0.2kHz < f < 3.4kHz
20
X
Current Gain-RSN to Metallic
FREQUENCY RESPONSE (OFF-HOOK)
2-Wire to 4-Wire
0.3kHz < f < 3.4kHz (Note 15, Figure 8)
900
1000
1100
Ratio
0dBm at 1.0kHz, E = 0V
RX
0.3kHz < f < 3.4kHz (Note 16, Figure 9)
-0.2
-0.2
-0.2
-
-
-
0.2
0.2
0.2
dB
dB
dB
4-Wire to 2-Wire
4-Wire to 4-Wire
0dBm at 1.0kHz, E = 0V
G
0.3kHz < f < 3.4kHz (Note 17, Figure 9)
0dBm at 1.0kHz, E = 0V
G
0.3kHz < f < 3.4kHz (Note 18, Figure 9)
INSERTION LOSS
2-Wire to 4-Wire
0dBm, 1kHz (Note 19, Figure 9)
0dBm, 1kHz (Note 20, Figure 9)
-0.2
-0.2
-
-
0.2
0.2
dB
dB
4-Wire to 2-Wire
GAIN TRACKING (Ref = -10dBm, at 1.0kHz)
2-Wire to 4-Wire
+3dBm to +7dBm (Note 21, Figure 9)
-40dBm to +3dBm (Note 21, Figure 9)
-55dBm to -40dBm (Note 21, Figure 9)
-40dBm to +7dBm (Note 22, Figure 9)
-0.15
-0.1
-0.2
-0.1
-
-
-
-
0.15
0.1
dB
dB
dB
dB
2-Wire to 4-Wire
2-Wire to 4-Wire
0.2
4-Wire to 2-Wire
0.1
FN4235.6
June 6, 2006
5
HC5515
Electrical Specifications T = 0°C to 70°C, V = +5V ±5%, V = -5V ±5%, V = -48V, AGND = BGND = 0V, R
= R
= 41.2kΩ,
= 1.5µF, Z = 600Ω, Unless Otherwise Specified.
A
R
CC
EE
BAT DC1
DC2
= 39kΩ, R
SG
= 0Ω, R = R = 0Ω, C = 10nF, C
D
F1 F2 HP DC
L
(Continued)
PARAMETER
CONDITIONS
-55dBm to -40dBm (Note 22, Figure 9)
MIN
TYP
MAX
UNITS
4-Wire to 2-Wire
-0.2
-
0.2
dB
GRX = ((V )(300k))/(-3)(600)
- V
TR1 TR2
Where: V
TR1
is the Tip to Ring Voltage with V
RSN
= 0V
and V
is the Tip to Ring Voltage with V
= -3V
TR2
RSN
V
V
= 0V
RSN
C
R
RX
= -3V
RSN
TIP
27
V
TIP
27
RSN
16
TX
19
R
300kΩ
L
600Ω
R
T
R
R
L
DC1
600kΩ
V
TX
600Ω
I
41.2kΩ
V
V
DCMET
TR
TR
E
G
E
RX
C
R
R
DC
RX
DC2
1/ωC < R
L
RING
28
R
RING RSN
28 16
DC
14
1.5µF
41.2kΩ
300kΩ
FIGURE 8. CURRENT GAIN-RSN TO METALLIC
FIGURE 9. FREQUENCY RESPONSE, INSERTION LOSS,
GAIN TRACKING AND HARMONIC DISTORTION
NOISE
Idle Channel Noise at 2-Wire
C-Message Weighting (Note 23, Figure 10)
-
-
8.5
-
-
dBrnC
dBrnp
Psophometrical Weighting
(Note 23, Figure 10)
-81.5
Idle Channel Noise at 4-Wire
C-Message Weighting (Note 24, Figure 10)
-
-
8.5
-
-
dBrnC
dBrnp
Psophometrical Weighting
(Note 23, Figure 10)
-81.5
HARMONIC DISTORTION
2-Wire to 4-Wire
0dBm, 1kHz (Note 25, Figure 7)
-
-
-65
-65
-54
-54
dB
dB
4-Wire to 2-Wire
0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 9)
BATTERY FEED CHARACTERISTICS
Constant Loop Current Tolerance
I = 2500/(R
-40°C to 85°C (Note 27)
+ R
DC2
),
0.85I
0.75I
14
I
I
1.15I
1.25I
20
mA
mA
V
L
DC1
L
L
L
L
L
L
R
= 41.2kΩ
DCX
Loop Current Tolerance (Standby)
I = (V -3)/(R +1800),
L
BAT
L
-40°C to 85°C (Note 28)
Open Circuit Voltage (V
TIP
- V
)
-40°C to 85°C, (Active) R
= ∞
SG
16.67
RING
LOOP CURRENT DETECTOR
On-Hook to Off-Hook
R
R
R
= 33kΩ, -40°C to 85°C
11
9.5
-
465/R
405/R
17.2
15.0
-
mA
mA
mA
D
D
D
D
D
Off-Hook to On-Hook
= 33kΩ, -40°C to 85°C
= 33kΩ, -40°C to 85°C
Loop Current Hysteresis
60/R
D
TIP
27
V
TX
19
R
R
L
T
V
600Ω
TR
V
TX
600kΩ
R
RX
RING RSN
28 16
300kΩ
FIGURE 10. IDLE CHANNEL NOISE
FN4235.6
June 6, 2006
6
HC5515
Electrical Specifications T = 0°C to 70°C, V = +5V ±5%, V = -5V ±5%, V = -48V, AGND = BGND = 0V, R
= R
= 41.2kΩ,
= 1.5µF, Z = 600Ω, Unless Otherwise Specified.
A
R
CC
EE
BAT DC1
DC2
= 39kΩ, R
SG
= 0Ω, R = R = 0Ω, C = 10nF, C
D
F1 F2 HP DC
L
(Continued)
PARAMETER
RING TRIP DETECTOR (DT, DR)
Offset Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
Source Res = 0
Source Res = 0
Source Res = 0
-20
-
-
-
-
-
20
mV
nA
V
Input Bias Current
-360
360
Input Common-Mode Range
Input Resistance
V
+1
0
-
BAT
1
Source Res = 0, Unbalanced
Source Res = 0, Balanced
MΩ
MΩ
3
-
RING RELAY DRIVER
V
at 25mA
I
= 25mA
OL
-
-
0.2
-
0.6
10
V
SAT
Off-State Leakage Current
V
= 12V
µA
OH
DIGITAL INPUTS (E0, C1, C2)
Input Low Voltage, V
0
2
-
-
-
-
-
0.8
V
IL
Input High Voltage, V
V
V
IH
Input Low Current, I : C1, C2
CC
-
V
V
V
= 0.4V
= 0.4V
= 2.4V
-200
-100
-
µA
µA
µA
IL
IL
IL
IH
Input Low Current, I : E0
IL
-
Input High Current
40
DETECTOR OUTPUT (DET)
Output Low Voltage, V
I
I
= 2mA
-
2.7
8
-
-
0.45
-
V
V
OL
OL
Output High Voltage, V
= 100µA
OH
OH
Internal Pull-Up Resistor
POWER DISSIPATION (V
Open Circuit State
15
25
kΩ
= -48V)
BAT
C1 = C2 = 0
C1 = C2 = 1
-
-
-
-
26.3
37.5
110
1.1
70
85
mW
mW
mW
W
On-Hook, Standby
On-Hook, Active
C1 = 0, C2 = 1, R = High Impedance
300
1.4
L
Off-Hook, Active
C1 = 0, C2 = 1, R = 600Ω
L
TEMPERATURE GUARD
Thermal Shutdown
150
-
180
°C
SUPPLY CURRENTS (V
= -28V)
BAT
Open Circuit State (C1, 2 = 0, 0)
On-Hook
I
I
I
I
I
I
I
I
I
-
-
-
-
-
-
-
-
-
1.3
0.6
2.8
2.0
1.2
3.5
2.0
1.6
9.5
4.0
5.2
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC
EE
0.35
1.6
BAT
CC
EE
Standby State (C1, 2 = 1, 1)
On-Hook
0.62
0.55
3.7
BAT
CC
EE
Active State (C1, 2 = 0, 1)
On-Hook
1.1
2.2
BAT
PSRR
V
V
to 2 or 4-Wire Port
to 2 or 4-Wire Port
(Note 29, Figure 11)
(Note 29, Figure 11)
-
-
40
40
-
-
dB
dB
CC
EE
FN4235.6
June 6, 2006
7
HC5515
Electrical Specifications T = 0°C to 70°C, V = +5V ±5%, V = -5V ±5%, V = -48V, AGND = BGND = 0V, R
BAT DC1
= R = 41.2kΩ,
DC2
A
R
CC
EE
= 39kΩ, R = 0Ω, R = R = 0Ω, C = 10nF, C = 1.5µF, Z = 600Ω, Unless Otherwise Specified.
D
SG
F1
F2
HP
DC
L
(Continued)
PARAMETER
to 2 or 4-Wire Port
CONDITIONS
(Note 29, Figure 11)
MIN
TYP
MAX
UNITS
V
-
40
-
dB
BAT
-48V SUPPLY
+5V SUPPLY
-5V SUPPLY
100mV
, 50Hz TO 4kHz
RMS
TIP
27
V
TX
19
PSRR = 20 log (VTX/VIN
)
R
T
R
L
V
600kΩ
TX
600Ω
R
RX
RING RSN
28 16
300kΩ
FIGURE 11. POWER SUPPLY REJECTION RATIO
Circuit Operation and Design Information
The HC5515 is a current feed voltage sense Subscriber Line
Interface Circuit (SLIC). This means that for short loop
For loop resistances that result in a tip to ring voltage less than
the saturation guard voltage the loop current is defined as:
applications the SLIC provides a programed constant current to
the tip and ring terminals while sensing the tip to ring voltage.
2.5V
-------------------------------------
I
=
× 1000
(EQ. 1)
L
R
+ R
DC2
DC1
The following discussion separates the SLIC’s operation into
its DC and AC paths, then follows up with additional circuit
and design information.
where: I = Constant loop current, and
L
R
and R
= Loop current programming resistors.
and R removes the VF
DC1
DC2
Capacitor C
between R
DC1
DC
DC2
Constant Loop Current (DC) Path
signals from the battery feed control loop. The value of C
is determined by Equation 2:
DC
SLIC in the Active Mode
The DC path establishes a constant loop current that flows
out of tip and into the ring terminal. The loop current is
1
1
(EQ. 2)
⎛
⎞
⎠
C
= T × --------------- + ---------------
DC
⎝
R
R
DC1
DC2
programmed by resistors R
, R and the voltage on
DC1 DC2
the R
pin (Figure 12). The R voltage is determined by
DC
DC
where T = 30ms.
the voltage across R in the saturation guard circuit. Under
1
constant current feed conditions, the voltage drop across R
NOTE: The minimum C
DC
value is obtained if R
= R .
DC2
DC1
1
sets the R
voltage to -2.5V. This occurs when current
DC
Figure 13 illustrates the relationship between the tip to ring
voltage and the loop resistance. For a 0Ω loop resistance
flows through R into the current source I . The R voltage
establishes a current (I
1
2
DC
/(R
) that is equal to V
RSN
RDC DC1
both tip and ring are at V
/2. As the loop resistance
BAT
+R
). This current is then multiplied by 1000, in the loop
DC2
increases, so does the voltage differential between tip and
ring. When this differential voltage becomes equal to the
saturation guard voltage, the operation of the SLIC’s loop
feed changes from a constant current feed to a resistive
feed. The loop current in the resistive feed region is no
longer constant but varies as a function of the loop
resistance.
current circuit, to become the tip and ring loop currents.
For the purpose of the following discussion, the saturation
guard voltage is defined as the maximum tip to ring voltage
at which the SLIC can provide a constant current for a given
battery and overhead voltage.
FN4235.6
June 6, 2006
8
HC5515
V
TX
I
+
-
RSN
R
R
R
RX
RSN
LOOP CURRENT
CIRCUIT
I
TIP
TIP
I
DC1
DC2
TIP
I
RING
RING
I
C
DC
RING
R
DC
SATURATION GUARD
CIRCUIT
-
-2.5V
+
-
+
A
2
I
A
1
I
R
1
-
+
17.3kΩ
2
R
SG
1
-5V
R
SG
HC5515
-5V
-5V
FIGURE 12. DC LOOP CURRENT
The Saturation Guard circuit (Figure 12) monitors the tip to
ring voltage via the transconductance amplifier A . A
generates a current that is proportional to the tip to ring
V
= -48V, I = 23mA, R
= 4.0kΩ
SG
BAT
L
0
-10
-20
-30
-40
-50
V
1
1
TIP
SATURATION
GUARD VOLTAGE
voltage difference. I is internally set to sink all of A ’s
1
1
CONSTANT CURRENT
FEED REGION
RESISTIVE FEED
REGION
current until the tip to ring voltage exceeds 12.5V. When the
tip to ring voltage exceeds 12.5V (with no R resistor) A
SG
1
supplies more current than I can sink. When this happens
1
A amplifies its input current by a factor of 12 and the current
2
through R becomes the difference between I and the
1
2
output current from A . As the current from A increases, the
2
2
voltage across R decreases and the output voltage on R
1
DC
decreases. This results in a corresponding decrease in the
loop current. The R pin provides the ability to increase the
SATURATION
GUARD VOLTAGE
V
RING
SG
saturation guard reference voltage beyond 12.5V. Equation
3 gives the relationship between the R resistor value and
∞
0
1.2K
LOOP RESISTANCE (Ω)
SG
FIGURE 13. V vs R
TR
L
the programmable saturation guard reference voltage:
Figure 14 shows the relationship between the saturation
guard voltage, the loop current and the loop resistance.
Notice from Figure 14 that for a loop resistance <1.2kΩ (R
= 4.0kΩ) the SLIC is operating in the constant current feed
region and for resistances >1.2kΩ the SLIC is operating in
the resistive feed region. Operation in the resistive feed
region allows long loop and off-hook transmission by
keeping the tip and ring voltages off the rails. Operation in
this region is transparent to the customer.
5
5 • 10
(EQ. 3)
V
= 12.5 + -----------------------------------
SGREF
R
+ 17300
SG
SG
where:
V
= Saturation Guard reference voltage, and
SGREF
R
= Saturation Guard programming resistor.
SG
When the Saturation guard reference voltage is exceeded,
the tip to ring voltage is calculated using Equation 4:
5
16.66 + 5 • 10 ⁄ (R
+ 17300)
50
SG
(EQ. 4)
CONSTANT CURRENT
FEED REGION
------------------------------------------------------------------------------------
= R ×
L
V
TR
V
= -48V, R
= 4.0kΩ
SG
R
+ (R
+ R
) ⁄ 600
DC2
BAT
L
DC1
40
30
20
10
0
SATURATION GUARD
where:
= Voltage differential between tip and ring, and
VOLTAGE, V = 38V
TR
V
TR
R = Loop resistance.
V
= -24V, R = ∞
SG
BAT
L
SATURATION GUARD
For on-hook transmission R = ∞, Equation 4 reduces to:
L
RESISTIVE FEED
REGION
VOLTAGE, V = 13V
TR
5
5 • 10
(EQ. 5)
V
= 16.66 + -----------------------------------
TR
R
+ 17300
0
10
20
LOOP CURRENT (mA)
30
SG
The value of R
should be calculated to allow maximum
SG
R
R
100kΩ
100kΩ
4kΩ
2kΩ
<1.2kΩ
<400Ω
R
R
= 4.0kΩ
= ∞Ω
L
L
SG
loop length operation. This requires that the saturation guard
reference voltage be set as high as possible without clipping
the incoming or outgoing VF signal. A voltage margin of -4V
1.5kΩ
700Ω
SG
FIGURE 14. V vs I and R
L
TR
L
FN4235.6
June 6, 2006
9
HC5515
on tip and -4V on ring, for a total of -8V margin, is
recommended as a general guideline. The value of R
calculated using Equation 6:
V
= Is the analog ground referenced receive signal,
= Is used to set the 4-wire to 2-wire gain,
RX
is
Z
E
SG
RX
= Is the AC open circuit voltage, and
G
⎛
⎞
⎜
⎟
⎟
Z = Is the line impedance.
L
5
⎜
⎜
⎜
⎜
⎝
5 • 10
(R
R
=
---------------------------------------------------------------------------------------------------------------------------------------------- – 17300
⎟
⎟
⎟
⎠
SG
+ R
)
⎛
⎞
(AC) 2-Wire Impedance
The AC 2-wire impedance (Z ) is the impedance looking
DC1
DC2
( V
– V
) × 1 + --------------------------------------------- – 16.66V
⎜
⎟
BAT
MAR
600R
⎝
⎠
L
TR
into the SLIC, including the fuse resistors, and is calculated
as follows:
(EQ. 6)
where:
Let V
= 0. Then from Equation 10:
RX
V
V
= Battery voltage, and
BAT
= Voltage Margin. Recommended value of -8V to
I
MAR
(EQ. 12)
(EQ. 13)
M
------------
V
= Z
•
TX
T
allow a maximum overload level of 3.1V
.
1000
PEAK
For on-hook transmission R = ∞, Equation 6 reduces to:
Z
is defined as:
L
TR
5
5 • 10
– V
V
R
= ----------------------------------------------------------------- – 17300
TR
(EQ. 7)
SG
Z
= -----------
V
– 16.66V
TR
BAT
MAR
I
M
Substituting in Equation 9 for V
:
TR
SLIC in the Standby Mode
Overall system power is saved by configuring the SLIC in the
standby state when not in use. In the standby state the tip
and ring amplifiers are disabled and internal resistors are
V
2R • I
F M
TX
(EQ. 14)
Z
= ---------- + -----------------------
TR
I
I
M
M
Substituting in Equation 12 for V
:
connected between tip to ground and ring to V
. This
TX
BAT
connection enables a loop current to flow when the phone
goes off-hook. The loop current detector then detects this
current and the SLIC is configured in the active mode for
voice transmission. The loop current in standby state is
calculated as follows:
Z
T
1000
(EQ. 15)
(EQ. 16)
Z
= ------------ + 2R
TR
F
Therefore:
Z
= 1000 • (Z
– 2R )
T
TR
F
V
– 3V
BAT
(EQ. 8)
-------------------------------
≈
I
Equation 16 can now be used to match the SLIC’s
L
R
+ 1800Ω
L
impedance to any known line impedance (Z ).
TR
where:
I = Loop current in the standby state,
Example:
L
Calculate Z to make Z = 600Ω in series with 2.16µF.
T
TR
R = Loop resistance, and
L
R = 20Ω.
F
V
= Battery voltage.
BAT
⎛
⎞
1
Z
= 1000 • 600 + ----------------------------------------- – 2 • 20
⎜
⎝
⎟
T
–6
⎠
(AC) Transmission Path
jω • 2.16 • 10
SLIC in the Active Mode
Z = 560kΩ in series with 2.16nF.
T
Figure 15 shows a simplified AC transmission model. Circuit
analysis yields the following design equations:
(AC) 2-Wire to 4-Wire Gain
The 2-wire to 4-wire gain is equal to V / V
TX TR
.
(EQ. 9)
(EQ. 10)
(EQ. 11)
V
= V + I • 2R
TR
TX
M
F
From Equations 9 and 10 with V
RX
= 0:
V
Z ⁄ 1000
T
Z ⁄ 1000 + 2R
T F
V
V
I
TX
TX
RX
M
(EQ. 17)
A
= ----------- = -----------------------------------------
---------- + ----------- = ------------
2 – 4
V
Z
Z
1000
= E – I • Z
L
TR
T
RX
V
TR
G
M
(AC) 4-Wire to 2-Wire Gain
where:
= Is the AC metallic voltage between tip and ring,
The 4-wire to 2-wire gain is equal to V /V
.
TR RX
From Equations 9, 10 and 11 with E = 0:
V
TR
including the voltage drop across the fuse resistors R ,
G
F
Z
V
Z
T
Z
RX
L
TR
--------------------------------------------
A
= ----------- = –---------- •
V
= Is the AC metallic voltage. Either at the ground
4 – 2
TX
referenced 4-wire side or the SLIC tip and ring terminals,
Z
V
(EQ. 18)
T
RX
------------ + 2R + Z
F
L
1000
I
= Is the AC metallic current,
M
R = Is a fuse resistor,
F
Z = Is used to set the SLIC’s 2-wire impedance,
T
FN4235.6
June 6, 2006
10
HC5515
I
M
TIP
A = 250
R
F
Z
L
V
TX
+
-
Z
TR
+
TX
-
+
1
V
V
TR
+
TX
-
V
+
-
Z
T
E
G
-
I
M
A = 4
RSN
Z
A = 250
RX
R
I
F
M
RING
+
RX
1000
V
-
HC5515
FIGURE 15. SIMPLIFIED AC TRANSMISSION CIRCUIT
For applications where the 2-wire impedance (Z
,
Example:
Given: R = 20kΩ, Z
TR
Equation 15) is chosen to equal the line impedance (Z ), the
L
= 280kΩ, Z = 562kΩ (standard
TX
RX
T
expression for A
simplifies to:
4-2
value), R = 20Ω and Z = 600Ω,
F
Z
1
2
T
(EQ. 19)
The value of Z = 18.7kΩ
--
A
= –---------- •
B
4 – 2
Z
RX
R
FB
(AC) 4-Wire to 4-Wire Gain
The 4-wire to 4-wire gain is equal to V /V
I
2
R
V
TX
TX
.
TX RX
From Equations 9, 10 and 11 with E = 0:
-
+
G
+
TX
I
1
V
Z
+ 2R
F
V
Z
T
Z
RX
L
TX
-
--------------------------------------------
A
= ----------- = –---------- •
(EQ. 20)
4 – 4
Z
V
T
RX
------------ + 2R + Z
Z
Z
B
F
L
HC5515
T
1000
+
RX
V
-
RSN
Transhybrid Circuit
Z
RX
The purpose of the transhybrid circuit is to remove the receive
signal (V ) from the transmit signal (V ), thereby preventing
an echo on the transmit side. This is accomplished by using an
external op amp (usually part of the CODEC) and by the
inversion of the signal from the 4-wire receive port (RSN) to the
CODEC/
FILTER
RX
TX
FIGURE 16. TRANSHYBRID CIRCUIT
4-wire transmit port (V ). Figure 16 shows the transhybrid
TX
circuit. The input signal will be subtracted from the output signal
Supervisory Functions
The loop current and the ring trip detector outputs are
if I equals I . Node analysis yields the following equation:
1
2
multiplexed to a single logic output pin called DET. See
V
V
RX
Z
B
TX
(EQ. 21)
----------- + ----------- = 0
Table 1 to determine the active detector for a given logic
input. For further discussion of the logic circuitry see section
titled “Digital Logic Inputs”.
R
TX
The value of Z is then:
B
V
Before proceeding with an explanation of the loop current
detector and the longitudinal impedance, it is important to
understand the difference between a “metallic” and
“longitudinal” loop currents. Figure 17 illustrates 3 different
types of loop current encountered.
RX
(EQ. 22)
-----------
Z
= –R
•
TX
B
V
TX
Where V /V equals 1/ A
RX TX
.
4-4
Therefore:
Z
T
Case 1 illustrates the metallic loop current. The definition of
a metallic loop current is when equal currents flow out of tip
and into ring. Loop current is a metallic current.
------------ + 2R + Z
Z
F
L
(EQ. 23)
1000
RX
---------- --------------------------------------------
Z
= R
•
TX
•
B
Z
Z + 2R
L F
T
FN4235.6
June 6, 2006
11
HC5515
Cases 2 and 3 illustrate the longitudinal loop current. The
definition of a longitudinal loop current is a common mode
current, that flows either out of or into tip and ring
Taking into account the hysteresis voltage, the typical value
of R for the off-hook to on-hook condition is:
D
375
R
= --------------------------------------------------------------------------
(EQ. 26)
D
I
simultaneously. Longitudinal currents in the on-hook state result
OFF – HOOK to ON – HOOK
in equal currents flowing through the sense resistors R and
1
A filter capacitor (C ) in parallel with R will improve the
accuracy of the trip point in a noisy environment. The value
of this capacitor is calculated using the following Equation:
R (Figure 17). And longitudinal currents in the off-hook state
D
D
2
result in unequal currents flowing through the sense resistors
R and R . Notice that for case 2, longitudinal currents flowing
1
2
T
R
D
away from the SLIC, the current through R is the metallic loop
current plus the longitudinal current; whereas the current
1
C
= -------
(EQ. 27)
D
through R is the metallic loop current minus the longitudinal
current. Longitudinal currents are generated when the phone
line is influenced by magnetic fields (e.g., power lines).
2
where: T = 0.5ms.
Ring Trip Detector
Ring trip detection is accomplished with the internal ring trip
comparator and the external circuitry shown in Figure 18.
The process of ring trip is initiated when the logic input pins
are in the following states: E0 = 0, C1 = 1 and C2 = 0. This
logic condition connects the ring trip comparator to the DET
output, and causes the Ringrly pin to energize the ring relay.
The ring relay connects the tip and ring of the phone to the
external circuitry in Figure 18. When the phone is on-hook
the DT pin is more positive than the DR pin and the DET
output is high. For off-hook conditions DR is more positive
than DT and DET goes low. When DET goes low, indicating
that the phone has gone off-hook, the SLIC is commanded
by the logic inputs to go into the active state. In the active
state, tip and ring are once again connected to the phone
and normal operation ensues.
Loop Current Detector
Figure 17 shows a simplified schematic of the loop current
detector. The loop current detector works by sensing the
metallic current flowing through resistors R and R . This
1
2
results in a current (I ) out of the transconductance
RD
amplifier (gm ) that is equal to the product of gm and the
1
1
metallic loop current. I
then flows out the R pin and
RD
D
through resistor R to V . The value of I
EE
is equal to:
RD
D
I
– I
I
L
300
TIP
RING
(EQ. 24)
I
= ----------------------------------- = ---------
RD
600
The I
RD
current results in a voltage drop across R that is
D
compared to an internal 1.25V reference voltage. When the
voltage drop across R exceeds 1.25V, and the logic is
D
configured for loop current detection, the DET pin goes low.
Figure 18 illustrates battery backed unbalanced ring injected
ringing. For tip injected ringing just reverse the leads to the
phone. The ringing source could also be balanced.
The hysteresis resistor R adds an additional voltage
H
effectively across R , causing the on-hook to off-hook
D
threshold to be slightly higher than the off-hook to on-hook
threshold.
NOTE: The DET output will toggle at 20Hz because the DT input is
not completely filtered by C . Software can examine the duty cycle
RT
Taking into account the hysteresis voltage, the typical value
of R for the on-hook to off-hook condition is:
D
and determine if the DET pin is low for more that half the time, if so
the off-hook condition is indicated.
465
R
= --------------------------------------------------------------------------
(EQ. 25)
D
I
ON – HOOK to OFF – HOOK
gm (I
)
METALLIC
1
R
D
R
H
+
-
I
RD
C
D
R
CURRENT
LOOP
COMPARATOR
D
+
-
+
TIP
-
V
R
R
REF
1.25V
1
2
V
EE
gm
1
-5V
RING
CASE 1
CASE 2
CASE 3
DIGITAL MULTIPLEXER
DET
-
+
I
I
I
LONGITUDINAL
METALLIC LONGITUDINAL
←
←
→
HC5515
FIGURE 17. LOOP CURRENT DETECTOR
FN4235.6
June 6, 2006
12
HC5515
transconductance amplifiers GT and GR. The output of GT
and GR are the differential currents DI1 and DI2, which in
turn feed the differential inputs of current sources IT and IR
respectively. IT and IR have current gains of 250 single
ended and 500 differentially, thus leading to a change in IT
and IR that is equal to 500(DI) and 500(DI2).
R
R
R
C
RT
1
2
RT
DT
DR
-
DET
R
+
3
RING TRIP
COMPARATOR
TIP
R
4
The circuit shown in Figure 19(B) illustrates the tip side of
the longitudinal network. The advantages of a differential
input current source are: improved noise since the noise due
E
RG
V
BAT
to current source 2I is now correlated, power savings due
O
to differential current gain and minimized offset error at the
Operational Amplifier inputs via the two 5kΩ resistors.
RING
RINGRLY
HC5515
RING
RELAY
Digital Logic Inputs
FIGURE 18. RING TRIP CIRCUIT FOR BATTERY BACKED
RINGING
Table 1 is the logic truth table for the TTL compatible logic
input pins. The HC5515 has an enable input pin (E0) and
two control inputs pins (C1, C2).
Longitudinal Impedance
The enable pin E0 is used to enable or disable the DET
output pin. The DET pin is enabled if E0 is at a logic level 0
and disabled if E0 is at a logic level 1.
The feedback loop described in Figure 19(A, B) realizes the
desired longitudinal impedances from tip to ground and from
ring to ground. Nominal longitudinal impedance is resistive
and in the order of 22Ω.
A combination of the control pins C1 and C2 is used to select
1 of the 4 possible operating states. A description of each
operating state and the control logic follow:
In the presence of longitudinal currents this circuit attenuates
the voltages that would otherwise appear at the tip and ring
terminals, to levels well within the common mode range of
the SLIC. In fact, longitudinal currents may exceed the
programmed DC loop current without disturbing the SLIC’s
VF transmission capabilities.
Open Circuit State (C1 = 0, C2 = 0)
In this state the SLIC is effectively off. All detectors and
both the tip and ring line drive amplifiers are powered
down, presenting a high impedance to the line. Power
dissipation is at a minimum.
The function of this circuit is to maintain the tip and ring
voltages symmetrically around V
/2, in the presence of
BAT
Active State (C1 = 0, C2 = 1)
longitudinal currents. The differential transconductance
amplifiers G and G accomplish this by sourcing or sinking
The tip output is capable of sourcing loop current and for
open circuit conditions is about -4V from ground. The ring
output is capable of sinking loop current and for open circuit
T
R
the required current to maintain V at V
/2.
C
BAT
When a longitudinal current is injected onto the tip and ring
inputs, the voltage at VC moves from it’s equilibrium value
conditions is about V
normal. The loop current detector is active, E0 determines if
the detector is gated to the DET output.
+4V. VF signal transmission is
BAT
V
/2. When VC changes by the amount DVC, this change
BAT
appears between the input terminals of the differential
I
LONG
TIP CURRENT SOURCE
WITH DIFFERENTIAL INPUTS
I
I
LONG
T
TIP
20Ω
+
∆I
1
∆I
TIP
1
∆V
T
-
5kΩ
5kΩ
G
T
R
-
LARGE
+
R
V
/2
BAT
LARGE
+
-
V
∆I
C
∆I
1
1
G
R
V
C
V
/2
BAT
R
LARGE
I
LONG
∆I
∆I
2
2
2I
0
RING
HC5515
R
LARGE
+
I
R
I
∆V
TIP DIFFERENTIAL
TRANSCONDUCTANCE AMPLIFIER
LONG
R
-
RING
FIGURE 19A.
FIGURE 19. LONGITUDINAL IMPEDANCE NETWORK
FIGURE 19B.
FN4235.6
June 6, 2006
13
HC5515
operating conditions and allows negative surges to be
returned to system ground.
Ringing State (C1 = 1, C2 = 0)
The ring relay driver and the ring trip detector are activated.
Both the tip and ring line drive amplifiers are powered down.
Both tip and ring are disconnected from the line via the
external ring relay.
The fuse resistors (R ) serve a dual purpose of being
F
nondestructive power dissipaters during surge and fuses
when the line in exposed to a power cross.
Standby State (C1 = 1, C2 = 1)
Power-Up Sequence
Both the tip and ring line drive amplifiers are powered down.
Internal resistors are connected between tip to ground and ring
The HC5515 has no required power-up sequence. This is a
result of the Dielectrically Isolated (DI) process used in the
fabrication of the part. By using the DI process, care is no
longer required to insure that the substrate be kept at the
most negative potential as with junction isolated ICs.
to V
to allow loop current detect in an off-hook condition.
BAT
The loop current and ground key detectors are both active, E0
determines if the detector is gated to the DET output.
AC Transmission Circuit Stability
To ensure stability of the AC transmission feedback loop two
Printed Circuit Board Layout
Care in the printed circuit board layout is essential for proper
operation. All connections to the RSN pin should be made as
close to the device pin as possible, to limit the interference
that might be injected into the RSN terminal. It is good
practice to surround the RSN pin with a ground plane.
compensation capacitors C and C
Figure 20 (Application Circuit) illustrates their use.
Recommended value is 2200pF.
are required.
TC RC
AC-DC Separation Capacitor, C
HP
The high pass filter capacitor connected between pins HPT
and HPR provides the separation between circuits sensing
tip to ring DC conditions and circuits processing AC signals.
The analog and digital grounds should be tied together at the
device.
A 10nf C
will position the low end frequency response
HP
3dB break point at 48Hz. Where:
1
(EQ. 28)
f
= ----------------------------------------------------
3dB
(2 • π • R
• C
)
HP
HP
where R
= 330kΩ.
HP
Thermal Shutdown Protection
The HC5515’s thermal shutdown protection is invoked if a
fault condition on the tip or ring causes the temperature of
the die to exceed 160°C. If this happens, the SLIC goes into
a high impedance state and will remain there until the
temperature of the die cools down by about 20°C. The SLIC
will return back to its normal operating mode, providing the
fault condition has been removed.
Surge Voltage Protection
The HC5515 must be protected against surge voltages and
power crosses. Refer to “Maximum Ratings” TIPX and
RINGX terminals for maximum allowable transient tip and
ring voltages. The protection circuit shown in Figure 20
utilizes diodes together with a clamping device to protect tip
and ring against high voltage transients.
Positive transients on tip or ring are clamped to within a
couple of volts above ground via diodes D and D . Under
1
2
normal operating conditions D and D are reverse biased
1
2
and out of the circuit.
Negative transients on tip and ring are clamped to within a
couple of volts below ground via diodes D and D with the
3
4
help of a Surgector. The Surgector is required to block
conduction through diodes D and D under normal
3
4
FN4235.6
June 6, 2006
14
HC5515
SLIC Operating States
TABLE 1. LOGIC TRUTH TABLE
E0
0
C1
0
C2
0
SLIC OPERATING STATE
ACTIVE DETECTOR
DET OUTPUT
Logic Level High
Open Circuit
Active
No Active Detector
Loop Current Detector
Ring Trip Detector
0
0
1
Loop Current Status
Ring Trip Status
0
1
0
Ringing
0
1
1
Standby
Loop Current Detector
Loop Current Status
1
1
1
1
0
0
1
1
0
1
0
1
Open Circuit
Active
No Active Detector
Loop Current Detector
Ring Trip Detector
Logic Level High
Ringing
Standby
Loop Current Detector
BFLE = 20 • log (E /V ), E = source is removed.
RX TR
L
Notes
where: E , V and E are defined in Figure 5.
RX TR
L
2. Overload Level (Two-Wire port) - The overload level is
specified at the 2-wire port (V ) with the signal source at the
11. Two-Wire Return Loss - The 2-wire return loss is computed
TR0
4-wire receive port (E ). I
= 30mA, R
= 4kΩ,
using the following equation:
RX
increase the amplitude of E
DCMET
until 1% THD is measured at
SG
RX
r = -20 • log (2V /V ).
M
S
V
. Reference Figure 1.
TRO
where: Z = The desired impedance; e.g., the characteristic
D
impedance of the line, nominally 600Ω. (Reference Figure 6).
3. LongitudinalImpedance - The longitudinal impedance is
computed using the following equations, where TIP and RING
voltages are referenced to ground. L , L , V , V , A and
12. Overload Level (4-Wire port) - The overload level is specified
ZT ZR
T
R
R
A
are defined in Figure 2.
at the 4-wire transmit port (V
) with the signal source (E ) at
T
TXO
= 23mA, Z = 20kΩ, R
G
the 2-wire port, I
= 4kΩ (Refer-
DCMET
L
SG
(TIP) L = V /A ,
ZT
T
T
ence Figure 7). Increase the amplitude of E until 1% THD is
G
(RING) L = V /A ,
ZR
measured at V
. Note that the gain from the 2-wire port to
R
R
TXO
the 4-wire port is equal to 1.
where: E = 1V
(0Hz to 100Hz).
L
RMS
4. Longitudinal Current Limit (Off-Hook Active) - Off-Hook
(Active, C = 1, C = 0) longitudinal current limit is determined
13. Output Offset Voltage - The output offset voltage is specified
with the following conditions: E = 0, I
= 23mA, Z = ∞
G
DCMET
, V and Z are defined
L
1
2
and is measured at V . E , I
TX
DCMET
G
DCMET TX
L
by increasing the amplitude of E (Figure 3A) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains low
(no false detection).
L
in Figure 7. Note: I
is established with a series 600Ω
resistor between tip and ring.
14. Two-Wire to Four-Wire (Metallic to V ) Voltage Gain - The
TX
5. Longitudinal Current Limit (On-Hook Standby) - On-Hook
2-wire to 4-wire (metallic to V ) voltage gain is computed
TX
(Active, C = 1, C = 1) longitudinal current limit is determined
1
2
using the following equation.
by increasing the amplitude of E (Figure 3B) until the 2-wire
L
longitudinal balance drops below 45dB. DET pin remains high
(no false detection).
G
= (V /V ), E = 0dBm0, V , V , and E are defined
TX TR TX TR
2-4
in Figure 7.
G
G
6. Longitudinal to Metallic Balance - The longitudinal to metallic
15. Current Gain RSN to Metallic - The current gain RSN to
balance is computed using the following equation:
Metallic is computed using the following equation:
BLME = 20 • log (E /V ), where: E and V
TR TR
Figure 4.
are defined in
K = I [(R
DC1
+ R
DC2
are defined in Figure 8.
)/(V
- V
)] K, I , R
DC1
, R ,
DC2
L
L
M
RDC
RSN
M
V
and V
RDC
RSN
7. Metallic to Longitudinal FCC Part 68, Para 68.310 - The
16. Two-Wire to Four-Wire Frequency Response - The 2-wire to
metallic to longitudinal balance is defined in this spec.
4-wire frequency response is measured with respect to
E
= 0dBm at 1.0kHz, E
= 0V, I = 23mA. The
G
RX
DCMET
8. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire
frequency response is computed using the following equation:
balance is computed using the following equation:
F
= 20 • log (V /V ), vary frequency from 300Hz to
2-4
TX TR
BLFE = 20 • log (E /V ),: E and V are defined in Figure 4.
TX TX
L
L
3.4kHz and compare to 1kHz reading.
9. Metallic to Longitudinal Balance - The metallic to
V
, V , and E are defined in Figure 9.
TX TR
G
longitudinal balance is computed using the following equation:
17. Four-Wire to Two-Wire Frequency Response - The 4-wire to
BMLE = 20 • log (E /V ), E
TR RX
= 0,
L
2-wire frequency response is measured with respect to
where: E , V and E are defined in Figure 5.
E
= 0dBm at 1.0kHz, E = 0V, I
= 23mA. The
TR
L
RX
RX
G
DCMET
frequency response is computed using the following equation:
10. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal
F
= 20 • log (V /E ), vary frequency from 300Hz to
balance is computed using the following equation:
4-2
TR RX
FN4235.6
June 6, 2006
15
HC5515
3.4kHz and compare to 1kHz reading.
and E are defined in Figure 9.
E
= -10dBm, 1.0kHz signal, E = 0, I = 23mA and is
DCMET
RX
G
computed using the following equation:
V
TR
RX
G
= 20 • log (V /E ) vary amplitude -40dBm to +3dBm, or
TR RX
4-2
18. Four-Wire to Four-Wire Frequency Response - The 4-wire
-55dBm to -40dBm and compare to -10dBm reading.
to 4-wire frequency response is measured with respect to
V
and E are defined in Figure 9. The level is specified at
E
= 0dBm at 1.0kHz, E = 0V, I
= 23mA. The
TR
RX
RX
G
DCMET
the 4-wire receive port and referenced to a 600Ω impedance
frequency response is computed using the following equation:
level.
F
= 20 • log (V /E ), vary frequency from 300Hz to
TX RX
4-4
3.4kHz and compare to 1kHz reading.
23. Two-Wire Idle Channel Noise - The 2-wire idle channel noise
at V
is specified with the 2-wire port terminated in 600Ω (R )
TR
L
V
and E are defined in Figure 9.
TX
19. Two-Wire to Four-Wire Insertion Loss - The 2-wire to 4-wire
insertion loss is measured with respect to E = 0dBm at 1.0kHz
RX
and with the 4-wire receive port grounded (Reference Figure 10).
24. Four-Wire Idle Channel Noise - The 4-wire idle channel noise
G
at V is specified with the 2-wire port terminated in 600Ω (R ).
TX
L
input signal, E
the following equation:
= 0, I = 23mA and is computed using
RX
DCMET
The noise specification is with respect to a 600Ω impedance
level at V . The 4-wire receive port is grounded (Reference
TX
L
= 20 • log (V /V )
TX TR
Figure 10).
2-4
where: V , V , and E are defined in Figure 9. (Note: The
TX TR
25. Harmonic Distortion (2-Wire to 4-Wire) - The
harmonic
G
fuse resistors, R , impact the insertion loss. The specified
distortion is measured with the following conditions.
F
insertion loss is for R = 0).
F
E
V
= 0dBm at 1kHz, I
= 23mA. Measurement taken at
G
DCMET
. (Reference Figure 7).
TX
20. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire
insertion loss is measured based upon E
= 0dBm, 1.0kHz
26. Harmonic Distortion (4-Wire to 2-Wire) - The
harmonic
RX
= 23mA and is computed using
input signal, E = 0, I
distortion is measured with the following conditions. E
0dBm0. Vary frequency between 300Hz and 3.4kHz, I
=
=
G
DCMET
RX
DCMET
the following equation:
23mA. Measurement taken at V . (Reference Figure 9).
TR
L
= 20 • log (V /E ),
TR RX
4-2
27. Constant Loop Current - The constant loop current is
where: V and E are defined in Figure 9.
TR
RX
calculated using the following equation:
21. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire
I
= 2500 / (R
+ R ).
DC2
L
DC1
gain tracking is referenced to measurements taken for
E
= -10dBm, 1.0kHz signal, E
= 0, I = 23mA and is
G
RX
DCMET
28. Standby State Loop Current - The standby state loop current
computed using the following equation.
is calculated using the following equation:
G
= 20 • log (V /V ) vary amplitude -40dBm to +3dBm, or
TX TR
2-4
I
= [|V | - 3] / [R +1800], T = 25°C.
BAT L A
L
-55dBm to -40dBm and compare to -10dBm reading.
29. Power Supply Rejection Ratio - Inject a 100mV
signal
RMS
supplies. PSRR is
V
and V are defined in Figure 9.
TX
TR
(50Hz to 4kHz) on V
, V
and V
BAT
CC EE
computed using the following equation:
22. Four-Wire to Two-Wire Gain Tracking - The 4-wire to 2-wire
gain tracking is referenced to measurements taken for
PSRR = 20 • log (V /V ). V and V are defined in Figure 11.
TX IN TX IN
Pin Descriptions
PLCC
SYMBOL
DESCRIPTION
Internally connected to output of RING power amplifier.
1
2
RING
SENSE
BGND
Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
4
5
6
7
8
9
V
+5V power supply.
CC
RINGRLY
Ring relay driver output.
V
Battery supply voltage, -24V to -56V.
BAT
R
Saturation guard programming resistor pin.
This pin is used during manufacturing. This pin is to be left open for proper SLIC operation.
SG
NC
E0
TTL compatible logic input. Enables the DET output when set to logic level zero and disables DET output when set to
a logic level one.
11
12
DET
C2
Detector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered (see
Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET output is
an open collector with an internal pull-up of approximately 15kΩ to V
CC.
TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing
or Standby) of the SLIC.
FN4235.6
June 6, 2006
16
HC5515
Pin Descriptions (Continued)
PLCC
SYMBOL
DESCRIPTION
13
C1
TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing
or Standby) of the SLIC.
14
R
DC feed current programming resistor pin. Constant current feed is programmed by resistors R
DC1
and R
DC2
DC
connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to AGND
to isolate the AC signal components.
15
16
AGND
RSN
Analog ground.
Receive Summing Node. The AC and DC current flowing into this pin establishes the metallic loop current that flows
between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into the RSN
pin. The constant current programming resistors and the networks for program receive gain and 2-wire impedance all
connect to this pin.
18
19
V
V
-5V power supply.
EE
Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming the
2-wire input impedance connects between this pin and RSN.
TX
20
21
22
23
25
HPR
HPT
RD
RING side of AC/DC separation capacitor C . C
is required to properly separate the ring AC current from the DC
is connected to HPT.
HP HP
loop current. The other end of C
HP
TIP side of AC/DC separation capacitor C . C is required to properly separate the tip AC current from the DC loop
HP HP
current. The other end of C
is connected to HPR.
HP
Loop current programming resistor. Resistor R sets the trigger level for the loop current detect circuit. A filter capacitor
D
C
is also connected between this pin and V
.
D
EE
DT
Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in
the SLIC with inputs DT and DR.
DR
Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in
the SLIC with inputs DT and DR.
26
27
28
TIP
Internally connected to output of tip power amplifier.
Output of tip power amplifier.
SENSE
TIPX
RINGX
N/C
Output of ring power amplifier.
3, 10 17,
24
No internal connection.
FN4235.6
June 6, 2006
17
HC5515
Pinout
HC5515
(PLCC)
TOP VIEW
4
3
2
1
28 27 26
RINGRLY
5
6
25 DR
24 N/C
23 DT
V
BAT
R
7
SG
8
NC
22 RD
21 HPT
20 HPR
9
E0
10
11
N/C
DET
19 V
TX
12 13 14 15 16 17 18
FN4235.6
June 6, 2006
18
HC5515
Application Circuit
C
(NOTE 32)
HP
R
C
R
RT
RT
1
2
R
U
FB
R
3
R
D
U
1
21 HPT
HPR 20
2
-5V
R
R
R
TX
4
22 RD
23 DT
V
V
19
18
-
TX
+
-5V
R
R
B
EE
T
V
BAT
R
RX
25 DR
RSN 16
AGND 15
PTC
PTC
R
F1
27 TIPX
R
DC1
D
D
TIP
D
1
2
3
CODEC/FILTER
C
TC
2 BGND
R
14
DC
NOTE 31
R
C
DC
DC2
C
4 V
C1 13
C2 12
RC
CC
D
RING
4
28 RINGX
R
Surgector
F2
V
BAT
K
A
DET 11
6 V
BAT
G
5 RINGRLY
E
9
8
O
D
5
R
SG
E
7 R
1
SG
RINGING
+ 90V
+5V
OR
12V
RELAY
-5V
(V
)
RMS
BAT
D
6
R , R 200kΩ, 5%, 1/4W
U1 SLIC (Subscriber Line Interface Circuit)
HC5515
1
3
R
R
910kΩ, 5%, 1/4W
1.2MΩ, 5%, 1/4W
18.7kΩ,1%, 1/4W
39kΩ, 5%, 1/4W
2
U2 Combination CODEC/Filter e.g.
CD22354A or Programmable CODEC/
Filter, e.g. SLAC
4
R
B
D
R
C
1.5µF, 20%, 10V
DC
R
, R
41.2kΩ, 5%, 1/4W
20.0kΩ, 1%, 1/4W
280kΩ, 1%, 1/4W
562kΩ, 1%, 1/4W
20kΩ, 1%, 1/4W
150Ω, 5%, 2W
DC1 DC2
C
10nF, 20%, 100V (Note 2)
0.39µF, 20%, 100V
2200pF, 20%, 100V
HP
R
FB
C
RT
R
RX
C
, C
TC RC
R
T
TX
RT
Relay Relay, 2C Contacts, 5V or 12V Coil
D - D IN4007 Diode
R
1
5
R
Surgector SGT27S10
R
V
V
= -28V, R
= -48V, R
= ∞
SG BAT
SG
SG
PTC Polyswitch TR600-150
= 4.0kΩ, 1/4W 5%
BAT
D
Diode, 1N4454
6
R
, R
Line Resistor, 20Ω, 1% Match, 2 W
Carbon column resistor or thick film on
ceramic
F1 F2
NOTES:
30. It is recommended that the anodes of D and D be shorted to ground through a battery referenced surgector (SGT27S10).
3
4
31. To meet the specified 25dB 2-wire return loss at 200Hz, C
needs to be 20nF, 20%, 100V.
HP
FIGURE 20. APPLICATION CIRCUIT
FN4235.6
June 6, 2006
19
HC5515
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
N28.45 (JEDEC MS-018AB ISSUE A)
PIN (1) IDENTIFIER
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.025 (0.64)
0.045 (1.14)
0.050 (1.27) TP
R
INCHES
MILLIMETERS
C
L
SYMBOL
MIN
MAX
MIN
4.20
MAX
4.57
NOTES
A
A1
D
0.165
0.090
0.485
0.450
0.191
0.485
0.450
0.191
0.180
0.120
0.495
0.456
0.219
0.495
0.456
0.219
-
D2/E2
D2/E2
2.29
3.04
-
12.32
11.43
4.86
12.57
11.58
5.56
-
C
L
E1 E
D1
D2
E
3
4, 5
VIEW “A”
12.32
11.43
4.86
12.57
11.58
5.56
-
E1
E2
N
3
0.020 (0.51)
MIN
4, 5
6
A1
D1
D
28
28
A
Rev. 2 11/97
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
-C-
4. To be measured at seating plane
contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4235.6
June 6, 2006
20
相关型号：
©2020 ICPDF网 联系我们和版权申明