HC55185AIMZ [INTERSIL]
VoIP Ringing SLIC Family; 网络电话振铃SLIC家庭
| 型号： | HC55185AIMZ |
| 厂家： | 
Intersil |
| 描述： | VoIP Ringing SLIC Family |
| 文件： | 总20页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC55185
®
Data Sheet
December 18, 2006
FN4831.14
VoIP Ringing SLIC Family
Features
The RSLIC-VoIP family of
ringing subscriber line
interface circuits (RSLIC)
supports analog Plain Old
Telephone Service (POTS) in
• Onboard Ringing Generation
• Compatible with Existing HC5518x Devices
• Low Standby Power Consumption (75V, 65mW)
• Reduced Idle Channel Noise
short and medium loop length, wireless and wireline
• Programmable Transient Current Limit
• Improved Off Hook Software Interface
• Integrated MTU DC Characteristics
• Low External Component Count
applications. Ideally suited for remote subscriber units, this
family of products offers flexibility to designers with high
ringing voltage and low power consumption system
requirements.
The RSLIC-VoIP family operates to 100V which translates
directly to the amount of ringing voltage supplied to the end
subscriber. With the high operating voltage, subscriber loop
lengths can be extended to 500Ω (i.e., 5,000 feet) and
beyond.
• Silent Polarity Reversal
• Pulse Metering and On Hook Transmission
• Tip Open Ground Start Operation
• Balanced and Unbalanced Ringing
• Thermal Shutdown with Alarm Indicator
• 28 Lead Surface Mount Packaging
• Reduced Footprint Micro Leadframe Packaging
• Dielectric Isolated (DI) High Voltage Design
• QFN Package Option
Other key features across the product family include: low
power consumption, ringing using sinusoidal or trapezoidal
waveforms, robust auto-detection mechanisms for when
subscribers go on or off hook, and minimal external discrete
application components. Integrated test access features are
also offered on selected products to support loopback
testing as well as line measurement tests.
There are five product offerings of the HC55185 with each
version providing voltage grades of high battery voltage and
longitudinal balance. The voltage feed amplifier design uses
low fixed loop gains to achieve high analog performance
with low susceptibility to system induced noise.
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip Scale Package Footprint; Improves PCB
efficiency and has a thinner profile
• Pb-free plus anneal available (RoHS compliant)
Block Diagram
Applications
POL
CDC
VBL
VBH
• Voice Over Internet Protocol (VoIP)
• Cable Modems
ILIM
DC
BATTERY
SWITCH
RINGING
PORT
VRS
CONTROL
• Voice Over DSL (VoDSL)
• Short Loop Access Platforms
• Remote Subscriber Units
• Terminal Adapters
2-WIRE
PORT
TIP
VRX
VTX
-IN
RING
TRANSMIT
SENSING
4-WIRE
PORT
TRANSIENT
CURRENT
LIMIT
VFB
TL
Related Literature
• AN9814, User’s Guide for Development Board
F2
F1
F0
SW+
SW-
TEST
ACCESS
DETECTOR
LOGIC
CONTROL
LOGIC
• AN9824, Modeling of the AC Loop
• Interfacing to DSP CODECs (Contact Factory)
• TB379 Thermal Characterization of Packages for ICs
RTD RD E0 DETALM
BSEL SWC
• AN9922, Thermal Characterization and Modeling of the
RSLIC18 in the Micro Leadframe Package
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001-2006. All Rights Reserved. RSLIC18™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
1
HC55185
Ordering Information
LONGITUDINAL
BALANCE
HIGH BATTERY (VBH)
FULL
TEMP.
PKG.
PART NUMBER
HC55185AIM*
PART MARKING
100V
85V
75V
58dB
53dB
TEST RANGE (°C)
PACKAGE
-40 to +85 28 Ld PLCC
-40 to +85 28 Ld PLCC (Pb-free) N28.45
-40 to +85 28 Ld PLCC N28.45
-40 to +85 28 Ld PLCC (Pb-free) N28.45
-40 to +85 28 Ld PLCC N28.45
-40 to +85 28 Ld PLCC (Pb-free) N28.45
-40 to +85 28 Ld PLCC N28.45
-40 to +85 28 Ld PLCC (Pb-free) N28.45
DWG. #
HC55185 AIM
HC55185 AIMZ
HC55185 BIM
HC55185 BIMZ
HC55185 CIM
HC55185 CIMZ
HC55185 DIM
HC55185 DIMZ
HC55185 ECM
N28.45
•
•
•
•
•
•
•
•
•
•
•
•
•
•
HC55185AIMZ* (Note)
HC55185BIM*
•
•
HC55185BIMZ* (Note)
HC55185CIM*
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
HC55185CIMZ* (Note)
HC55185DIM*
•
•
HC55185DIMZ* (Note)
HC55185ECM*
0 to +75
0 to +75
0 to +75
0 to +75
0 to +85
0 to +85
0 to +85
0 to +85
28 Ld PLCC
N28.45
•
•
•
•
•
•
•
•
HC55185ECMZ* (Note) HC55185 ECMZ
28 Ld PLCC (Pb-free) N28.45
HC55185ECR*
HC55185 ECR
HC55185 ECRZ
HC55185 FCM
HC55185 FCMZ
HC55185 FCR
HC55185 FCRZ
HC55185 GIM
HC55185 GIMZ
HC55185 GCM
HC55185 GCMZ
HC55185 GCR
32 Ld QFN
L32.7x7**
HC55185ECRZ* (Note)
HC55185FCM*
32 Ld QFN (Pb-free) L32.7x7**
28 Ld PLCC
N28.45
•
•
•
•
HC55185FCMZ* (Note)
HC55185FCR*
28 Ld PLCC (Pb-free) N28.45
32 Ld QFN
L32.7x7**
HC55185FCRZ* (Note)
HC55185GIM
32 Ld QFN (Pb-free) L32.7x7**
-40 to +85 28 Ld PLCC
N28.45
•
•
•
•
•
•
HC55185GIMZ (Note)
HC55185GCM
-40 to +85 28 Ld PLCC (Pb-free) N28.45
0 to +85
0 to +85
0 to +85
0 to +85
28 Ld PLCC
N28.45
•
•
•
•
HC55185GCMZ (Note)
HC55185GCR*
28 Ld PLCC (Pb-free) N28.45
32 Ld QFN
L32.7x7**
HC55185GCRZ* (Note) HC55185 GCRZ
HC5518XEVAL1
32 Ld QFN (Pb-free) L32.7x7**
Evaluation board platform, including CODEC.
*Add "96" suffix for tape and reel
**Reference “Special Considerations for the QFN Package” text.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Device Operating Modes
MODE
Low Power Standby
Forward Active
Unbalanced Ringing
Reverse Active
Ringing
F2
F1
F0 E0 = 1 E0 = 0 HC55185A HC55185B HC55185C HC55185D HC55185E HC55185F HC55185G
0
0
0
1
0
1
0
1
0
1
SHD
SHD
RTD
SHD
RTD
SHD
SHD
n/a
GKD
GKD
RTD
GKD
RTD
GKD
GKD
n/a
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
0
0
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
0
Forward Loop Back
Tip Open
1
0
1
1
Power Denial
1
1
•
FN4831.14
December 18, 2006
2
HC55185
Pinouts
HC55185
(28 LD PLCC)
TOP VIEW
HC55185
(32 LD QFN)
TOP VIEW
4
3
2
1
28 27 26
32 31 30 29 28 27 26 25
SW+
SW-
SWC
F2
ILIM
RTD
CDC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
RTD
CDC
25
24
23
22
5
6
SW+
SW-
7
V
SWC
F2
CC
V
CC
8
-IN
F1
-IN
21 VFB
20 VTX
9
F1
F0
VFB
VTX
VRX
10
F0
E0
19
E0 11
VRX
NC
12 13 14 15 16 17 18
9
10 11 12 13 14 15 16
FN4831.14
December 18, 2006
3
HC55185
Absolute Maximum Ratings
T
= +25°C
Thermal Information
A
Maximum Supply Voltages
Thermal Resistance (Typical)
θ
(°C/W)
θ
(°C/W)
JC
JA
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
CC
CC
PLCC (Note 1) . . . . . . . . . . . . . . . . . . .
QFN (Note 2) . . . . . . . . . . . . . . . . . . . .
53
27
N/A
1
- V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110V
BH
Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . . -110V
Maximum Tip/Ring Negative Voltage Pulse (Note 8) . . . . . . VBH -15V
Maximum Tip/Ring Positive Voltage Pulse (Note 8) . . . . . . . . . . . .+8V
ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(PLCC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389
Operating Conditions
Die Characteristics
Temperature Range
Commercial (C suffix) . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
Industrial (I suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
BH
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
Positive Power Supply (V ). . . . . . . . . . . . . . . . . . . . . . . +5V, ±5%
CC
Low Battery Power Supply (V ). . . . . . . . . . . . . -16V to -52V, ±5%
BL
High Battery Power Supply (V
)
BH
AIM, CIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to 100V, ±5%
BL
BIM, DIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EIM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
V
to -85V, ±10%
to -75V, ±10%
BL
BL
Uncommitted Switch (loop back or relay driver) . . . . . +5V to -100V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ for the PLCC package is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief
JA
TB379 for details.
2. θ for the QFN package is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach
JA
features including conductive thermal vias. θ , the “case temp” is measured at the center of the exposed metal pad on the package underside.
JC
See Tech Brief 379 and AN9922 for additional information and board layout considerations.
Electrical Specifications Unless Otherwise Specified, T = -40°C to +85°C for industrial (I) grade and T = 0°C to +85°C for commercial
A
A
(C) grade, V = -24V, V
= -100V, -85V or -75V, V
= +5V, AGND = BGND = 0V, loop current limit = 25mA.
BL BH
CC
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω.
PARAMETER
RINGING PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VRS Input Impedance (Note 3)
Differential Ringing Gain (Note 4)
450
78
-
80
-
kΩ
V/V
V/V
V
Balanced Ringing, VRS to 2-Wire, R
= ∞
= ∞
82
LOAD
Unbalanced Ringing, VRS to 2-Wire, R
40
LOAD
Tip, Referenced to V /2 + 0.5 (Note 9)
Centering Voltage Accuracy
Open Circuit Ringing Voltage
-
-
-
± 2.5
± 2.5
67
-
-
-
BH
Ring, Referenced to V /2 + 0.5
BH
V
Balanced Ringing, VRS Input = 0.840V
V
V
RMS
RMS
Unbalanced Ringing, VRS Input = 0.840V
33.5
-
RMS
RMS
%
Ringing Voltage Total Distortion
R
= 1.3 kΩ, V
= |V | -5
BH
-
-
-
4.0
L
T-R
4-Wire to 2-Wire Ringing Off Isolation
2-Wire to 4-Wire Transmit Isolation
Active Mode, Referenced to VRS Input
90
-
-
dB
dB
Ringing Mode Referenced to the Differential
Ringing Amplitude
80
AC TRANSMISSION PARAMETERS
Receive Input Impedance (Note 3)
Transmit Output Impedance (Note 3)
4-Wire Port Overload Level (Note 3)
2-Wire Port Overload Level (Note 3)
2-Wire Return Loss
160
-
-
1
-
kΩ
-
3.1
3.1
-
-
Ω
THD = 1%
THD = 1%
300Hz
3.5
3.5
24
40
21
V
V
PEAK
-
PEAK
dB
-
1kHz
-
-
dB
dB
3.4kHz
-
-
FN4831.14
December 18, 2006
4
HC55185
Electrical Specifications Unless Otherwise Specified, T = -40°C to +85°C for industrial (I) grade and T = 0°C to +85°C for commercial
A
A
(C) grade, V = -24V, V
= -100V, -85V or -75V, V
= +5V, AGND = BGND = 0V, loop current limit = 25mA.
BL BH
CC
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω. (Continued)
PARAMETER
TEST CONDITIONS
Forward Active, Grade A and B
Forward Active, Grade C, D and E
Forward Active, Grade A and B
Forward Active, Grade C, D and E
+3 to -40dBm, 1kHz
MIN
58
53
58
53
-
TYP
62
MAX
UNITS
dB
2-Wire Longitudinal Balance (Notes 5, 6)
-
-
59
dB
4-Wire Longitudinal Balance (Notes 5, 6)
67
-
1
dB
64
-
dB
2-Wire to 4-Wire Level Linearity
4-Wire to 2-Wire Level Linearity
Referenced to -10dBm
±0.025
±0.050
±0.100
-
-
dB
-40 to -50dBm, 1kHz
-
-
dB
-50 to -55dBm, 1kHz
-
-
dB
Longitudinal Current Capability Per Wire (Note 3)
Test for False Detect
20
10
-0.20
-
-
mA
mA
RMS
RMS
Test for False Detect, Low Power Standby
-
4-Wire to 2-Wire Insertion Loss
2-Wire to 4-Wire Insertion Loss
4-Wire to 4-Wire Insertion Loss
Forward Active Idle Channel Noise (Note 6)
0.00
+0.20
dB
-6.22 -6.02 -5.82
-6.22 -6.02 -5.82
dB
dB
2-Wire C-Message, T = +25°C
4-Wire C-Message, T = +25°C
2-Wire C-Message, T = +25°C
4-Wire C-Message, T = +25°C
-
-
-
-
10
4
13
7
dBrnC
dBrnC
dBrnC
dBrnC
Reverse Active Idle Channel Noise (Note 6)
11
5
14
8
DC PARAMETERS
Off Hook Loop Current Limit
Programming Accuracy
Programming Range
Programming Accuracy
Programming Range
Forward Polarity Only
-8.5
15
-10
40
18
-
-
-
+8.5
45
+10
100
26
-
%
mA
%
Off Hook Transient Current Limit
-
-
mA
mA
Loop Current During Low Power Standby
Open Circuit Voltage (|Tip - Ring|)
-
V
V
V
V
V
V
= -16V
8.0
15.5
49
44.5
51.5
-53
V
V
V
V
V
V
BL
BL
BH
BL
BH
RG
DC
DC
DC
DC
DC
DC
= -24V
14
43
-
17
-
> -60V
Low Power Standby, Open Circuit Voltage
(Tip - Ring)
= -48V
-
> -60V
43
-
-
Absolute Open Circuit Voltage
TEST ACCESS FUNCTIONS
Switch On Voltage
in LPS and FA; V
in RA; V
BH
> -60V
-56
TG
I
= 45mA
-
-
0.30
-
0.60
52
V
V
OL
Loopback Max Battery
LOOP DETECTORS AND SUPERVISORY FUNCTIONS
Switch Hook Programming Range
Switch Hook Programming Accuracy
Dial Pulse Distortion
5
-10
-
-
-
15
mA
%
Assumes 1% External Programming Resistor
+10
1.0
2.5
-
-
%
Ring Trip Comparator Threshold
Ring Trip Programming Current Accuracy
Ground Key Threshold
2.3
-10
-
2.9
V
+10
%
12
20
175
-
-
-
mA
μs
°C
E0 Transition, DET Output Delay
Thermal Alarm Output
-
IC Junction Temperature
-
LOGIC INPUTS (F0, F1, F2, E0, SWC, BSEL)
Input Low Voltage
-
-
-
0.8
V
V
Input High Voltage
2.0
-20
-
-
Input Low Current
V
= 0.4V
-10
μA
IL
FN4831.14
December 18, 2006
5
HC55185
Electrical Specifications Unless Otherwise Specified, T = -40°C to +85°C for industrial (I) grade and T = 0°C to +85°C for commercial
A
A
(C) grade, V = -24V, V
= -100V, -85V or -75V, V
= +5V, AGND = BGND = 0V, loop current limit = 25mA.
BL BH
CC
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
V
= 2.4V
-
-
1
μA
IH
LOGIC OUTPUTS (DET, ALM)
Output Low Voltage
I
I
= 5mA
-
0.15
3.5
0.4
-
V
V
OL
Output High Voltage
= 100μA
2.4
OH
SUPPLY CURRENTS
Low Power Standby, BSEL = 1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.9
0.66
4.9
1.2
7.0
0.9
2.2
6.4
0.3
2.0
9.3
0.3
2.4
10.3
23.5
3.8
0.3
4.0
0.22
6.0
0.90
6.5
2.5
9.5
2.0
3.0
9.0
1.0
3.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC
BH
CC
BL
Forward or Reverse Active, BSEL = 0
Forward Active, BSEL = 1
CC
BL
BH
CC
BL
Ringing, BSEL = 1 (Balanced Ringing, 100)
Ringing, BSEL = 1 (Unbalanced Ringing, 010)
BH
CC
BL
BH
CC
BL
Forward Loopback, BSEL = 0
Tip Open, BSEL = 0
13.5
32
5.5
1.0
6.0
0.5
CC
BL
Power Denial, BSEL = 0 or 1
CC
BL
ON HOOK POWER DISSIPATION (Note 7)
Forward or Reverse
V
V
V
V
V
V
V
= -24V
-
-
-
-
-
-
-
55
85
-
-
-
-
-
-
-
mW
mW
mW
mW
mW
mW
mW
BL
Low Power Standby
= -100V
= -85V
= -75V
= -100V
= -85V
= -75V
BH
BH
BH
BH
BH
BH
75
65
Ringing
250
230
225
OFF HOOK POWER DISSIPATION (Note 7)
Forward or Reverse
V
= -24V
-
305
-
mW
BL
POWER SUPPLY REJECTION RATIO
V
to 2-Wire
f = 300Hz
f = 1kHz
-
-
-
-
-
-
-
-
-
40
35
28
45
43
33
30
35
33
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
CC
f = 3.4kHz
f = 300Hz
f = 1kHz
V
to 4-Wire
CC
f = 3.4kHz
V
V
V
to 2-Wire
to 4-Wire
to 2-Wire
300Hz ≤ f ≤ 3.4kHz
300Hz ≤ f ≤ 3.4kHz
300Hz ≤ f ≤ 3.4kHz
BL
BL
BH
FN4831.14
December 18, 2006
6
HC55185
Electrical Specifications Unless Otherwise Specified, T = -40°C to +85°C for industrial (I) grade and T = 0°C to +85°C for commercial
A
A
(C) grade, V = -24V, V
= -100V, -85V or -75V, V
= +5V, AGND = BGND = 0V, loop current limit = 25mA.
BL BH
CC
All AC parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to
3.4kHz. Protection resistors = 0Ω. (Continued)
PARAMETER
TEST CONDITIONS
300Hz ≤ f ≤ 1kHz
1kHz < f ≤ 3.4kHz
MIN
TYP
40
MAX
UNITS
dB
V
to 4-Wire
-
-
-
-
BH
45
dB
NOTES:
3. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial
design release and upon design changes which would affect these characteristics.
4. Differential Ringing Gain is measured with VRS = 0.795V
for -75V devices.
for -100V devices, VRS = 0.663 V
for -85V devices and VRS = 0.575V
RMS RMS
RMS
5. Longitudinal Balance is tested per IEEE455-1985, with 368Ω per Tip and Ring terminal.
6. These parameters are tested 100% at room temperature. These parameters are guaranteed not tested across temperature via statistical
characterization and design.
7. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current
limits.
8. Characterized with 2 x 10μs, and 10 x 1000μs first level lightning surge waveforms (GR-1089-CORE)
9. For Unbalanced Ringing the Tip terminal is offset to 0V and the Ring terminal is centered at Vbh/2 + 0.5V.
Special Considerations for the QFN
Package
The new QFN package offers a significant footprint reduction
(65%) and improved thermal performance with respect to the
28 lead PLCC. To realize the thermal enhancements and
maintain the high voltage (-100V) performance, the exposed
leadframe should be soldered to a power/heat sink plane
Application Circuit Modifications
The HC55185 basic application circuit is nearly identical to
that of the HC55180 through HC55184. The HC55185
requires an additional resistor to program the transient
current limit feature. This programming resistor is connected
from pin 16 (TL) to ground. In addition some component
values have been changed to improve overall device
performance. The table below lists the component value
changes required for the HC55185 application circuit.
that is electrically connected to the high battery supply (V
)
BH
within the application board. This approach distributes the
heat evenly across the board and is accomplished by using
conductive thermal vias. Reference technical brief TB379
and AN9922 for additional information on thermal
characterization and board layout considerations.
TABLE 2. COMPONENT VALUE CHANGES
REFERENCE
HC55180 - 184
210kΩ
HC55185
66.5kΩ
≥ 49Ω
≥ 49Ω
4.7μ
RS
RP1
RP2
CFB
≥ 35Ω
Product Family Cross Reference
≥ 35Ω
0.47μ
The following table provides an ordering and functional cross
reference for the existing HC55180 through HC55184
products and the new and improved HC55185 product.
The value of RS is based on a 600Ω termination impedance
and RP1 = RP2 = 49.9Ω. Design equations are provided to
calculate RS for other combinations of termination and
protection resistance.
TABLE 1. PRODUCT CROSS REFERENCE
EXISTING DEVICES
HC55180CIM, HC55180DIM
HC55181AIM, HC55182AIM
HC55181BIM, HC55182BIM
HC55181CIM, HC55182CIM
HC55181DIM, HC55182DIM
HC55183ECM, HC55184ECM
FUNCTIONAL EQUIVALENT
None Offered
The CFB capacitor must be non-polarized for proper device
operation in Reverse Active. Ceramic surface mount
capacitors (1206 body style) are available from Panasonic
with a 6.3V voltage rating. These can be used for CFB since
it is internally limited to approximately ±3V. The CDC
capacitor may be either polarized or non polarized.
HC55185AIM
HC55185BIM
HC55185CIM
HC55185DIM
HC55185ECM
Parametric Improvements
The most significant parametric improvement of the
HC55185 is reduction in Idle Channel Noise. This
improvement was accomplished by redistributing gains in
the impedance matching loop. The impact to the application
circuit is the change in the impedance programming resistor
RS. The redistribution of gains also improves AC
performance at the upper end of the voice band.
Any of the HC55185 products may be used without the
battery switch function by shorting the supply pins VBL and
VBH together. This provides compatibility with HC55180
type applications which do not require the battery switch.
FN4831.14
December 18, 2006
7
HC55185
diagram applies to the sink current limit with current polarity
changed accordingly.
Functional Improvements
In addition to parametric improvements, internal circuit
changes and application circuit changes have been made to
improve the overall device functionality.
I
/K
O
I
= 1.21/TL
I
ERR
REF
200k
Off Hook Interface
The transient behavior of the device in response to mode
changes has been significantly improved. The benefit to the
application is reduction or more likely elimination of DET
glitches when off hook events occur. In addition to internal
circuit modifications, the change of CFB value contributes to
this functional improvement.
TIP or RING
-
+
20
I
O
I
SIG
VB/2
FIGURE 1. CURRENT LIMIT FUNCTIONAL DIAGRAM
Transient Current Limit
During normal operation, the error current (I
) is zero and
ERR
The drive current capability of the output amplifiers is
determined by an externally programmable output current
limit circuit which is separate from the DC loop current limit
function and programmed at the pin TL. The current limit
circuit works in both the source and sink direction, with an
internally fixed offset to prevent the current limit functions
from turning on simultaneously. The current limit function is
provided by sensing line current and reducing the voltage
drive to the load when the externally set threshold is
exceeded, hence forcing a constant source or sink current.
the output voltage is determined by the signal current (I
)
SIG
multiplied by the 200k feedback resistor. With the current
polarity as shown for I , the output voltage moves positive
SIG
with respect to half battery. Assuming the amplifier output is
driving a load at a more negative potential, the amplifier
output will source current.
During excessive output source current flow, the scaled
output current (I /K) exceeds the reference current (I
)
O
REF
forcing an error current (I
). With the polarity as shown
ERR
the error current subtracts from the signal current, which
SOURCE CURRENT PROGRAMMING
reduces the amplifier output voltage. By reducing the output
voltage the source current to the load is decreased and the
output current is limited.
The source current is externally programmed as shown in
Equation 1.
1780
(EQ. 1)
-------------
R
=
TL
DETERMINING THE PROPER SETTING
I
SRC
Since this feature programs the maximum output current of
the device, the setting must be high enough to allow for
detection of ring trip or programmed off hook loop current,
whichever is greater.
For example a source current limit setting of 50mA is
programmed with a 35.6kΩ resistor connected from pin 16 of
the device to ground. This setting determines the maximum
amount of current which flows from Tip to Ring during an off
hook event until the DC loop current limit responds. In addition
this setting also determines the amount of current which will
flow from Tip or Ring when external battery faults occur.
To allow for proper ring trip operation, the transient current
limit setting should be set at least 25% higher than the peak
ring trip current setting. Setting the transient current 25%
higher should account for programming tolerances of both
the ring trip threshold and the transient current limit.
SINK CURRENT PROGRAMMING
The sink current limit is internally offset 20% higher than the
externally programmed source current limit setting.
If loop current is larger than ring trip current (low REN applica-
tions) then the transient current limit should be set at least 35%
higher than the loop current setting. The slightly higher offset
accounts for the slope of the loop current limit function.
(EQ. 2)
I
= 1.20 × I
SRC
SNK
If the source current limit is set to 50mA, the sink current limit
will be 60mA. This setting will determine the maximum current
that flows into Tip or Ring when external ground faults occur.
Attention to detail should be exercised when programming
the transient current limit setting. If ring trip detect does not
occur while ringing, then re-examine the transient current
limit and ring trip threshold settings.
FUNCTIONAL DESCRIPTION
Each amplifier is designed to limit source current and sink
current. The diagram below shows the functionality of the
circuit for the case of limiting the source current. A similar
FN4831.14
December 18, 2006
8
HC55185
4-WIRE TO 2-WIRE GAIN
Design Equations
The 4-wire to 2-wire gain is defined as the receive gain. It is
a function of the terminating impedance, synthesized
impedance and protection resistors. Equation 8 calculates
Loop Supervision Thresholds
SWITCH HOOK DETECT
the receive gain, G
.
The switch hook detect threshold is set by a single external
42
resistor, R . Equation 3 is used to calculate the value of R
.
SH SH
Z
⎛
⎜
⎝
⎞
⎟
⎠
L
-----------------------------------------
O
G
= –2
42
(EQ. 3)
= 600 ⁄ I
(EQ. 8)
Z
+ 2R + Z
P L
R
SH
SH
The term I
SH
is the desired DC loop current threshold. The
When the device source impedance and protection resistors
equals the terminating impedance, the receive gain equals
unity.
loop current threshold programming range is from 5mA to
15mA.
GROUND KEY DETECT
2-WIRE TO 4-WIRE GAIN
The ground key detector senses a DC current imbalance
between the Tip and Ring terminals when the ring terminal is
connected to ground. The ground key detect threshold is not
externally programmable and is internally fixed to 12mA
regardless of the switch hook threshold.
The 2-wire to 4-wire gain (G ) is the gain from tip and ring to
24
the VTX output. The transmit gain is calculated in Equation 9.
Z
⎛
⎜
⎝
⎞
⎟
⎠
O
-----------------------------------------
O
G
= –
24
(EQ. 9)
Z
+ 2R + Z
P L
When the protection resistors are set to zero, the transmit
gain is -6dB.
RING TRIP DETECT
The ring trip detect threshold is set by a single external
resistor, R . I should be set between the peak ringing
current and the peak off hook current while still ringing.
RT RT
TRANSHYBRID GAIN
The transhybrid gain is defined as the 4-wire to 4-wire gain
R
= 1800 ⁄ I
RT
(EQ. 4)
(G ).
44
RT
Z
⎛
⎜
⎝
⎞
⎟
⎠
O
(EQ. 10)
In addition, the ring trip current must be set below the
transient current limit, including tolerances. The capacitor
, in parallel with R , will set the ring trip response time.
--------------------------------------
O
G
= –
44
Z
+ 2R + Z
P L
C
RT RT
When the protection resistors are set to zero, the transhybrid
gain is -6dB.
Loop Current Limit
The loop current limit of the device is programmed by the
COMPLEX IMPEDANCE SYNTHESIS
external resistor R . The value of R can be calculated
IL IL
Substituting the impedance programming resistor, R , with a
S
complex programming network provides complex
impedance synthesis.
using Equation 5:
1760
------------
R
=
(EQ. 5)
IL
I
LIM
2-WIRE
NETWORK
PROGRAMMING
NETWORK
C
C
The term I
LIM
is the desired loop current limit. The loop
2
Parallel
current limit programming range is from 15mA to 45mA.
R
R
1
Series
Impedance Matching
R
2
The impedance of the device is programmed with the
R
Parallel
external component R . R is the gain setting resistor for
the feedback amplifier that provides impedance matching. If
complex impedance matching is required, then a complex
S
S
FIGURE 2. COMPLEX PROGRAMMING NETWORK
The reference designators in the programming network
network can be substituted for R .
S
match the evaluation board. The component R has a
S
different design equation than the R used for resistive
S
impedance synthesis. The design equations for each
component are provided below.
RESISTIVE IMPEDANCE SYNTHESIS
The source impedance of the device, Z , can be calculated
O
in Equation 6.
R
= 133.3 × (R – 2(R ))
1 P
(EQ. 11)
Series
(EQ. 6)
R
= 133.3(Z )
O
S
(EQ. 12)
(EQ. 13)
R
C
= 133.3 × R
2
Parallel
Parallel
The required impedance is defined by the terminating
impedance and protection resistors as shown in Equation 7.
·
= C ⁄ 133.3
2
(EQ. 7)
Z
= Z – 2R
L P
O
FN4831.14
December 18, 2006
9
HC55185
voltage exceeds the MTU reference of -56V, the Ring
terminal will be clamped by the internal reference (typically
-54V). The same Ring relationships apply when operating
Low Power Standby
Overview
The low power standby mode (LPS, 000) should be used
during idle line conditions. The device is designed to operate
from the high battery during this mode. Most of the internal
circuitry is powered down, resulting in low power dissipation.
If the 2-wire (tip/ring) DC voltage requirements are not
critical during idle line conditions, the device may be
operated from the low battery. Operation from the low battery
will decrease the standby power dissipation.
from the low battery voltage. For high battery voltages (V
)
BH
less than or equal to the internal MTU reference threshold:
V
= V
+ 4
BH
(EQ. 14)
RING
Loop Current
During LPS, the device will provide current to a load. The
current path is through resistors and switches, and will be
function of the off hook loop resistance (R
). This
LOOP
TABLE 3. DEVICE INTERFACES DURING LPS
includes the off hook phone resistance and copper loop
resistance. The current available during LPS is determined
by Equation 15.
INTERFACE
Receive
ON
OFF
NOTES
x
x
x
AC transmission, impedance
matching and ringing are
disabled during this mode.
(EQ. 15)
I
= (– 1 – (–49)) ⁄ (600 + 600 + R
)
LOOP
Ringing
LOOP
Transmit
Internal current limiting of the standby switches will limit the
maximum current to 20mA.
2-Wire
x
x
Amplifiers disabled.
Loop Detect
Switch hook or ground key.
Another loop current related parameter is longitudinal
current capability. The longitudinal current capability is
2-Wire Interface
reduced to 10mA
per pin. The reduction in longitudinal
RMS
current capability is a result of turning off the Tip and Ring
amplifiers.
During LPS, the 2-wire interface is maintained with internal
switches and voltage references. The Tip and Ring
amplifiers are turned off to conserve power. The device will
provide MTU compliance, loop current and loop supervision.
Figure 3 represents the internal circuitry providing the 2-wire
interface during low power standby.
On Hook Power Dissipation
The on hook power dissipation of the device during LPS is
determined by the operating voltages and quiescent currents
and is calculated using Equation 16.
GND
(EQ. 16)
P
= V
× I
+ V × I
+ V
× I
CC CCQ
LPS
BH
BHQ
BL
BLQ
600Ω
The quiescent current terms are specified in the electrical
tables for each operating mode. Load power dissipation is
not a factor since this is an on hook mode. Some
applications may specify a standby current. The standby
current may be a charging current required for modern
telephone electronics.
TIP AMP
TIP
RING
RING AMP
Standby Current Power Dissipation
600Ω
Any standby line current, I
, introduces an additional
SLC
. Equation 17 illustrates the
MTU REF
power dissipation term P
SLC
power contribution is zero when the standby line current is
zero.
FIGURE 3. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM
(EQ. 17)
MTU Compliance
P
= I
× ( V
– 49 + 1 + I
x1200)
SLC
SLC
SLC
BH
Maintenance Termination Unit or MTU compliance places
DC voltage requirements on the 2-wire terminals during idle
line conditions. The minimum idle voltage is 42.75V. The
high side of the MTU range is 56V. The voltage is expressed
as the difference between Tip and Ring.
If the battery voltage is less than -49V (the MTU clamp is
off), the standby line current power contribution reduces to
Equation 18.
(EQ. 18)
P
= I
× ( V
+ 1 + I
x1200)
SLC
SLC
SLC
BH
The Tip voltage is held near ground through a 600Ω resistor
and switch. The Ring voltage is limited to a maximum of
-56V (by MTU REF) when operating from either the high or
low battery. A switch and 600Ω resistor connect the MTU
reference to the Ring terminal. When the high battery
Most applications do not specify charging current
requirements during standby. When specified, the typical
charging current may be as high as 5mA.
FN4831.14
December 18, 2006
10
HC55185
filter is set by the external capacitor C . The value of the
DC
external capacitor should be 4.7μF.
Forward Active
Overview
Most applications will operate the device from low battery
while off hook. The DC feed characteristic of the device will
drive Tip and Ring towards half battery to regulate the DC
loop current. For light loads, Tip will be near -4V and Ring
The forward active mode (FA, 001) is the primary AC
transmission mode of the device. On hook transmission, DC
loop feed and voice transmission are supported during forward
active. Loop supervision is provided by either the switch hook
detector (E0 = 1) or the ground key detector (E0 = 0). The
device may be operated from either high or low battery for on-
hook transmission and low battery for loop feed.
will be near V
+ 4V. The following diagram shows the DC
VBL
feed characteristic.
V
m = (ΔV /ΔI ) = 11.1kΩ
TR
TR(OC)
L
On-Hook Transmission
The primary purpose of on hook transmission will be to
support caller ID and other advanced signalling features.
The transmission over load level while on hook is 3.5V
.
PEAK
I
LIM
I
(mA)
LOOP
When operating from the high battery, the DC voltages at Tip
and Ring are MTU compliant. The typical Tip voltage is -4V
and the Ring voltage is a function of the battery voltage for
battery voltages less than -60V as shown in Equation 19.
(EQ. 19)
FIGURE 5. DC FEED CHARACTERISTIC
The point on the y-axis labeled V
is the open circuit
TR(OC)
Tip to Ring voltage and is defined by the feed battery
V
= V
+ 4
BH
voltage.
RING
(EQ. 20)
V
= V
– 8
BL
TR(OC)
Loop supervision is provided by the switch hook detector at
the DET output. When DET goes low, the low battery should
be selected for DC loop feed and voice transmission.
The curve of Figure 5 determines the actual loop current for
a given set of loop conditions. The loop conditions are
determined by the low battery voltage and the DC loop
impedance. The DC loop impedance is the sum of the
protection resistance, copper resistance (Ω/foot) and the
telephone off hook DC resistance.
Feed Architecture
The design implements a voltage feed current sense
architecture. The device controls the voltage across Tip and
Ring based on the sensing of load current. Resistors are
placed in series with Tip and Ring outputs to provide the
current sensing. The diagram below illustrates the concept.
I
I
A
SC
I
I
B
LIM
R
R
A
B
V
IN
R
CS
-
V
+
OUT
2R
R
KNEE
P
R
(Ω)
LOOP
R
R
L
C
FIGURE 6. I
LOOP
vs R
LOAD CHARACTERISTIC
LOOP
-
+
The slope of the feed characteristic and the battery voltage
define the maximum loop current on the shortest possible
K
S
FIGURE 4. VOLTAGE FEED CURRENT SENSE DIAGRAM
loop as the short circuit current I
SC
.
V
– 2R I
P LIM
1.1e4
By monitoring the current at the amplifier output, a negative
feedback mechanism sets the output voltage for a defined
TR(OC)
(EQ. 21)
-----------------------------------------------------
I
= I
+
SC
LIM
load. The amplifier gains are set by resistor ratios (R , R ,
A
B
The term I
is the programmed current limit, 1760/R . The
IL
LIM
R ) providing all the performance benefits of matched
C
line segment I represents the constant current region of the
loop current limit function.
A
resistors. The internal sense resistor, R , is much smaller
CS
than the gain resistors and is typically 20Ω for this device.
V
– R
I
LOOP LIM
The feedback mechanism, K , represents the amplifier
TR(OC)
(EQ. 22)
S
--------------------------------------------------------------
+
LIM
I
= I
A
1.1e4
configuration providing the negative feedback.
DC Loop Feed
The maximum loop impedance for a programmed loop
current is defined as R
.
The feedback mechanism for monitoring the DC portion of
the loop current is the loop detector. A low pass filter is used
in the feedback to block voice band signals from interfering
with the loop current limit function. The pole of the low pass
KNEE
V
TR(OC)
(EQ. 23)
-----------------------
R
=
KNEE
I
LIM
FN4831.14
December 18, 2006
11
HC55185
When R
is exceeded, the device will transition from
constant current feed to constant voltage, resistive feed. The
of the signal injected at V . The echo must be cancelled to
RX
maintain voice quality. Most applications will use a summing
KNEE
line segment I represents the resistive feed portion of the
load characteristic.
amplifier in the CODEC front end as shown below to cancel
the echo signal.
B
V
TR(OC)
R
-----------------------
(EQ. 24)
I
=
B
R
LOOP
VRX
VTX
R
R
RX OUT
A
B
R
Voice Transmission
1:1
R
F
The feedback mechanism for monitoring the AC portion of
the loop current consists of two amplifiers, the sense
amplifier (SA) and the transmit amplifier (TA). The AC
feedback signal is used for impedance synthesis. A detailed
model of the AC feed back loop is provided below.
-
+
T
A
TX IN
R
S
+2.4V
CODEC
-IN
HC5518x
R
R
VRX
FIGURE 8. TRANSHYBRID BALANCE INTERFACE
20
20
-
R
TIP
+
1:1
The resistor ratio, R /R , provides the final adjustment for
F
B
the transmit gain, G . The transmit gain is calculated using
VTX
TX
+
RING
-
Equation 27.
T
A
R
S
R
⎛
⎜
⎝
⎞
⎟
⎠
F
-------
(EQ. 27)
G
= –G
24
TX
R
3R
-IN
C
R
B
4R
4R
4R
4R
FB
8K
Most applications set R = R , hence the device 2-wire to
F
B
-
+
VFB
4-wire equals the transmit gain. Typically R is greater than
V
B
SA
3R
20kΩ to prevent loading of the device transmit output.
The resistor ratio, R /R , is determined by the transhybrid
F
A
gain of the device, G . R is previously defined by the
44
F
FIGURE 7. AC SIGNAL TRANSMISSION MODEL
transmit gain requirement and R is calculated using
A
Equation 28.
The gain of the transmit amplifier, set by R , determines the
S
R
B
programmed impedance of the device. The capacitor C
FB
----------
R
=
A
(EQ. 28)
G
blocks the DC component of the loop current. The ground
symbols in the model represent AC grounds, not actual DC
potentials.
44
Power Dissipation
The power dissipated by the device during on hook
transmission is strictly a function of the quiescent currents
for each supply voltage during Forward Active operation.
The sense amp output voltage, V , as a function of Tip and
SA
Ring voltage and load is calculated using Equation 25.
30
Z
L
------
(EQ. 25)
V
= –(V – V )
SA
T
R
P
= V
× I
+ V × I
+ V
× I
CC CCQ
(EQ. 29)
FAQ
BH
BL
BLQ
BHQ
The transmit amplifier provides the programmable gain
required for impedance synthesis. In addition, the output of
this amplifier interfaces to the CODEC transmit input. The
output voltage is calculated using Equation 26.
Off hook power dissipation is increased above the quiescent
power dissipation by the DC load. If the loop length is less
than or equal to R
, the device is providing constant
KNEE
current, I , and the power dissipation is calculated using
A
R
S
Equation 30.
⎛
⎝
⎞
⎠
(EQ. 26)
----------
V
= –V
SA
VTX
8e3
2
(EQ. 30)
P
= P
+ (V xI ) – (R
LOOP
xI
)
A
FA(IA)
FA(Q)
BL
A
Once the impedance matching components have been
selected using the design equations, the above equations
provide additional insight as to the expected AC node
voltages for a specific Tip and Ring load.
If the loop length is greater than R
operating in the constant voltage, resistive feed region. The
power dissipated in this region is calculated using Equation 31.
, the device is
KNEE
2
(EQ. 31)
P
= P
+ (V xI ) – (R xI
LOOP
)
B
Transhybrid Balance
FA(IB)
FA(Q)
BL
B
The final step in completing the impedance synthesis design
is calculating the necessary gains for transhybrid balance.
The AC feed back loop produces an echo at the V output
TX
FN4831.14
December 18, 2006
12
HC55185
Since the current relationships are different for constant
current versus constant voltage, the region of device
operation is critical to valid power dissipation calculations.
POL pin and minimal voltage excursion ±0.75V, are well
suited to polarized capacitors.
Power Dissipation
The power dissipation equations for forward active operation
also apply to the reverse active mode.
Reverse Active
Overview
The reverse active mode (RA, 011) provides the same
functionality as the forward active mode. On hook
transmission, DC loop feed and voice transmission are
supported. Loop supervision is provided by either the switch
hook detector (E0 = 1) or the ground key detector (E0 = 0).
The device may be operated from either high or low battery.
Ringing
Overview
The ringing mode (RNG,100) provides linear amplification to
support a variety of ringing waveforms. A programmable ring
trip function provides loop supervision and auto disconnect
upon ring trip. The device is designed to operate from the
high battery during this mode.
During reverse active the Tip and Ring DC voltage
characteristics exchange roles. That is, Ring is typically 4V
below ground and Tip is typically 4V more positive than
battery. Otherwise, all feed and voice transmission
characteristics are identical to forward active.
Architecture
The device provides linear amplification to the signal applied
to the ringing input, V . The differential ringing gain of the
RS
device is 80V/V. The circuit model for the ringing path is
shown in Figure 10.
Silent Polarity Reversal
Changing from forward active to reverse active or vice versa
is referred to as polarity reversal. Many applications require
slew rate control of the polarity reversal event. Requirements
range from minimizing cross talk to protocol signalling.
R
R/8
-
+
20
VRS
-
TIP
+
600k
5:1
The device uses an external low voltage capacitor, C
, to
POL
V
+
BH
2
20
-
set the reversal time. Once programmed, the reversal time
will remain nearly constant over various load conditions. In
addition, the reversal timing capacitor is isolated from the AC
loop, therefore loop stability is not impacted.
+
RING
-
R
The internal circuitry used to set the polarity reversal time is
shown below.
FIGURE 10. LINEAR RINGING MODEL
The voltage gain from the VRS input to the Tip output is
I
1
40V/V. The resistor ratio provides a gain of 8 and the current
mirror provides a gain of 5. The voltage gain from the VRS
input to the Ring output is -40V/V. The equations for the Tip
and Ring outputs during ringing are provided below.
V
POL
75kΩ
C
POL
BH
2
I
(EQ. 33)
2
-----------
V =
+ (40 × VRS)
T
V
BH
-----------
(EQ. 34)
V
=
– (40 × VRS)
R
2
FIGURE 9. REVERSAL TIMING CONTROL
When the input signal at VRS is zero, the Tip and Ring
amplifier outputs are centered at half battery. The device
provides auto centering for easy implementation of
sinusoidal ringing waveforms. Both AC and DC control of the
Tip and Ring outputs is available during ringing. This feature
allows for DC offsets as part of the ringing waveform.
During forward active, the current from source I1 charges
the external timing capacitor C
and the switch is open.
POL
The internal resistor provides a clamping function for
voltages on the POL node. During reverse active, the switch
closes and I2 (roughly twice I1) pulls current from I1 and the
timing capacitor. The current at the POL node provides the
drive to a differential pair which controls the reversal time of
the Tip and Ring DC voltages.
Ringing Input
The ringing input, V , is a high impedance input. The high
RS
impedance allows the use of low value capacitors for AC
Δtime
75000
----------------
=
(EQ. 32)
C
POL
coupling the ring signal. The V
input is enabled only
RS
Where Δtime is the required reversal time. Polarized
capacitors may be used for C . The low voltage at the
during the ringing mode, therefore a free running oscillator
may be connected to VRS at all times.
POL
FN4831.14
December 18, 2006
13
HC55185
When operating from a battery of -100V, each amplifier, Tip
and Ring, will swing a maximum of 95V . Hence, the
For sinusoidal waveforms, the average current, I
defined in Equation 38.
, is
AVG
P-P
maximum signal swing at VRS to achieve full scale ringing is
approximately 2.4V . The low signal levels are compatible
V
× 2
2
⎝ ⎠
π Z
RMS
⎛ ⎞
-- -----------------------------------------
=
(EQ. 38)
I
AVG
P-P
+ R
REN
LOOP
with the output voltage range of the CODEC. The digital
nature of the CODEC ideally suits it for the function of
programmable ringing generator. See Applications Section.
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
Logic Control
Unbalanced Ringing
Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
The HC55185GCM offers a new Unbalanced Ringing mode
(010). This feature has been added to accommodate some
Analog PBX Trunk Lines that require the Tip terminal to be
held near ground for the duration of the ringing bursts. The
Tip terminal is offset to 0V’s with an internal current source
that is applied to the inverting input of the Tip amplifier. This
reduces the differential ringing gain to 40V/V. The Ring
terminal will center at Vbh/2 and swing from -Vbh to ground.
As in Balanced Ringing, off hook detection is accomplished
by sensing the peak current and comparing it to a preset
threshold. This allows the same sensing, comparing and
threshold circuitry to be used in both Ringing modes. This
mode of operation does not require any additional external
components.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full wave rectifies the
ringing current, which is then filtered with external components
R
and C . The resistor R sets the trip threshold and the
RT
RT RT
capacitor C sets the trip response time. Most applications will
RT
require a trip response time less than 150ms.
Three very distinct actions occur when the devices detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
Forward Loop Back
Overview
The Forward Loop Back mode (FLB, 101) provides test
capability for the device. An internal signal path is enabled
allowing for both DC and AC verification. The internal 600Ω
terminating resistor has a tolerance of ±20%. The device is
intended to operate from only the low battery during this
mode.
Power Dissipation
The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to valid
power calculations is the correct definition of average and RMS
currents. The average current defines the high battery supply
current. The RMS current defines the load current.
Architecture
When the forward loop back mode is initiated internal
switches connect a 600Ω load across the outputs of the Tip
and Ring amplifiers.
TIP
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
TIP AMP
power, P , and the silent interval power, P .
r
s
600Ω
t
t
r
s
(EQ. 35)
------------- -------------
+ P ×
s
P
= P ×
RNG
r
RING AMP
t + t
t + t
r s
r
s
RING
The terms t and t represent the cadence. The ringing
R
S
interval is t and the silent interval is t . The typical cadence
FIGURE 11. FORWARD LOOP BACK INTERNAL TERMINATION
R
S
ratio t :t is 1:2.
R S
DC Verification
The quiescent power of the device in the ringing mode is
defined in Equation 36.
When the internal signal path is provided, DC current will
flow from Tip to Ring. The DC current will force DET low,
indicating the presence of loop current. In addition, the ALM
output will also go low. This does not indicate a thermal
alarm condition. Rather, proper logic operation is verified in
the event of a thermal shutdown. In addition to verifying
device functionality, toggling the logic outputs verifies the
interface to the system controller.
P
= V
× I
+ V × I
+ V
× I
CC CCQ
(EQ. 36)
r(Q)
BH
BHQ
BL
BLQ
The total power during the ringing interval is the sum of the
quiescent power and loading power:
2
V
RMS
+ R
LOOP
-----------------------------------------
(EQ. 37)
P
= P
+ V
× I –
AVG
r
r(Q)
BH
Z
REN
FN4831.14
December 18, 2006
14
HC55185
AC Verification
Functionality
The entire AC loop of the device is active during the forward
loop back mode. Therefore a 4-wire to 4-wire level test
capability is provided. Depending on the transhybrid balance
implementation, test coverage is provided by a one or two
step process.
During power denial, both the Tip and Ring amplifiers are
disabled, representing high impedances. The voltages at
both outputs are near ground.
Thermal Shutdown
In the event the safe die temperature is exceeded, the ALM
output will go low and DET will go high and the part will
automatically shutdown. When the device cools, ALM will
go high and DET will reflect the loop status. If the thermal
fault persists, ALM will go low again and the part will
shutdown. Programming power denial will permanently
shutdown the device and stop the self cooling cycling.
System architectures which cannot disable the transhybrid
function would require a two step process. The first step
would be to send a test tone to the device while on hook and
not in forward loop back mode. The return signal would be
the test level times the gain R /R of the transhybrid
F
A
amplifier. Since the device would not be terminated,
cancellation would not occur. The second step would be to
program the device to FLB and resend the test tone. The
return signal would be much lower in amplitude than the first
step, indicating the device was active and the internal
termination attenuated the return signal.
Battery Switching
Overview
The integrated battery switch selects between the high
battery and low battery. The battery switch is controlled
with the logic input BSEL. When BSEL is a logic high, the
high battery is selected and when a logic low, the low
battery is selected. All operating modes of the device will
operate from high or low battery except forward loop back.
System architectures which disable the transhybrid function
would achieve test coverage with a signal step. Once the
transhybrid function is disable, program the device for FLB
and send the test tone. The return signal level is determined
by the 4-wire to 4-wire gain of the device.
Functionality
Tip Open
The logic control is independent of the operating mode
decode. Independent logic control provides the most
flexibility and will support all application configurations.
Overview
The tip open mode (110) is intended for compatibility for PBX
type interfaces. Used during idle line conditions, the device
does not provide transmission. Loop supervision is provided
by either the switch hook detector (E0 = 1) or the ground key
detector (E0 = 0). The ground key detector will be used in
most applications. The device may be operated from either
high or low battery.
When changing device operating states, battery switching
should occur simultaneously with or prior to changing the
operating mode. In most cases, this will minimize overall
power dissipation and prevent glitches on the DET output.
The only external component required to support the battery
switch is a diode in series with the V
supply lead. In the
BH
event that high battery is removed, the diode allows the
device to transition to low battery operation.
Functionality
During tip open operation, the Tip switch is disabled and the
Ring switch is enabled. The minimum Tip impedance is
30kΩ. The only active path through the device will be the
Ring switch.
Low Battery Operation
All off hook operating conditions should use the low battery.
The prime benefit will be reduced power dissipation. The
typical low battery for the device is -24V. However this may
be increased to support longer loop lengths or high loop
current requirements. Standby conditions may also operate
from the low battery if MTU compliance is not required,
further reducing standby power dissipation.
In keeping with the MTU characteristics of the device, Ring
will not exceed -56V when operating from the high battery.
Though MTU does not apply to tip open, safety requirements
are satisfied.
Power Denial
High Battery Operation
Overview
Other than ringing, the high battery should be used for
standby conditions which must provide MTU compliance.
During standby operation the power consumption is typically
85mW with -100V battery. If ringing requirements do not
require full 100V operation, then a lower battery will result in
lower standby power.
The power denial mode (111) will shutdown the entire device
except for the logic interface. Loop supervision is not
provided. This mode may be used as a sleep mode or to
shut down in the presence of a persistent thermal alarm.
Switching between high and low battery will have no effect
during power denial.
FN4831.14
December 18, 2006
15
HC55185
High Voltage Decoupling
+5V
The 100V rating of the device will require a capacitor of
higher voltage rating for decoupling. Suggested decoupling
RELAY
values for all device pins are 0.1μF. Standard surface mount
ceramic capacitors are rated at 100V. For applications driven
at low cost and small size, the decoupling scheme shown
below could be implemented.
SW+
SW-
SWC
0.22μ
0.22μ
FIGURE 13. EXTERNAL RELAY SWITCHING
Test Load
The switch may be used to connect test loads across Tip
and Ring. The test loads can provide external test
termination for the device. Proper connection of the
uncommitted switch to Tip and Ring is shown in Figure 14.
VBL
VBH
HC5518X
FIGURE 12. ALTERNATE DECOUPLING SCHEME
It is important to place the external diode between the VBH
pin and the decoupling capacitor. Attaching the decoupling
capacitor directly to the VBH pin will degrade the reliability of
the device. Refer to Figure 12 for the proper arrangement.
This applies to both single and stacked and decoupling
arrangements.
TIP
RING
TEST
LOAD
If VBL and VBH are tied together to override the battery
switch function, then the external diode is not needed and
the decoupling may be attached directly to VBH.
SW+
SWC
SW-
Uncommitted Switch
FIGURE 14. TEST LOAD SWITCHING
Overview
The uncommitted switch is a three terminal device designed
for flexibility. The independent logic control input, SWC,
allows switch operation regardless of device operating
mode. The switch is activated by a logic low. The positive
and negative terminals of the device are labeled SW+ and
SW- respectively.
The diode in series with the test load blocks current from
flowing through the uncommitted switch when the polarity of
the Tip and Ring terminals are reversed. In addition to the
reverse active state, the polarity of Tip and Ring are
reversed for half of the ringing cycle. With independent logic
control and the blocking diode, the uncommitted switch may
be continuously connected to the Tip and Ring terminals.
Relay Driver
The uncommitted switch may be used as a relay driver by
connecting SW+ to the relay coil and SW- to ground. The
switch is designed to have a maximum on voltage of 0.6V
with a load current of 45mA.
Since the device provides the ringing waveform, the relay
functions which may be supported include subscriber
disconnect, test access or line interface bypass. An external
snubber diode is not required when using the uncommitted
switch as a relay driver.
FN4831.14
December 18, 2006
16
HC55185
TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT
LIST
Basic Application Circuit
COMPONENT
VALUE
HC55185
18.7kΩ
23.7kΩ
49.9kΩ
71.5kΩ
66.5kΩ
0.47μF
4.7μF
TOL
N/A
1%
RATING
N/A
C
PS1
U1 - Ringing SLIC
C
PS2
R
R
R
R
R
C
C
C
C
D
R
0.1W
0.1W
0.1W
0.1W
0.1W
10V
D
TL
RT
SH
IL
1
C
PS3
1%
1%
VCC
VBH
VRX
VBL
C
C
RX
RS
1%
R
P1
U
1
1%
TIP
S
VRS
VTX
-IN
, C , C , C , C
RT POL
20%
20%
20%
20%
HC55185
RX
RS
TX
R
P2
, C
10V
DC FB
PS1
RING
SW+
SW-
C
TX
R
0.1μF
>100V
100V
S
, C
PS3
0.1μF
PS2
1
C
RT
RT
C
FB
1N400X type with breakdown > 100V.
VFB
R
RTD
, R
P2
P1
Standard applications will use ≥ 49Ω per side. Protection resistor
values are application dependent and will be determined by
protection requirements.
SWC
BSEL
E0
R
SH
RD
R
IL
ILIM
Design Parameters: Ring Trip Threshold = 76mA
, Switch
PEAK
Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize
Device Impedance = (3*66.5kΩ)/400 = 498.8Ω, with 49.9Ω
protection resistors, impedance across Tip and Ring
terminals = 599Ω. Transient current limit = 95mA.
F0
C
DC
CDC
V
F1
CC
C
POL
F2
POL
DET
R
TL
TL
ALM
AGND
BGND
FIGURE 15. HC55185 BASIC APPLICATION CIRCUIT
FN4831.14
December 18, 2006
17
HC55185
Pin Descriptions
PLCC QFN SYMBOL
DESCRIPTION
1
2
29
30
TIP
TIP power amplifier output.
BGND
Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
3
4
5
6
7
31
32
1
VBL
VBH
SW+
SW-
Low battery supply connection.
High battery supply connection for the most negative battery.
Uncommitted switch positive terminal.
2
Uncommitted switch negative terminal.
3
SWC
Switch control input. This TTL compatible input controls the uncommitted switch, with a logic “0” enabling the switch
and logic “1” disabling the switch.
8
4
F2
Mode Control Input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of
operation of the device.
9
5
6
7
F1
F0
E0
Mode control input.
Mode control input.
10
11
Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD (E0 = 0) comparator
outputs to the DET output based upon the state at the F2-F0 pins (see the Device Operating Modes table shown on page 2).
12
13
9
DET
ALM
Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating
mode. The detected output will either be switch hook, ground key or ring trip (see the Device Operating Modes table
shown on page 2).
10
Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature
(approximately 175°C) and the device has been powered down automatically.
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
11
12
13
14
15
17
18
19
20
21
22
23
24
25
27
AGND
BSEL
TL
Analog ground reference. This pin should be externally connected to BGND.
Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery.
Programming pin for the transient current limit feature, set by an external resistor to ground.
External capacitor on this pin sets the polarity reversal time.
POL
VRS
VRX
VTX
VFB
-IN
Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode.
Analog Receive Voltage - 4-wire analog audio input voltage. AC couples to CODEC.
Transmit Output Voltage - Output of impedance matching amplifier, AC couples to CODEC.
Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching.
Impedance matching amplifier summing node.
VCC
CDC
RTD
ILIM
RD
Positive voltage power supply, usually +5V.
DC Biasing Filter Capacitor - Connects between this pin and V
Ring trip filter network.
.
CC
Loop Current Limit programming resistor.
Switch hook detection threshold programming resistor.
RING power amplifier output.
RING
FN4831.14
December 18, 2006
18
HC55185
Quad Flat No-Lead Plastic Package (QFN)
L32.7x7
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VKKC ISSUE C)
2X
0.15
C A
D
A
MILLIMETERS
9
D/2
SYMBOL
MIN
TYP
MAX
1.00
NOTES
D1
A
A1
A2
A3
b
0.80
0.90
-
D1/2
-
-
-
0.05
1.00
-
2X
N
0.15 C
B
6
-
9
INDEX
AREA
0.20 REF
9
1
2
3
E1/2
E/2
9
0.23
0.28
0.38
4.85
4.85
5, 8
E1
E
B
D
7.00 BSC
-
D1
D2
E
6.75 BSC
9
2X
4.55
4.55
4.70
7, 8
0.15 C
B
7.00 BSC
-
2X
TOP VIEW
0.15 C
A
E1
E2
e
6.75 BSC
9
4.70
7, 8
0
A2
4X
C
A
/ /
0.10 C
0.08 C
0.65 BSC
-
k
0.25
0.50
-
-
-
0.75
0.15
-
L
0.60
8
SEATING PLANE
A1
A3
SIDE VIEW
9
L1
N
-
32
8
8
-
10
2
5
NX b
0.10 M C A B
Nd
Ne
P
3
4X P
D2
D2
8
7
3
NX k
(DATUM B)
-
-
0.60
9
2
N
θ
-
12
9
4X P
Rev. 4 8/03
1
(DATUM A)
2
3
NOTES:
(Ne-1)Xe
REF.
E2
6
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
INDEX
AREA
7
8
E2/2
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
NX L
8
N
e
9
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
(Nd-1)Xe
REF.
CORNER
OPTION 4X
BOTTOM VIEW
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
A1
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
C
L
C
L
9. Features and dimensions A2, A3, D1, E1, P & θ are present
when Anvil singulation method is used and not present for saw
singulation.
L
L
10
10
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
L1
L1
e
e
C
C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
FN4831.14
December 18, 2006
19
HC55185
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
N28.45 (JEDEC MS-018AB ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
PIN (1) IDENTIFIER
0.025 (0.64)
0.045 (1.14)
0.050 (1.27) TP
INCHES
MILLIMETERS
R
C
L
SYMBOL
MIN
MAX
MIN
4.20
MAX
4.57
NOTES
A
A1
D
0.165
0.090
0.485
0.450
0.191
0.485
0.450
0.191
0.180
0.120
0.495
0.456
0.219
0.495
0.456
0.219
-
2.29
3.04
-
D2/E2
D2/E2
12.32
11.43
4.86
12.57
11.58
5.56
-
C
L
D1
D2
E
3
E1 E
4, 5
12.32
11.43
4.86
12.57
11.58
5.56
-
VIEW “A”
E1
E2
N
3
4, 5
6
0.020 (0.51)
MIN
28
28
A1
D1
D
Rev. 2 11/97
A
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
-C-
4. To be measured at seating plane
contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4831.14
December 18, 2006
20
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