HCS02D [INTERSIL]
Radiation Hardened Quad 2-Input NOR Gate; 抗辐射四2输入或非门
| 型号： | HCS02D |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened Quad 2-Input NOR Gate |
| 文件： | 总8页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCS02MS
Radiation Hardened
Quad 2-Input NOR Gate
August 1995
Features
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD(Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 Rads (Si)/s
• Dose Rate Upset >1010 RAD(Si)/s 20ns Pulse
Y1
A1
1
2
3
4
5
6
7
14 VCC
13 Y4
12 B4
11 A4
10 Y3
B1
Y2
• Latch-Up Free Under Any Conditions
A2
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
B2
9
8
B3
A3
GND
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Y1
A1
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
Y4
Description
B1
B4
A4
Y3
Y2
The Intersil HCS02MS is a Radiation Hardened Quad 2-Input NOR
Gate. A low on both inputs forces the output to a High state.
A2
B2
B3
A3
The HCS02MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
GND
8
The HCS02MS is supplied in a 14 lead Ceramic Flatpack Package
(K suffix) or a 14 lead SBDIP Package (D suffix).
TRUTH TABLE
INPUTS
OUTPUTS
An
L
Bn
L
Yn
H
L
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE LEVEL
L
H
L
PACKAGE
H
H
L
o
o
HCS02DMSR
HCS02KMSR
-55 C to +125 C Intersil Class
S Equivalent
14 Lead SBDIP
H
L
NOTE: L = Logic Level Low, H = Logic level High
o
o
-55 C to +125 C Intersil Class
S Equivalent
14 Lead Ceramic
Flatpack
Functional Diagram
o
HCS02D/
Sample
+25 C
Sample
Sample
Die
14 Lead SBDIP
An
(2, 5, 8, 11)
o
HCS02K/
Sample
+25 C
14 Lead Ceramic
Flatpack
Yn
(1, 4, 10, 13)
o
HCS02HMSR
+25 C
Die
Bn
(3, 6, 9, 12)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518744
File Number 2433.2
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Specifications HCS02MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Thermal Resistance
SBDIP Package. . . . . . . . . . . . . . . . . . . .
Ceramic Flatpack Package . . . . . . . . . . . 116 C/W
Maximum Package Power Dissipation at +125 C
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.66W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/ C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.6mW/ C
θ
θ
JA
JC
o
o
74 C/W
24 C/W
o
o
30 C/W
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
o
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
o
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265 C
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
o
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . 100ns/V Max
Input Low Voltage (VIL). . . . . . . . . . . . . . .0.0V to 30% of VCC Max.
Input High Voltage (VIH) . . . . . . . . . . . . . . 70% of VCC to VCC Min.
o
o
Operating Temperature Range (T ) . . . . . . . . . . . . -55 C to +125 C
A
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
LIMITS
(NOTE 1)
PARAMETERS
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
UNITS
µA
o
Quiescent Current
ICC
VCC = 5.5V,
VIN = VCC or GND
1
2, 3
1
+25 C
-
10
o
o
+125 C, -55 C
-
200
µA
o
Output Current
(Sink)
IOL
IOH
VOL
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
+25 C
4.8
4.0
-4.8
-4.0
-
-
mA
mA
mA
mA
V
o
o
2, 3
1
+125 C, -55 C
-
-
o
Output Current
(Source)
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V
+25 C
o
o
2, 3
1, 2, 3
+125 C, -55 C
-
o
o
o
Output Voltage Low
VCC = 4.5V, VIH = 3.15V,
+25 C, +125 C, -55 C
0.1
IOL = 50µA, VIL = 1.35V
o
o
o
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C
-
0.1
V
V
V
o
o
o
Output Voltage High
VOH
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
+25 C, +125 C, -55 C
VCC
-0.1
-
-
o
o
o
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
+25 C, +125 C, -55 C
VCC
-0.1
o
Input Leakage
Current
IIN
FN
VCC = 5.5V, VIN = VCC or
GND
1
+25 C
-
-
-
±0.5
±5.0
-
µA
µA
-
o
o
2, 3
+125 C, -55 C
o
o
o
Noise Immunity
Functional Test
VCC = 4.5V,
VIH = 0.70(VCC),
VIL = 0.30(VCC) (Note 2)
7, 8A, 8B
+25 C, +125 C, -55 C
NOTES:
1. All voltages reference to device GND.
2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number 518744
2
Specifications HCS02MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
LIMITS
(NOTES 1, 2)
A SUB-
PARAMETER
Input to Yn
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
18
UNITS
ns
o
TPHL
VCC = 4.5V
9
+25 C
2
2
2
2
o
o
10, 11
9
+125 C, -55 C
20
ns
o
Input to Yn
NOTES:
TPLH
VCC = 4.5V
+25 C
20
ns
o
o
10, 11
+125 C, -55 C
22
ns
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
18
UNITS
pF
o
Capacitance Power
Dissipation
CPD
VCC = 5.0V, f = 1MHz
1
1
1
1
1
1
+25 C
-
-
-
-
-
-
o
o
+125 C, -55 C
26
pF
o
Input Capacitance
CIN
VCC = 5.0V, f = 1MHz
VCC = 4.5V
+25 C
10
pF
o
+125 C
10
pF
o
Output Transition
Time
TTHL
TTLH
+25 C
15
ns
o
+125 C
22
ns
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD LIMITS
(NOTES 1, 2)
PARAMETERS
Quiescent Current
Output Current (Sink)
SYMBOL
ICC
CONDITIONS
TEMPERATURE
MIN
-
MAX
UNITS
mA
o
VCC = 5.5V, VIN = VCC or GND
+25 C
0.2
o
IOL
VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V
+25 C
4.0
-4.0
-
-
mA
o
Output Current
(Source)
IOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25 C
mA
o
Output Voltage Low
Output Voltage High
Input Leakage Current
VOL
VOH
VCC = 4.5V or 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC) at 200K RAD, IOL = 50µA
+25 C
-
0.1
-
V
V
o
VCC = 4.5V or 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC) at 200K RAD, IOH = -50µA
+25 C
VCC
-0.1
o
IIN
FN
VCC = 5.5V, VIN = VCC or GND
+25 C
-
-
±5
µA
o
Noise Immunity
Functional Test
VCC = 4.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC) at 200K RAD, (Note 3)
+25 C
-
-
o
Input to Yn
TPHL
TPLH
VCC = 4.5V
VCC = 4.5V
+25 C
2
2
20
22
ns
ns
o
+25 C
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number 518744
3
Specifications HCS02MS
o
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 C)
GROUP B
PARAMETER
SUBGROUP
DELTA LIMIT
3µA
ICC
5
5
IOL/IOH
-15% of 0 Hour
TABLE 6. APPLICABLE SUBGROUPS
GROUP A SUBGROUPS
TESTED RECORDED
COMFORMANCE GROUP
Initial Test
MIL-STD-883 METHOD
100% 5004
1, 7, 9
1, 7, 9, ∆
1 (Note 2)
Interim Test
PDA
100% 5004
1, ∆ (Note 2)
100% 5004
1, 7, ∆
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆
1, 7, 9
Group A (Note 1)
Subgroup B5
Subgroup B6
Group D
Sample 5005
Sample 5005
Sample 5005
Sample 5005
1, 2, 3, ∆ (Note 2)
1, 7, 9
NOTES:
1. Alternate Group A testing in accordance with MIL-STD-883 Method 5005 may be exercised.
2. Table 5 parameters only.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
CONFORMANCE
GROUPS
Group E Subgroup 2
NOTE:
METHOD
PRE RAD
POST RAD
PRE RAD
POST RAD
5005
1, 7, 9
Table 4
1, 9
Table 4 (Note 1)
1. Except FN test which will be performed 100% Go/No-Go.
Spec Number 518744
4
Specifications HCS02MS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
STATIC BURN-IN I TEST CONDITIONS (Note 1)
1, 4, 10, 13 2, 3, 5, 6, 7, 8, 9, 11, 12
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
1, 4, 10, 13
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
50kHz
25kHz
-
14
-
-
-
-
7
-
2, 3, 5, 6, 8, 9, 11,
12, 14
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
-
7
1, 4, 10, 13
14
2, 3, 5, 6, 8, 9,
11, 12
-
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% static burn-in.
2. Each Pin except VCC and GND will have a resistor of 1kΩ ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
2, 3, 5, 6, 8, 9, 11, 12, 14
1, 4, 10, 13
7
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518744
5
HCS02MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% PIND, Method 2020, Condition A
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number 518744
6
HCS02MS
AC Load Circuit
AC Timing Diagrams
DUT
TEST
POINT
VIH
INPUT
VS
CL
RL
VIL
TPLH
TPHL
VOH
VOL
VOH
VOL
CL = 50pF
RL = 500Ω
VS
OUTPUT
FIGURE 2
TTLH
TTHL
80%
80%
20%
20%
OUTPUT
FIGURE 1
AC VOLTAGE LEVELS
PARAMETER
VCC
HCS
4.50
4.50
2.25
0
UNITS
V
V
V
V
V
VIH
VS
VIL
GND
0
Spec Number 518744
7
HCS02MS
Die Characteristics
DIE DIMENSIONS:
87 x 88 mils
2.20mm x 2.24mm
METALLIZATION:
Type: AlSi
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 x 4 mils
Metallization Mask Layout
HCS02MS
Y1
(1)
VCC
(14)
Y4
(13)
A1 (2)
(12) B4
(11) A4
B1 (3)
(10) Y3
Y2 (4)
A2 (5)
(9) B3
(6)
B2
(8)
A3
(7)
GND
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518744
8
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