HCS05KMSR [INTERSIL]
Radiation Hardened Hex Inverter with Open Drain; 抗辐射六角逆变器与漏极开路型号: | HCS05KMSR |
厂家: | Intersil |
描述: | Radiation Hardened Hex Inverter with Open Drain |
文件: | 总7页 (文件大小:110K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HCS05MS
Radiation Hardened
Hex Inverter with Open Drain
September 1995
Features
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
TOP VIEW
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
A1
Y1
1
2
3
4
5
6
7
14 VCC
13 A6
12 Y6
11 A5
10 Y5
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
A2
Y2
A3
Y3
9
8
A4
Y4
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
GND
• Input Logic Levels
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
A1
Y1
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
A6
Y6
Description
A2
The Intersil HCS05MS is a Radiation Hardened Hex inverter
function with open drain outputs. These open drain outputs can
drive into resistive loads with a separate voltage supply.
Y2
A5
Y5
A3
Y3
A4
Y4
The HCS05MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
GND
8
The HCS05MS is supplied in a 14 lead Ceramic Flatpack (K suffix)
or a Ceramic Dual-In-Line Package (D suffix).
Functional Diagram
Yn
An
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE LEVEL
PACKAGE
o
o
HCS05DMSR
-55 C to +125 C Intersil Class
S Equivalent
14 Lead SBDIP
TRUTH TABLE
OUTPUTS
INPUTS
o
o
HCS05KMSR
-55 C to +125 C Intersil Class
S Equivalent
14 Lead Ceramic
Flatpack
An
L
Yn
o
Z (Note 1)
H (Note 2)
HCS05D/
Sample
+25 C
Sample
Sample
Die
14 Lead SBDIP
H
L
o
HCS05K/
Sample
+25 C
14 Lead Ceramic
Flatpack
NOTES:
1. No pullup resistor
2. With pullup resistor
3. L = Low
o
HCS05HMSR
+25 C
Die
4. H = High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518829
File Number 3557.1
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
35
Specifications HCS05MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Thermal Resistance
SBDIP Package. . . . . . . . . . . . . . . . . . . .
Ceramic Flatpack Package . . . . . . . . . . . 116 C/W
Maximum Package Power Dissipation at +125 C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/ C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.6mW/ C
θ
θ
JA
JC
o
o
74 C/W
24 C/W
o
o
30 C/W
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
o
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
o
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265 C
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
o
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . 100ns/V Max
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . . . 70% of VCC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
o
o
Operating Temperature Range (T ) . . . . . . . . . . . . -55 C to +125 C
A
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
LIMITS
(NOTE 1)
PARAMETER
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
UNITS
µA
o
Supply Current
ICC
VCC = 5.5V,
1
+25 C
-
10
VIN = VCC or GND
o
o
2, 3
1
+125 C, -55 C
-
200
µA
o
Output Current
(Sink)
IOL
VCC = VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
(Note 2)
+25 C
4.8
4.0
-
-
mA
o
o
2, 3
+125 C, -55 C
mA
o
o
o
Output Voltage Low
VOL
VCC = 5.5V, VIH = 3.85V,
VIL = 1.35V, IOL = 50µA
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C
-
-
0.1
0.1
V
V
o
o
o
VCC = 4.5V, VIH = 3.15V,
+25 C, +125 C, -55 C
VIL = 1.35V, IOL = 50µA,
o
Input Leakage
Current
IIN
IOZH
FN
VCC = 5.5V, VIN = VCC or
GND
1
2, 3
+25 C
-
-
-
-
-
±0.5
±5.0
1
µA
µA
µA
µA
V
o
o
+125 C, -55 C
o
Three-State Output
Leakage Current
VCC = 5.5V,
Force Voltage = VCC
1
+25 C
o
o
2, 3
+125 C, -55 C
50
-
o
o
o
Noise Immunity
Functional Test
VCC = 4.5V, VIH = 3.15,
VIL = 1.35 (Note 3)
7, 8A, 8B
+25 C, +125 C, -55 C
NOTES:
1. All voltages reference to device GND.
2. Force/Measure functions may be interchanged.
3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
LIMITS
(NOTES 1, 2)
A SUB-
PARAMETER
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
2
MAX
18
UNITS
ns
o
Propagation Delay
An to Yn
TPLZ
TPZL
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
9
+25 C
o
o
10, 11
+125 C, -55 C
2
20
ns
NOTES:
1. All voltages referenced to device GND.
2. Measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns.
Spec Number 518829
36
Specifications HCS05MS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MAX
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
UNITS
pF
o
Capacitance Power
Dissipation
CPD
VCC = 5.0V, VIH = 5.0V,
VIL = 0.0V, f = 1MHz
1
1
1
1
1
1
+25 C
-
-
15
23
10
10
15
22
o
o
+125 C, -55 C
pF
o
Input Capacitance
CIN
VCC = 5.0V, VIH = 5.0V,
VIL = 0.0V, f = 1MHz
+25 C
-
pF
o
o
+125 C, -55 C
-
pF
o
Output Transition
Time
TTHL
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
+25 C
1
1
ns
o
o
+125 C, -55 C
ns
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
(NOTE 1)
PARAMETER
Supply Current
SYMBOL
ICC
CONDITIONS
TEMPERATURE
MIN
MAX
0.2
-
UNITS
mA
o
VCC = 5.5V, VIN = VCC or GND
VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0V
+25 C
-
4.0
-
o
Output Current (Sink)
Output Voltage Low
IOL
+25 C
mA
o
VOL
VCC = 5.5V , VIH = 3.85V, VIL = 1.65V,
+25 C
0.1
V
IOL = 50µA
o
VCC = 4.5V , VIH = 3.15V, VIL = 1.35V,
+25 C
-
0.1
V
IOL = 50µA
o
Input Leakage Current
IIN
VCC = 5.5V, VIN = VCC or GND
+25 C
-
-
±5
µA
µA
o
Three-State Output
Leakage Current
IOZH
VCC = 5.5V, Force Voltage = 0V or VCC
+25 C
±50
o
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH =3.15V, VIL = 1.35V,
(Note 2)
+25 C
-
-
V
o
Propagation Delay
NOTES:
TPLZ
TPZL
VCC = 4.5V, VIH =4.5V, VIL = 0V
+25 C
2
20
ns
1. All voltages referenced to device GND.
2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
o
TABLE 5. DELTA PARAMETERS (+25 C)
PARAMETER
Supply Current
SYMBOL
ICC
GROUP B SUBGROUP
UNITS
µA
+3
±200
-15
Three-State Leaking Current
Output Current
IOZH
IOL
nA
%
Spec Number 518829
37
Specifications HCS05MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test (Preburn-In)
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
Sample/5005
Sample/5005
GROUP A SUBGROUPS
READ AND RECORD
ICC, IOL, IOZH
1, 7, 9
1, 7, 9
Interim Test I (Postburn-In)
Interim Test II (Postburn-In)
PDA
ICC, IOL, IOZH
ICC, IOL/H
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
Interim Test III (Postburn-In)
PDA
ICC, IOL, IOZH
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Final Test
Group A (Note 1)
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Group D
NOTE:
1, 7, 9
1. Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
CONFORMANCE
GROUPS
Group E Subgroup 2
NOTE:
METHOD
PRE RAD
POST RAD
PRE RAD
1, 9
POST RAD
5005
1, 7, 9
Table 4
Table 4 (Note 1)
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
STATIC BURN-IN I TEST CONDITIONS (Note 1)
1, 3, 5, 7, 9, 11, 13
GROUND
VCC = 6V ± 0.5V
1/2 VCC = 3V ± 0.5V
50kHz
25kHz
-
2, 4, 6, 8, 10, 12, 14
-
-
-
-
-
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
2, 4, 6, 8, 10, 12 1, 3, 5, 9, 11, 13, 14
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
7
-
-
-
7
14
2, 4, 6, 8, 10, 12
1, 3, 5, 9, 11, 13
NOTES:
1. Each pin except VCC and GND will have a series resistor of 10KΩ ± 5%.
2. Each pin except VCC and GND will have a series resistor of 1KΩ ± 5%.
TABLE 9. IRRADIATION TEST CONNECTIONS
FUNCTION
OPEN
GROUND
VCC = 5V ± 0.5V
Irradiation Circuit
(Note 1)
2, 4, 6, 8, 10, 12
7
1, 3, 5, 9, 11, 13, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group E, Subgroup 2, sample
size is 4 dice/wafe,r 0 failures.
Spec Number 518829
38
HCS05MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% PIND, Method 2020, Condition A
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number 518829
39
HCS05MS
Transition Timing Diagram
Three-State Low Timing Diagram and
Load Circuit
VIH
VIH
VS
INPUT
INPUT
VS
VSS
VSS
TPZL
TPLZ
TTHL
VOZ
VOL
VOH
VOL
80%
VT
VW
OUTPUT
OUTPUT
20%
THREE-STATE LOW VOLTAGE LEVELS
PARAMETER
VCC
HCS
4.50
4.50
2.25
2.25
0.90
0
UNITS
V
V
V
V
V
V
VIH
VS
VT
VW
GND
VCC
RL
CL
TEST
POINT
DUT
CL = 50pF
RL = 500Ω
Spec Number 518829
40
HCS05MS
Die Characteristics
DIE DIMENSIONS:
87 x 88 mils
2.20mm x 2.24mm
METALLIZATION:
Type: AlSi
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 x 4 mils
Metallization Mask Layout
HCS05MS
Y1 (2)
(12) Y6
(11) A5
A2 (3)
(10) Y5
Y2 (4)
A3 (5)
(9) A4
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518829
41
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