HCS109HMSR [INTERSIL]
Radiation Hardened Dual JK Flip Flop; 抗辐射双JK触发器
| 型号： | HCS109HMSR |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened Dual JK Flip Flop |
| 文件： | 总9页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCS109MS
Radiation Hardened
Dual JK Flip Flop
September 1995
Features
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
R1
J1
1
2
3
4
5
6
7
8
16 VCC
15 R2
14 J2
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ)
K1
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
CP1
S1
13 K2
12 CP2
11 S2
10 Q2
• Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
Q1
Q1
• Latch-Up Free Under Any Conditions
9
Q2
GND
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
R1
J1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
R2
• Input Current Levels Ii ≤ 5µA at VOL, VOH
K1
J2
CP1
S1
K2
Description
CP2
S2
Q1
The Intersil HCS109MS is a Radiation Hardened Dual JK
Flip Flop with set and reset. The flip flop changes state with
the positive transition of the clock (CP1 or CP2).
Q1
Q2
Q2
GND
The HCS109MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS109MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCS109DMSR
TEMPERATURE RANGE
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
PACKAGE
16 Lead SBDIP
o
o
-55 C to +125 C
o
o
HCS109KMSR
-55 C to +125 C
16 Lead Ceramic Flatpack
16 Lead SBDIP
o
HCS109D/Sample
HCS109K/Sample
HCS109HMSR
+25 C
o
+25 C
Sample
16 Lead Ceramic Flatpack
Die
o
+25 C
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518748
File Number 2466.2
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
103
HCS109MS
Functional Diagram
5 (11)
S
6 (10)
Q
2 (14)
J
S
J
Q
Q
F/F
7 (9)
Q
3 (13)
K
K
CL CL
R
4 (12)
CP
1 (15)
R
16
VCC
8
GND
TRUTH TABLE
INPUTS
OUTPUTS
S
L
R
CP
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
H
L
X
H
L
X
H*
L
H*
H
H
H
H
H
H
H
H
H
H
H
H
L
L
Toggle
H
H
X
No Change
H
X
H
L
L
No Change
*Unpredictable and unstable condition if both S and R go high simultaneously
L = Logic Level Low
H = Logic Level High
= Transition from Low to High Level
Spec Number 518748
104
Specifications HCS109MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Thermal Resistance
SBDIP Package. . . . . . . . . . . . . . . . . . . .
Ceramic Flatpack Package . . . . . . . . . . . 114 C/W
Maximum Package Power Dissipation at +125 C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/ C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/ C
θ
θ
JA
JC
o
o
73 C/W
24 C/W
o
o
29 C/W
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
o
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265 C
o
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
o
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5 VCC (TR, TF) . . . . . . . .500ns Max
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
o
o
Operating Temperature Range (T ) . . . . . . . . . . . . -55 C to +125 C
A
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
LIMITS
(NOTE 1)
PARAMETER
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
UNITS
µA
o
Quiescent Current
ICC
VCC = 5.5V,
VIN = VCC or GND
1
2, 3
1
+25 C
-
20
o
o
+125 C, -55 C
-
400
µA
o
Output Current
(Sink)
IOL
IOH
VOL
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
+25 C
4.8
4.0
-4.8
-4.0
-
-
mA
mA
mA
mA
V
o
o
2, 3
1
+125 C, -55 C
-
-
o
Output Current
(Source)
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V
+25 C
o
o
2, 3
1, 2, 3
+125 C, -55 C
-
o
o
o
Output Voltage Low
VCC = 4.5V, VIH = 3.15V,
+25 C, +125 C, -55 C
0.1
IOL = 50µA, VIL = 1.35V
o
o
o
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C
-
0.1
V
V
V
o
o
o
Output Voltage High
VOH
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
+25 C, +125 C, -55 C
VCC
-0.1
-
-
o
o
o
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
+25 C, +125 C, -55 C
VCC
-0.1
o
Input Leakage
Current
IIN
FN
VCC = 5.5V, VIN = VCC or
GND
1
+25 C
-
-
-
±0.5
±5.0
-
µA
µA
-
o
o
2, 3
+125 C, -55 C
o
o
o
Noise Immunity
Functional Test
VCC = 4.5V,
VIH = 0.70(VCC),
VIL = 0.30(VCC) (Note 2)
7, 8A, 8B
+25 C, +125 C, -55 C
NOTES:
1. All voltages reference to device GND.
2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number 518748
105
Specifications HCS109MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
(NOTES 1, 2)
CONDITIONS
GROUP A
SUBGROUPS
PARAMETER
CP to Q, Q
SYMBOL
TEMPERATURE
MAX
26
30
30
35
19
23
31
33
31
33
31
33
UNITS
ns
o
TPLH
VCC = 4.5V
9
10, 11
9
+25 C
2
2
2
2
2
2
2
2
2
2
2
2
o
o
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
+125 C, -55 C
ns
o
TPHL
TPLH
TPHL
TPHL
TPLH
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
S to Q
S to Q
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
R to Q
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
R to Q
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
-
MAX
UNITS
pF
o
Capacitance Power
Dissipation
CPD
VCC = 5.0V, f = 1MHz
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+25 C
41
56
10
10
15
22
30
20
-
o
o
+125 C, -55 C
-
pF
o
Input Capacitance
CIN
VCC = 5.0V, f = 1MHz
VCC = 4.5V
+25 C
-
pF
o
o
+125 C, -55 C
-
pF
o
Output Transition
Time
TTHL
TTLH
+25 C
-
ns
o
o
+125 C, -55 C
-
ns
o
Max Operating
Frequency
FMAX
TSU
TH
VCC = 4.5V
+25 C
-
MHz
MHz
ns
o
o
+125 C, -55 C
-
o
Setup Time JK to
CP
VCC = 4.5V
+25 C
18
27
3
o
o
+125 C, -55 C
-
ns
o
Hold Time JK to CP
VCC = 4.5V
+25 C
-
ns
o
o
+125 C, -55 C
3
-
ns
o
Removal Time R,
S to CP
TREM
TW
VCC = 4.5V
+25 C
18
27
18
27
18
27
-
ns
o
o
+125 C, -55 C
-
ns
o
Pulse Width CP
Pulse Width R, S
NOTE:
VCC = 4.5V
+25 C
-
ns
o
o
+125 C, -55 C
-
ns
o
TW
VCC = 4.5V
+25 C
-
ns
o
o
+125 C, -55 C
-
ns
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number 518748
106
Specifications HCS109MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
(NOTES 1, 2)
PARAMETER
Quiescent Current
Output Current (Sink)
SYMBOL
ICC
CONDITIONS
TEMPERATURE
MIN
MAX
0.4
-
UNITS
mA
o
VCC = 5.5V, VIN = VCC or GND
+25 C
-
o
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25 C
4.0
mA
o
Output Current
(Source)
IOH
VOL
VOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25 C
-4.0
-
-
0.1
-
mA
V
o
Output Voltage Low
Output Voltage High
Input Leakage Current
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOL = 50µA
+25 C
o
VCC = 4.5V and 5.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), IOH = -50µA
+25 C
VCC
-0.1
V
o
IIN
FN
VCC = 5.5V, VIN = VCC or GND
+25 C
-
-
±5
µA
o
Noise Immunity
Functional Test
VCC = 4.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC), (Note 3)
+25 C
-
-
o
CP to Q, Q
TPLH
TPHL
TPLH
TPHL
TPHL
TPLH
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
+25 C
2
2
2
2
2
2
30
35
23
33
33
33
ns
ns
ns
ns
ns
ns
o
+25 C
o
S to Q
S to Q
+25 C
o
+25 C
o
R to Q
+25 C
o
R to Q
+25 C
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
o
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 C)
GROUP B
PARAMETER
SUBGROUP
DELTA LIMIT
6µA
ICC
IOL/IOH
5
5
-15% of 0 Hour
Spec Number 518748
107
Specifications HCS109MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test (Preburn-In)
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
GROUP A SUBGROUPS
READ AND RECORD
ICC, IOL/H
1, 7, 9
1, 7, 9
Interim Test I (Postburn-In)
Interim Test II (Postburn-In)
PDA
ICC, IOL/H
ICC, IOL/H
1, 7, 9
1, 7, 9, Deltas
Interim Test III (Postburn-In)
PDA
1, 7, 9
ICC, IOL/H
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Group A (Note 1)
Group B
Subgroup B-5
Subgroups 1, 2, 3, 9, 10, 11,
(Note 2)
Subgroup B-6
Sample/5005
Sample/5005
1, 7, 9
1, 7, 9
Group D
NOTES:
1. Alternate group A testing in accordance with method 5005 of MIL-STD-883 may be exercised.
2. Table 5 parameters only.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
CONFORMANCE
GROUPS
Group E Subgroup 2
NOTE:
METHOD
PRE RAD
POST RAD
PRE RAD
1, 9
POST RAD
5005
1, 7, 9
Table 4
Table 4 (Note 1)
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
6, 7, 9, 10 1 - 5, 8, 11 - 15
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
6, 7, 9, 10
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
16
50kHz
25kHz
-
-
-
-
8
-
1 - 5, 11 - 16
1, 5, 11, 15, 16
-
-
8
6, 7, 9, 10
4, 12
2, 3, 13, 14
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
6, 7, 9, 10
8
1 - 5, 11 - 16
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518748
108
HCS109MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% PIND, Method 2020, Condition A
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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NORTH AMERICA
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Mercure Center
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TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
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FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
Spec Number 518748
109
HCS109MS
AC Load Circuit
AC Timing Diagrams
DUT
TEST
POINT
VIH
CL
INPUT
VS
RL
VIL
TPLH
TPHL
CL = 50pF
VOH
RL = 500Ω
VS
OUTPUT
VOL
TTLH
VOH
TTHL
80%
80%
20%
20%
OUTPUT
VOL
AC VOLTAGE LEVELS
PARAMETER
VCC
HCS
4.50
4.50
2.25
0
UNITS
V
V
V
V
V
VIH
VS
VIL
GND
0
Pulse Width, Setup, Hold Timing Diagram
Positive Edge Trigger
Load Circuit
DUT
TEST
POINT
TW
INPUT
VIH
CL
RL
VIL
TH
TSU
CL = 50pF
TW
RL = 500Ω
CP INPUT
VIH
VS
VIL
TH = Hold Time
TSU = Setup Time
TW = Pulse Width
PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS
PARAMETER
VCC
HCS
4.50
4.50
2.25
0
UNITS
V
V
V
V
V
VIH
VS
VIL
GND
0
Spec Number 518748
110
HCS109MS
Die Characteristics
DIE DIMENSIONS:
89 x 88 mils
2.25 x 2.24mm
METALLIZATION:
Type: AlSi
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 x 4 mils
Metallization Mask Layout
HCS109MS
J1
(2)
R1
(1)
VCC
(16)
(15) R2
K1 (3)
(14) J2
CP1 (4)
S1 (5)
(13) K2
Q1 (6)
(12) CP2
(11) S2
Q1 (7)
(8)
(9)
Q2
(10)
Q2
GND
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.
The mask series for the HCS109 is TA14340A.
Spec Number 518748
111
相关型号：
HCS109KMSH
J-Kbar Flip-Flop, HC/UH Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16
RENESAS
HCS10DMSR
HC/UH SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14, METAL SEALED, SIDE BRAZED, CERAMIC, DIP-14
RENESAS
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