HCS373T [INTERSIL]
Radiation Hardened Octal Transparent Latch, Three-State; 抗辐射八路透明锁存器，三态
| 型号： | HCS373T |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened Octal Transparent Latch, Three-State |
| 文件： | 总3页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCS373T
Data Sheet
July 1999
File Number 4617.1
Radiation Hardened Octal Transparent
Latch, Three-State
Features
• QML Class T, Per MIL-PRF-38535
Intersil’s Satellite Applications FlowTM (SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
• Radiation Performance
5
- Gamma Dose (γ) 1 x 10 RAD(Si)
- Latch-Up Free Under Any Conditions
2
- SEP Effective LET No Upsets: >100 MEV-cm /mg
-9
- Single Event Upset (SEU) Immunity < 2 x 10
Errors/Bit-Day (Typ)
The Intersil HCS373T is a Radiation Hardened Octal
Transparent Three-State Latch with an active-low output
enable. The HCS373T utilizes advanced CMOS/SOS
technology. The outputs are transparent to the inputs when
the Latch Enable (LE) is HIGH. When the Latch Enable (LE)
goes LOW, the data is latched. The Output Enable (OE)
controls the three-state outputs. When the Output Enable
(OE) is HIGH, the outputs are in the high impedance state.
The latch operation is independent of the state of the Output
Enable.
• 3 Micron Radiation Hardened CMOS SOS
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- V = 0.3 V
IL CC
Max
Min
- V = 0.7 V
IH
CC
• Input Current Levels Ii ≤ 5mA at V , V
OL OH
Pinouts
Specifications
HCS373DTR (SBDIP), CDIP2-T20
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
TOP VIEW
1
2
3
4
5
6
7
8
9
V
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
20
19
CC
Q7
Detailed Electrical Specifications for the HCS373T are
contained in SMD 5962-95792. A “hot-link” is provided from
our website for downloading.
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
www.intersil.com/spacedefense/newsafclasst.asp
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
12
Q4
www.intersil.com/quality/manuals.asp
GND 10
11 LE
Ordering Information
TEMP.
HCS373KTR (FLATPACK), CDFP4-F20
ORDERING
NUMBER
RANGE
( C)
TOP VIEW
o
PART NUMBER
HCS373DTR
HCS373KTR
OE
Q0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
5962R9579201TRC
5962R9579201TXC
-55 to 125
-55 to 125
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
D0
D1
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
Q1
Q2
D2
D3
Q3
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
HCS373T
Functional Diagram
1 OF 8
(3, 4, 7, 8, 13,
14, 17, 18)
LATCH
OE
D
D
Q
Q
(2, 5, 6, 9, 12,
15, 16, 19)
LE
COMMON CONTROLS
LE
(11)
OE
(1)
TRUTH TABLE
OE
L
LE
H
H
L
D
H
L
I
Q
H
L
L
L
L
L
L
h
X
H
Z
H
X
H = High Level, L = Low Level.
X = Immaterial, Z = High Impedance.
I = Low voltage level prior to the high-to-low latch enable transition.
h = High voltage level prior to the high-to-low latch enable transition.
2
HCS373T
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Type: Silox (S O )
(2747µm x 2693µm x 533µm ±51.0µm)
108 x 106 x 21mils ±2mil
i
2
Thickness: 13kÅ ±2.6kÅ
METALLIZATION:
Type: Al Si
WORST CASE CURRENT DENSITY:
2
< 2.0e5 A/cm
Thickness: 11kÅ ±1kÅ
TRANSISTOR COUNT:
SUBSTRATE POTENTIAL:
376
Unbiased Silicon on Sapphire
PROCESS:
BACKSIDE FINISH:
CMOS SOS
Sapphire
Metallization Mask Layout
HCS373T
D0
(3)
Q0
(2)
OE
(1)
V
Q7
(19)
CC
(20)
(18) D7
(17) D6
D1 (4)
Q1 (5)
(16) Q6
Q2 (6)
(15) Q5
(14) D5
D2 (7)
(12)
Q4
(13)
D4
(8)
(9)
Q3
(10)
GND
(11)
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The
mask series for the HCS373 is TA14303A.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
3
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