HD9P6409-9 [INTERSIL]
CMOS Manchester Encoder-Decoder; CMOS曼彻斯特编码器，解码器
| 型号： | HD9P6409-9 |
| 厂家： | 
Intersil |
| 描述： | CMOS Manchester Encoder-Decoder |
| 文件： | 总12页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD-6409
CMOS Manchester Encoder-Decoder
March 1997
Features
Description
• Converter or Repeater Mode
The HD-6409 Manchester Encoder-Decoder (MED) is a high
speed, low power device manufactured using self-aligned sil-
icon gate technology. The device is intended for use in serial
data communication, and can be operated in either of two
modes. In the converter mode, the MED converts Non
return-to-Zero code (NRZ) into Manchester code and
decodes Manchester code into Nonreturn-to-Zero code. For
serial data communication, Manchester code does not have
some of the deficiencies inherent in Nonreturn-to-Zero code.
For instance, use of the MED on a serial line eliminates DC
components, provides clock recovery, and gives a relatively
high degree of noise immunity. Because the MED converts
the most commonly used code (NRZ) to Manchester code,
the advantages of using Manchester code are easily realized
in a serial data link.
• Independent Manchester Encoder and Decoder
Operation
• Static to One Megabit/sec Data Rate Guaranteed
• Low Bit Error Rate
• Digital PLL Clock Recovery
• On Chip Oscillator
• Low Operating Power: 50mW Typical at +5V
• Available in 20 Lead Dual-In-Line and 20 Pad LCC
Package
Ordering Information
In the Repeater mode, the MED accepts Manchester code
input and reconstructs it with a recovered clock. This mini-
mizes the effects of noise on a serial data link. A digital
phase lock loop generates the recovered clock. A maximum
data rate of 1MHz requires only 50mW of power.
TEMPERATURE
RANGE
PKG.
PACKAGE
PDIP
1 MEGABIT/SEC
NO.
E20.3
M20.3
F20.3
o
o
-40 C to +85 C HD3-6409-9
o
o
SOIC
-40 C to +85 C HD9P6409-9
o
o
Manchester code is used in magnetic tape recording and in
fiber optic communication, and generally is used where data
accuracy is imperative. Because it frames blocks of data, the
HD-6409 easily interfaces to protocol controllers.
CERDIP
DESC
CLCC
DESC
-40 C to +85 C HD1-6409-9
o
o
-55 C to 125 C 5962-9088801MRA F20.3
o
o
-40 C to +85 C HD4-6409-9
J20.A
o
o
-55 C to 125 C 5962-9088801M2A J20.A
Pinouts
HD-6409 (CERDIP, PDIP, SOIC)
HD-6409 (CLCC)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
V
BZI
BOI
20
19
CC
BOO
3
2
1
20 19
UDI
18 BZO
17 SS
BZO
SS
18
17
SD/CDS
SDO
4
5
6
7
8
SD/CDS
SDO
16 ECLK
15 CTS
14 MS
SRST
NVM
16 ECLK
15 CTS
SRST
NVM
DCLK
RST
13 OX
MS
14
DCLK
12
IX
GND 10
11 CO
9
10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2951.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19995-1
HD-6409
Block Diagram
SDO
NVM
BOO
BZO
BOI
DATA
INPUT
LOGIC
5-BIT SHIFT
REGISTER
AND DECODER
OUTPUT
SELECT
LOGIC
BZI
UDI
COMMAND
SYNC
GENERATOR
CTS
EDGE
DETECTOR
SRST
RST
RESET
INPUT/
OUTPUT
SELECT
SD
MANCHESTER
ENCODER
SD/CDS
MS
IX
ECLK
DCLK
COUNTER
CIRCUITS
OSCILLATOR
OX
CO
SS
Logic Symbol
13
17
11
OX
IX
SS
CLOCK
GENERATOR
12
CO
19
18
15
4
16
BOO
BZO
SD/CDS
ECLK
ENCODER
CONTROL
CTS
14
9
MS
RST
2
1
3
5
8
7
SDO
BOI
BZI
UDI
DCLK
NVM
6
SRST
DECODER
5-2
HD-6409
Pin Description
PIN
NUMBER TYPE SYMBOL
NAME
DESCRIPTION
1
2
3
4
I
I
BZl
BOl
UDI
Bipolar Zero Input
Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II
encoded data to the decoder, BZI and BOl are logical complements. When using
pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high.
Bipolar One Input
Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II
encoded data to the decoder, BOI and BZI are logical complements. When using
pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low.
I
Unipolar Data Input
An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input
Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2
(BOl) for data input, UDI must be held low.
I/O
SD/CDS Serial Data/Com-
mand Data Sync
In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ
data is accepted synchronously on the falling edge of encoder clock output
(ECLK). In the repeater mode, SD/CDS is an output indicating the status of last
valid sync pattern received. A high indicates a command sync and a low indicates
a data sync pattern.
5
6
O
O
SDO
Serial Data Out
Serial Reset
The decoded serial NRZ data is transmitted out synchronously with the decoder
clock (DCLK). SDO is forced low when RST is low.
SRST
In the converter mode, SRST follows RST. In the repeater mode, when RST goes
low, SRST goes low and remains low after RST goes high. SRST goes high only
when RST is high, the reset bit is zero, and a valid synchronization sequence is
received.
7
O
NVM
Nonvalid Manchester A low on NVM indicates that the decoder has received invalid Manchester data
and present data on Serial Data Out (SDO) is invalid. A high indicates that the
sync pulse and data were valid and SDO is valid. NVM is set low by a low on RST,
and remains low after RST goes high until valid sync pulse followed by two valid
Manchester bits is received.
8
9
O
I
DCLK
RST
Decoder Clock
The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchro-
nously output received NRZ data (SDO).
Reset
In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low.
A high on RST enables SDO and DCLK, and forces SRST high. NVM remains
low after RST goes high until a valid sync pulse followed by two Manchester bits
is received, after which it goes high. In the repeater mode, RST has the same ef-
fect on SDO, DCLK and NVM as in the converter mode. When RST goes low,
SRST goes low and remains low after RST goes high. SRST goes high only
when RST is high, the reset bit is zero and a valid synchronization sequence is
received.
10
11
12
I
O
I
GND
Ground
Ground
C
Clock Output
Clock Input
Buffered output of clock input I . May be used as clock signal for other peripherals.
X
O
I
I is the input for an external clock or, if the internal oscillator is used, I and O
X X X
X
are used for the connection of the crystal.
13
14
15
O
I
O
Clock Drive
Mode Select
Clear to Send
If the internal oscillator is used, O and I are used for the connection of the crys-
tal.
X
X
X
MS
MS must be held low for operation in the converter mode, and high for operation
in the repeater mode.
I
CTS
In the converter mode, a high disables the encoder, forcing outputs BOO, BZO high
and ECLK low. A high to low transition of CTS initiates transmission of a Command
sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode,
the function of CTS is identical to that of the converter mode with the exception that
a transition of CTS does not initiate a synchronization sequence.
16
O
ECLK
Encoder Clock
In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data
to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from
BZl and BOl data by the digital phase locked loop.
5-3
HD-6409
Pin Description
PIN
NUMBER TYPE SYMBOL
NAME
DESCRIPTION
17
I
SS
Speed Select
A logic high on SS sets the data rate at 1/32 times the clock frequency while a
low sets the data rate at 1/16 times the clock frequency.
18
O
BZO
BOO
Bipolar Zero Output
Bipolar One Out
BZO and its logical complement BOO are the Manchester data outputs of the en-
coder. The inactive state for these outputs is in the high state.
19
20
O
I
See pin 18.
V
V
V
is the +5V power supply pin. A 0.1µF decoupling capacitor from V (pin-
CC
CC
CC
CC
20) to GND (pin-10) is recommended.
NOTE: (I) Input
(O) Output
Encoder Operation
The encoder uses free running clocks at 1X and 2X the data bits followed by a command sync pulse.
2
A command
rate derived from the system clock l for internal timing. CTS sync pulse is a 3-bit wide pulse with the first 1 1/2 bits high
X
is used to control the encoder outputs, ECLK, BOO and followed by 1 1/2 bits low. 3 Serial NRZ data is clocked into
BZO. A free running 1X ECLK is transmitted out of the the encoder at SD/CDS on the high to low transition of ECLK
encoder to drive the external circuits which supply the NRZ during the command sync pulse. The NRZ data received is
data to the MED at pin SD/CDS.
encoded into Manchester II data and transmitted out on
BOO and BZO following the command sync pulse. Fol-
lowing the synchronization sequence, input data is encoded
and transmitted out continuously without parity check or
word framing. The length of the data block encoded is
defined by CTS. Manchester data out is inverted.
4
A low on CTS enables encoder outputs ECLK, BOO and
BZO, while a high on CTS forces BZO, BOO high and holds
ECLK low. When CTS goes from high to low 1 , a synchro-
nization sequence is transmitted out on BOO and BZO. A
synchronization sequence consists of eight Manchester “0”
CTS
1
ECLK
DON’T CARE
SD/CDS
‘1’
‘0’ ‘1’
BZO
BOO
3
0
2
0
0
0
0
0
0
0
4
‘1’ ‘0’ ‘1’
COMMAND
SYNC
EIGHT “0’s”
SYNCHRONIZATION SEQUENCE
t
t
CE5
CE6
FIGURE 1. ENCODER OPERATION
Decoder Operation
The decoder requires a single clock with a frequency 16X or Zero inputs will accept data from differential inputs such as a
32X the desired data rate. The rate is selected on the speed comparator sensed transformer coupled bus. The Unipolar
select with SS low producing a 16X clock and high a 32X Data input can only accept noninverted Manchester II
clock. For long data links the 32X mode should be used as encoded data i.e. Bipolar One Out through an inverter to
this permits a wider timing jitter margin. The internal opera- Unipolar Data Input. The decoder continuously monitors this
tion of the decoder utilizes a free running clock synchronized data input for valid sync pattern. Note that while the MED
with incoming data for its clocking.
encoder section can generate only a command sync pattern,
the decoder can recognize either a command or data sync
pattern. A data sync is a logically inverted command sync.
The Manchester II encoded data can be presented to the
decoder in either of two ways. The Bipolar One and Bipolar
5-4
HD-6409
There is a three bit delay between UDI, BOl, or BZI input and The decoded data at SDO is in NRZ format. DCLK is pro-
the decoded NRZ data transmitted out of SDO.
vided so that the decoded bits can be shifted into an external
register on every high to low transition of this clock. Three bit
periods after an invalid Manchester bit is received on UDI, or
BOl, NVM goes low synchronously with the questionable
data output on SDO. FURTHER, THE DECODER DOES
NOT REESTABLISH PROPER DATA DECODING UNTIL
ANOTHER SYNC PATTERN IS RECOGNIZED.
Control of the decoder outputs is provided by the RST pin.
When RST is low, SDO, DCLK and NVM are forced low.
When RST is high, SDO is transmitted out synchronously
with the recovered clock DCLK. The NVM output remains
low after a low to high transition on RST until a valid sync
pattern is received.
DCLK
UDI
COMMAND
1
0
0
1
0
1
0
1
0
1
0
1
0
SYNC
SDO
RST
NVM
FIGURE 2. DECODER OPERATION
Repeater Operation
Manchester Il data can be presented to the repeater in either A low on CTS enables ECLK, BOO, and BZO. In contrast to
of two ways. The inputs Bipolar One In and Bipolar Zero In the converter mode, a transition on CTS does not initiate a
will accept data from differential inputs such as a comparator synchronization sequence of eight 0’s and a command sync.
or sensed transformer coupled bus. The input Unipolar Data The repeater mode does recognize a command or data sync
In accepts only noninverted Manchester II coded data. The pulse. SD/CDS is an output which reflects the state of the
decoder requires a single clock with a frequency 16X or 32X most recent sync pulse received, with high indicating a com-
the desired data rate. This clock is selected to 16X with mand sync and low indicating a data sync.
Speed Select low and 32X with Speed Select high. For long
When RST is low, the outputs SDO, DCLK, and NVM are
data links the 32X mode should be used as this permits a
low, and SRST is set low. SRST remains low after RST goes
wider timing jitter margin.
high and is not reset until a sync pulse and two valid
The inputs UDl, or BOl, BZl are delayed approximately 1/2 manchester bits are received with the reset bit low. The reset
bit period and repeated as outputs BOO and BZO. The 2X bit is the first data bit after the sync pulse. With RST high,
ECLK is transmitted out of the repeater synchronously with NRZ Data is transmitted out of Serial Data Out synchro-
BOO and BZO.
nously with the 1X DCLK.
INPUT
COUNT
1
2
3
4
5
6
7
ECLK
UDI
SYNC PULSE
BZO
BOO
RST
SRST
FIGURE 3. REPEATER OPERATION
5-5
HD-6409
Manchester Code
Nonreturn-to-Zero (NRZ) code represents the binary values The synchronization advantages of using the HD-6409 and
logic-O and Iogic-1 with a static level maintained throughout Manchester code are several fold. One is that Manchester is
the data cell. In contrast, Manchester code represents data a self clocking code. The clock in serial data communication
with a level transition in the middle of the data cell. Manches- defines the position of each data cell. Non self clocking
ter has bandwidth, error detection, and synchronization codes, as NRZ, often require an extra clock wire or clock
advantages over NRZ code.
track (in magnetic recording). Further, there can be a phase
variation between the clock and data track. Crosstalk
between the two may be a problem. In Manchester, the
serial data stream contains both the clock and the data, with
the position of the mid bit transition representing the clock,
and the direction of the transition representing data. There is
no phase variation between the clock and the data.
The Manchester II code Bipolar One and Bipolar Zero shown
below are logical complements. The direction of the transi-
tion indicates the binary value of data. A logic-0 in Bipolar
One is defined as a Low to high transition in the middle of
the data cell, and a logic-1 as a high to low mid bit transition,
Manchester Il is also known as Biphase-L code.
A second synchronization advantage is a result of the num-
ber of transitions in the data. The decoder resynchronizes on
each transition, or at least once every data cell. In contrast,
receivers using NRZ, which does not necessarily have tran-
sitions, must resynchronize on frame bit transitions, which
occur far less often, usually on a character basis. This more
frequent resynchronization eliminates the cumulative effect
of errors over successive data cells. A final synchronization
advantage concerns the HD-6409’s sync pulse used to ini-
tiate synchronization. This three bit wide pattern is suffi-
ciently distinct from Manchester data that a false start by the
receiver is unlikely.
The bandwidth of NRZ is from DC to the clock frequency fc/2,
while that of Manchester is from fc/2 to fc. Thus, Manchester
can be AC or transformer coupled, which has considerable
advantages over DC coupling. Also, the ratio of maximum to
minimum frequency of Manchester extends one octave, while
the ratio for NRZ is the range of 5-10 octaves. It is much eas-
ier to design a narrow band than a wideband amp.
Secondly, the mid bit transition in each data cell provides the
code with an effective error detection scheme. If noise pro-
duces a logic inversion in the data cell such that there is no
transition, an error indiction is given, and synchronization
must be re-established. This places relatively stringent
requirements on the incoming data.
BIT PERIOD
1
0
2
1
3
1
4
0
5
0
BINARY CODE
NONRETURN
TO ZERO
BIPOLAR ONE
BIPOLAR ZERO
FIGURE 4. MANCHESTER CODE
Crystal Oscillator Mode
LC Oscillator Mode
C1
I
X
C1
C1 = 32pF
I
X
C0 = CRYSTAL + STRAY
X1 = AT CUT PARALLEL
RESONANCE
16MHz
C1 = 20pF
C0 = 5pF
C0
R1
X1
FUNDAMENTAL
MODE
(TYP) = 30Ω
C1 – 2C0
L
C
≈ -------------------------
E
2
R
S
R1 = 15MΩ
1
O
f
≈ -----------------------
X
O
2π LC
e
C1
O
X
C
C1
O
FIGURE 5. CRYSTAL OSCILLATOR MODE
FIGURE 6. LC OSCILLATOR MODE
5-6
HD-6409
Using the 6409 as a Manchester Encoded UART
BZI
V
CC
BIPOLAR IN
BIPOLAR IN
BOI
BOO
BIPOLAR OUT
BIPOLAR OUT
UDI
BZO
SS
SD/CDS
SDO
ECLK
CTS
CTS
SRST
NVM
MS
OX
DCLK
RST
RESET
IX
GND
CO
LOAD
CK
LOAD
‘165
QH
SI CK LOAD QH
‘165
A
B
CK QH
A
B
CK
‘164
‘164
DATA IN
‘273
DATA IN
‘273
CP
PARALLEL DATA IN
PARALLEL DATA OUT
FIGURE 7. MANCHESTER ENCODER UART
5-7
HD-6409
Thermal Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance (Typical)
θ
θ
JC
JA
o
o
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CC
CERDIP. . . . . . . . . . . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . . . .
83 C/W
23 C/W
o
o
95 C/W
26 C/W
o
75 C/W
N/A
N/A
o
o
SOIC Package. . . . . . . . . . . . . . . . . . . . . 100 C/W
o
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature
o
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300 C
o
o
(
Lead Tips Only for Surface Mount Packages)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Temperature Range. . . . . . . . . . . . . . . . . -40 C to +85 C
o
o
Sync. Transition Span (t2) . . . . . . . . . . 1.5 DBP Typical, (Notes 1, 2)
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Short Data Transition Span (t4). . . . . . .0.5DBP Typical, (Notes 1, 2)
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . .50ns Max
NOTES:
Long Data Transition Span (t5) . . . . . . .1.0DBP Typical, (Notes 1, 2)
Zero Crossing Tolerance (tCD5) . . . . . . . . . . . . . . . . . . . . . .(Note 3)
1. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.
2. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by ±2 I clock cycles (16X mode)
X
or ±6 I clock cycles (32X mode).
X
3. The maximum zero crossing tolerance is ±2 I clock cycles (16X mode) or ±6 I clock cycles (32 mode) from the nominal.
X
X
o
o
DC Electrical Specifications V = 5.0V ± 10%, T = -40 C to +85 (HD-6409-9)
CC
A
SYMBOL
PARAMETER
MIN
MAX
UNITS
V
(NOTE 1) TEST CONDITIONS
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logic “1” Input Voltage (Reset)
Logic “0” Input Voltage (Reset)
Logical “1” Input Voltage (Clock)
Logical “0” Input Voltage (Clock)
70% V
-
V
V
V
V
V
V
V
V
= 4.5V
= 4.5V
= 5.5V
= 4.5V
= 5.5V
= 4.5V
IH
CC
CC
CC
CC
CC
CC
CC
IN
V
-
20% V
-
V
IL
CC
V
V
V
-0.5
-0.5
V
IHR
CC
V
-
GND +0.5
V
ILR
V
-
GND +0.5
+1.0
+20
V
IHC
CC
V
-
V
ILC
I
Input Leakage Current (Except I )
-1.0
-20
-10
µA
µA
µA
V
= V
or GND, V
= 5.5V
= 5.5V
I
I
X
CC
CC
CC
I
Input Leakage Current (I )
X
= V
or GND, V
IN
CC
I
I/O Leakage Current
+10
V
= V
CC
or GND, V
= 5.5V
CC
O
OUT
V
Output HIGH Voltage (All Except O )
V
-0.4
-
I
I
= -2.0mA, V
CC
= 4.5V (Note 2)
= 4.5V (Note 2)
OH
X
CC
OH
V
Output LOW Voltage (All Except O )
X
-
-
0.4
V
= +2.0mA, V
OL
OL
CC
I
Standby Power Supply Current
Operating Power Supply Current
Functional Test
100
µA
V
= V
CC
or GND, V
= 5.5V,
CCSB
IN
CC
Outputs Open
I
-
-
18.0
-
mA
-
f = 16.0MHz, V = V
or GND
CCOP
IN
CC
V
= 5.5V, C = 50pF
CC
L
F
(Note 1)
T
NOTES:
1. Tested as follows: f = 16MHz, V = 70% V , V = 20% V , V
≥ V /2, and V ≤ V /2, V = 4.5V and 5.5V.
CC
IH CC IL CC OH
CC
OL
CC
2. Interchanging of force and sense conditions is permitted
o
Capacitance T = +25 C, Frequency = 1MHz
A
SYMBOL
PARAMETER
TYP
UNITS
TEST CONDITIONS
All measurements are referenced to device GND
C
Input Capacitance
Output Capacitance
10
12
pF
pF
IN
C
OUT
5-8
HD-6409
o
o
AC Electrical Specifications V = 5.0V ±10%, T = -40 C to +85 C (HD-6409-9)
CC
A
SYMBOL
PARAMETER
MIN
MAX
UNITS
(NOTE 1) TEST CONDITIONS
f
t
Clock Frequency
-
16
-
MHz
sec
ns
-
-
-
-
C
Clock Period
1/f
C
C
t
Bipolar Pulse Width
t +10
C
-
1
t
One-Zero Overlap
-
20
20
120
0
t -10
C
ns
3
t
Clock High Time
-
-
ns
f = 16.0MHz
f = 16.0MHz
CH
t
Clock Low Time
ns
CL
t
Serial Data Setup Time
Serial Data Hold Time
DCLK to SDO, NVM
-
ns
-
-
-
-
CE1
CE2
CD2
t
-
ns
t
-
40
40
50
50
11
11
1.0
1.5
11.5
1.0
2.5
3.0
1.5
1.5
1.0
3.0
ns
t
ECLK to BZO
-
ns
R2
t
Output Rise Time (All except Clock)
Output Fall Time (All except Clock)
Clock Output Rise Time
Clock Output Fall Time
ECLK to BZO, BOO
-
ns
From 1.0V to 3.5V, C = 50pF, Note 2
L
r
t
-
ns
From 3.5V to 1.0V, C = 50pF, Note 2
L
f
t
-
ns
From 1.0V to 3.5V, C = 20pF, Note 2
L
r
t
-
ns
From 3.5V to 1.0V, C = 20pF, Note 2
L
f
t
t
t
t
t
0.5
0.5
10.5
-
DBP
DBP
DBP
DBP
DBP
DBP
DBP
DBP
DBP
DBP
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
Notes 2, 3
CE3
CE4
CE5
CE6
CE7
CD1
CD3
CD4
CTS Low to BZO, BOO Enabled
CTS Low to ECLK Enabled
CTS High to ECLK Disabled
CTS High to BZO, BOO Disabled
UDI to SDO, NVM
1.5
2.5
0.5
0.5
0.5
2.5
t
t
t
RST Low to CDLK, SDO, NVM Low
RST High to DCLK, Enabled
UDI to BZO, BOO
t
t
R1
R3
UDI to SDO, NVM
NOTES:
1. AC testing as follows: f = 4.0MHz, V = 70% V , V = 20% V , Speed Select = 16X, V
≥ V /2, V ≤ V /2, V
CC OL CC
= 4.5V and
CC
IH CC IL CC OH
5.5V. Input rise and fall times driven at 1ns/V, Output load = 50pF.
2. Guaranteed via characteristics at initial device design and after major process and/or design changes, not tested.
3. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.
5-9
HD-6409
Timing Waveforms
NOTE: UDI = 0, FOR NEXT DIAGRAMS
BIT PERIOD
BIT PERIOD
BIT PERIOD
BOI
BZI
T
1
T
T
T
3
3
2
T
1
T
2
COMMAND SYNC
T
1
BOI
BZI
T
T
T
2
3
3
T
1
DATA SYNC
T
2
T
T
1
1
BOI
BZI
T
T
T
T
T
3
3
3
3
3
T
1
T
T
T
T
4
4
5
5
ONE
ZERO
NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS
ONE
T
T
T
2
2
2
UDI
UDI
COMMAND SYNC
T
2
DATA SYNC
ONE
T
T
T
T
T
UDI
4
5
5
4
4
ZERO
ONE
ONE
FIGURE 8.
t
C
t
t
f
r
t
t
CL
r
90%
10%
3.5V
1.0V
t
CH
t
f
FIGURE 9. CLOCK TIMING
FIGURE 10. OUTPUT WAVEFORM
5-10
HD-6409
Timing Waveforms (Continued)
ECLK
t
CE2
t
CE1
SD/CDS
t
CE3
BZO
BOO
FIGURE 11. ENCODER TIMING
CTS
CTS
t
CE6
BZO
BOO
ECLK
t
CE7
t
CE4
BZO
BOO
t
CE5
ECLK
FIGURE 12. ENCODER TIMING
FIGURE 13. ENCODER TIMING
DCLK
UDI
t
CD5
MANCHESTER MANCHESTER MANCHESTER MANCHESTER
LOGIC-1 LOGIC-0 LOGIC-0 LOGIC-1
t
CD1
t
CD2
SDO
NVM
NRZ
LOGIC-1
t
CD2
NOTE: Manchester Data-In is not synchronous with Decoder Clock.
Decoder Clock is synchronous with decoded NRZ out of SDO.
FIGURE 14. DECODER TIMING
50%
RST
RST
50%
t
CD3
t
CD4
DCLK, SDO,
NVM
50%
DCLK
FIGURE 15. DECODER TIMING
FIGURE 16. DECODER TIMING
5-11
HD-6409
Timing Waveforms (Continued)
UDI
MANCHESTER ‘1’
ECLK
MANCHESTER ‘0’
MANCHESTER ‘0’
MANCHESTER ‘1’
t
R2
t
t
R2
R1
BZO
MANCHESTER ‘1’
MANCHESTER ‘0’
MANCHESTER ‘0’
t
R3
SDO
NVM
t
R3
FIGURE 17. REPEATER TIMING
Test Load Circuit
DUT
C
L
(NOTE)
NOTE: INCLUDES STRAY AND JIG
CAPACITANCE
FIGURE 18. TEST LOAD CIRCUIT
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5-12
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