HI1-0307-5 [INTERSIL]
CMOS Analog Switches; CMOS模拟开关
| 型号： | HI1-0307-5 |
| 厂家： | 
Intersil |
| 描述： | CMOS Analog Switches |
| 文件： | 总11页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-301 thru HI-307
TM
Data Sheet
March 2000
File Number 3125.4
CMOS Analog Switches
Features
The HI-301 thru HI-307 series of switches are monolithic
devices fabricated using CMOS technology and the Intersil
dielectric isolation process. These switches feature break
before-make switching, low and nearly constant ON
resistance over the full analog signal range, and low power
dissipation, (a few mW for the Hl-301 and HI-303, a few
hundred mW for the HI-307).
• Analog Signal Range (±15V Supplies) . . . . . . . . . . ±15V
o
• Low Leakage at 25 C . . . . . . . . . . . . . . . . . . . . . . . 40pA
o
• Low Leakage at 125 C . . . . . . . . . . . . . . . . . . . . . . . 1nA
o
• Low On Resistance at 25 C . . . . . . . . . . . . . . . . . . . 35Ω
• Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns
• Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pC
• TTL, CMOS Compatible
The HI-301 and HI-303 are TTL compatible and have a logic
“0” condition with an input less than 0.8V and a logic “1”
condition with an input greater than 4V. The HI-307 switches
are CMOS compatible and have a low state with an input
less than 3.5V and a high state with an input greater than
11V. (See pinouts for switch conditions with a logic “1” input.)
• Symmetrical Switch Elements
• Low Operating Power (Typ for Hl-301 and HI-303) . . 1.0mW
Applications
Ordering Information
• Sample and Hold (i.e., Low Leakage Switching)
• Op Amp Gain Switching (i.e., Low On Resistance)
• Portable, Battery Operated Circuits
• Low Level Switching Circuits
PART
NUMBER
TEMP.
RANGE ( C)
o
PACKAGE
14 Ld SOIC
PKG. NO.
M14.15
F14.3
HI9P0301-5
HI1-0303-2
HI1-0303-5
HI9P0303-5
HI9P0303-9
HI1-0307-5
0 to 75
-55 to 125
0 to 75
14 Ld CERDIP
14 Ld CERDIP
14 Ld SOIC
• Dual or Single Supply Systems
F14.3
0 to 75
M14.15
M14.15
F14.3
Functional Diagram
-40 to 85
0 to 75
14 Ld SOIC
S
14 Ld CERDIP
IN
N
P
D
Pinouts Switch States Shown For A Logic “1” Input
SPST HI-301
(SOIC)
DUAL SPDT HI-303 (CERDIP, SOIC)
HI-307 (CERDIP)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
V+
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
V+
D
1
D
2
S
3
S
4
NC
NC
D
3
D
4
S
1
S
2
D
1
D
2
NC
IN
NC
NC
V-
S
1
S
2
IN
1
IN
2
8
GND
GND
8
V-
LOGIC
SW1
OFF
ON
SW2
ON
LOGIC
SW1, SW2 SW3, SW4
0
1
0
1
OFF
ON
ON
OFF
OFF
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1
HI-301 thru HI-307
Schematic Diagrams
SWITCH CELL
A
V+
MN1B
MN2B MN3B
MP5B
MP4B
MN4B
IN
OUT
MN6B
MP3B MP2B
MP1B
V-
A
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
V+
D2A
MP1A
MN1A
MP2A
MN2A
MP3A
MN3A
MP4A
MP5A
MN5A
MP6A
MN6A
MP7A
MP8A
MN8A
200Ω
A
A
LOGIC
IN
D1A
MN4A
MN7A
GND
V-
SWITCH CELL DRIVER
(ONE PER SWITCH CELL)
2
HI-301 thru HI-307
Absolute Maximum Ratings
Thermal Information
o
o
Voltage Between Supplies (V+ to V-). . . . . . . . . . . . . . . .44V (±22V)
Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V
Analog Input Voltage . . . . . . . . . . . . . . . . . . (V+) +1.5V to (V-) -1.5V
Typical Derating Factor . . . . . . . . . 1.5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
CERDIP Package. . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
95
120
40
N/A
o
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
o
Operating Conditions
o
Temperature Range
HI-3XX-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HI-3XX-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
HI-3XX-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
(SOIC - Lead Tips Only)
o
o
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications Supplies = +15V, -15V; V = Logic Input. HI-301 and HI-303: V - for Logic “1” = 4V, for Logic “0” = 0.8V.
IN
IN
HI-307: V - for Logic “1” = 11V, for Logic “0” = 3.5V, Unless Otherwise Specified
IN
-2
-5, -9
TYP
TEMP
o
PARAMETER
( C)
MIN
TYP
MAX
MIN
MAX
UNITS
DYNAMIC CHARACTERISTICS
Switch ON Time, t
(Note 13)
25
25
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
-
210
160
160
100
60
3
300
-
-
-
-
-
-
-
-
-
-
-
210
160
160
100
60
3
300
ns
ns
ON
Switch OFF Time, t
(Note 13)
250
250
OFF
Switch ON Time, t
(Note 14)
250
250
ns
ON
Switch OFF Time, t
(Note 14)
150
150
ns
OFF
Break-Before-Make Delay, t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
OPEN
Charge Injection Voltage, ∆V (Note 7)
mV
dB
pF
pF
pF
pF
OFF Isolation (Note 6)
60
16
14
35
5
60
16
14
35
5
Input Switch Capacitance, C
S(OFF)
Output Switch Capacitance, C
D(OFF)
D(ON)
Output Switch Capacitance, C
Digital Input Capacitance, C
IN
DIGITAL INPUT CHARACTERISTICS
Input Low Level, V (Note 13)
Full
Full
Full
Full
Full
Full
-
4
-
-
-
-
-
-
-
0.8
-
-
4
-
-
-
-
-
-
-
0.8
-
V
V
INL
Input High Level, V
(Note 13)
INH
Input Low Level, V
(Note 14)
3.5
-
3.5
-
V
INL
Input High Level, V
(Note 14)
11
-
11
-
V
INH
Input Leakage Current (Low), I
(Note 5)
1
1
µA
µA
INL
Input Leakage Current (High), I
(Note 5)
-
1
-
1
INH
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range
Full
25
-15
-
35
40
0.04
1
+15
50
-15
-
+15
50
V
Ω
ON Resistance, r
ON
(Note 2)
-
-
-
-
-
-
-
-
35
Full
25
75
40
75
Ω
OFF Input Leakage Current, I
(Note 3)
1
0.04
0.2
5
nA
nA
S(OFF)
Full
100
100
3
HI-301 thru HI-307
Electrical Specifications Supplies = +15V, -15V; V = Logic Input. HI-301 and HI-303: V - for Logic “1” = 4V, for Logic “0” = 0.8V.
IN
IN
HI-307: V - for Logic “1” = 11V, for Logic “0” = 3.5V, Unless Otherwise Specified (Continued)
IN
-2
TYP
0.04
1
-5, -9
TYP
0.04
0.2
TEMP
( C)
o
PARAMETER
OFF Output Leakage Current, I
MIN
MAX
1
MIN
MAX
5
UNITS
nA
(Note 3)
25
Full
25
-
-
-
-
-
-
-
-
D(OFF)
100
1
100
5
nA
ON Leakage Current, I
(Note 4)
0.03
0.5
0.03
0.2
nA
D(ON)
Full
100
100
nA
POWER SUPPLY CHARACTERISTICS
Current, I+ (Notes 8, 13)
25
Full
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.09
0.5
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.09
0.5
1
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
-
-
Current, I- (Notes 8, 13)
Current, I+ (Notes 9, 13)
Current, I- (Notes 9, 13)
Current, I+ (Notes 10, 14)
Current, I- (Notes 10, 14)
Current, I+ (Notes 11, 14)
Current, I- (Notes 11, 14)
NOTES:
0.01
10
0.01
100
-
Full
25
-
100
10
-
0.01
0.01
100
-
Full
25
-
100
10
-
0.01
0.01
100
-
Full
25
-
100
10
-
0.01
0.01
100
-
Full
25
-
100
10
-
0.01
0.01
100
-
Full
25
-
0.01
-
100
10
-
0.01
-
100
-
Full
25
100
10
0.01
-
0.01
-
100
-
Full
100
2. V = ±10V, I
=
10mA. On resistance derived from the voltage measured across the switch under these conditions.
14V.
S
OUT
3. V = ±14V, V
=
D
S
4. V = V = ±14V.
S
D
5. The digital inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected.
6. V = 1V , f = 500kHz, C = 15pF, R = 1K.
S
RMS
L
L
7. V = 0V, C = 10nF, Logic Drive = 5V pulse (HI-301 - 303), 15V pulse (HI-307). Switches are symmetrical; S and D may be interchanged. Charge
S
L
Injection = Q = C x ∆V.
L
8. V = 4V (one input, all other inputs = 0V).
IN
9. V = 0.8V (all inputs).
IN
10. V = 15V (all inputs).
IN
11. V = 0V (all inputs).
IN
12. To drive from DTL/TTL circuits, pullup resistors to +5V supply are recommended.
13. HI-301 thru HI-303 only.
14. HI-307 only.
4
HI-301 thru HI-307
Test Circuits and Waveforms
V+
15V
LOGIC “1” = SWITCH ON
S
V
O
D
R
SWITCH
OUTPUT
V
= +3V
S
V
LOGIC
INPUT
0V
INH
C
L
L
300Ω
33pF
50%
50%
LOGIC
INPUT
V
S
V-
-15V
90%
GND
10%
0V
SWITCH
OUTPUT
t
SWITCH TYPE
V
INH
OFF
t
ON
HI-301 and HI-303
HI-307
4V
15V
FIGURE 1A. TEST CIRCUIT
FIGURE 1B. MEASUREMENT POINTS
FIGURE 1. SWITCH t
ON
AND t
OFF
+15V
V+
6
4
2
0
HI-301 AND HI-303
R
= 0
GEN
S
D
R
C
10pF
L
L
V
GEN
10kΩ
LOGIC INPUT
IN
V-
-15V
GND
V
LOGIC
0
0.4
0.8
1.2
1.6
TIME (µs)
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. TTL LOGIC INPUT
15
10
5
HI-307
10
5
(NOTE 16)
V
= 10V
GEN
0
0
LOGIC INPUT
0
0.4
0.8
TIME (µs)
1.2
1.6
0
0.4
0.8
TIME (µs)
1.2
1.6
FIGURE 2C. CMOS LOGIC INPUT
FIGURE 2D. V = 10V
ANALOG
5
HI-301 thru HI-307
Test Circuits and Waveforms (Continued)
5
0
5
0
V
= 5V
V
= 0V
GEN
GEN
-5
0
0.4
0.8
1.2
1.6
0
0.4
0.8
1.2
1.6
TIME (µs)
TIME (µs)
FIGURE 2E. V
= 5V
FIGURE 2F. V
ANALOG
= 0V
ANALOG
0
-5
0
-5
V
= -5V
GEN
-10
V
= -10V
GEN
0
0.4
0.8
TIME (µs)
1.2
1.6
0
0.4
0.8
1.2
1.6
TIME (µs)
FIGURE 2G. V
ANALOG
= -5V
FIGURE 2H. V
ANALOG
= -10V
NOTE:
15. If R
, R or C is increased, there will be proportional increases in rise and/or fall RC times.
GEN
L
L
FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES
15V
V+
S
S
D
D
1
2
1
OUT 1
OUT 2
V
V
= +3V
= +3V
S1
2
LOGIC “1” = SWITCH ON
INH
S2
R
C
= R = 300Ω
LOGIC
INPUT
L1
L1
L2
V
= C = 33pF
L2
R
C
R
C
L1
L2
L2
L1
0V
LOGIC
INPUT
V-
-15V
50%
50%
GND
OUT 1
OUT 2
0V
SWITCH
SWITCH TYPE
HI-301, HI-303
HI-307
V
INH
OUTPUTS
50%
0V
50%
5V
t
t
OPEN
OPEN
15V
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE DELAY (t
)
OPEN
6
HI-301 thru HI-307
Typical Performance Curves
80
60
40
20
0
80
o
D
C
T
= 25 C
V+ = +15V, V- = -15V
A
60
o
125 C
o
25 C
B
A
40
20
0
o
-55 C
A V+ = +15V, V- = -15V
B V+ = +10V, V- = -10V
C V+ = +7.5V, V- = -7.5V
D V+ = +5V, V- = -5V
-15
-10
-5
0
5
10
15
-15
-10
-5
0
5
10
15
DRAIN VOLTAGE (V)
DRAIN VOLTAGE (V)
FIGURE 4. r
DS(ON)
vs V
FIGURE 5. r vs V
DS(ON) D
D
100
80
60
40
20
0
100
10
V+ = +15V, V- = -15V
o
V+ = +15V, V- = -15V
= 30pF, V = 1V
RMS
C
LOAD
S
T
= 25 C, V = 15V, R = 2K
S L
A
R
= 100Ω
L
R
= 1kΩ
L
HI-301 AND HI-303
HI-307
1.0
0.1
5
6
7
8
1
10
100
1K
10K
100K
1M
10
10
10
10
FREQUENCY (Hz)
LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz)
FIGURE 6. DEVICE POWER DISSIPATION vs SWITCHING
FREQUENCY (SINGLE LOGIC INPUT)
FIGURE 7. OFF ISOLATION vs FREQUENCY
10.0
10.0
1.0
V+ = +15V, V- = -15V
V+ = +15V, V- = -15V
| V | = | V | = 14V
D
S
1.0
0.1
0.1
0.01
0.01
25
75
125
25
75
125
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 8. I
OR I
D(OFF)
vs TEMPERATURE†
FIGURE 9. I
vs TEMPERATURE†
D(ON)
S(OFF)
† The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or
zero depending on the analog voltage and temperature, and will vary greatly from unit to unit.
7
HI-301 thru HI-307
Typical Performance Curves (Continued)
16
12
8
60
50
40
30
20
TRANSITION (INDETERMINATE
DUE TO ACTIVE INPUT)
HI-301 AND HI-303
HI-307
4
TRANSITION
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
DRAIN VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 10. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE
FIGURE 11. DIGITAL INPUT CAPACITANCE vs INPUT VOLTAGE
300
300
V+ = +15V, V- = -15V
V+ = +15V, V- = -15V
V
= 15V, V = 0V
INH
INL
V
= 4.0V, V = 0V
INL
INH
t
ON
200
100
200
100
t
ON
t
OFF
t
OFF
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 12. SWITCHING TIME vs TEMPERATURE, HI-301 AND
HI-303
FIGURE 13. SWITCHING TIME vs TEMPERATURE, HI-307
300
o
o
V+ = +15V, T = 25 C
A
V+ = +15V, T = 25 C
A
V
= 15V, V = 0V
V
= 4V, V = 0V
INH
INL
t
INH
INL
ON
300
200
100
t
ON
200
100
t
OFF
t
OFF
0
5
10
15
0
5
10
15
NEGATIVE SUPPLY (V)
NEGATIVE SUPPLY (V)
FIGURE 14. SWITCHING TIME vs NEGATIVE SUPPLY
VOLTAGE, HI-301 AND HI-303
FIGURE 15. SWITCHING TIME vs NEGATIVE SUPPLY
VOLTAGE, HI-307
8
HI-301 thru HI-307
Typical Performance Curves (Continued)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
o
o
V- = -15V, T = 25 C
A
V- = -15V, T = 25 C
A
V
= 15V, V
= 0V
V
= 4.0V, V = 0V
INL
INH
INL
INH
t
ON
t
t
OFF
OFF
t
t
ON
OPEN
HI-301/303 ONLY
0
5
10
15
0
5
10
15
POSITIVE SUPPLY VOLTAGE (V)
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 16. SWITCHING TIME AND BREAK-BEFORE-MAKE
TIME vs POSITIVE SUPPLY VOLTAGE, HI-301
AND HI-303
FIGURE 17. SWITCHING TIME vs POSITIVE SUPPLY
VOLTAGE, HI-307
7
o
V- = -15V, T = 25 C
A
6
5
4
3
2
1
0
HI-307
HI-301 AND 303
0
5
10
15
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 18. INPUT SWITCHING THRESHOLD vs POSITIVE SUPPLY VOLTAGE
9
HI-301 thru HI-307
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES MILLIMETERS
MIN
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
10
HI-301 thru HI-307
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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11
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