HI20206JCP [INTERSIL]
Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter; 三重8位， 35 MSPS ， RGB ，3通道D / A转换器
| 型号： | HI20206JCP |
| 厂家： | 
Intersil |
| 描述： | Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter |
| 文件： | 总13页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Semiconductor
HI20206
Triple 8-Bit, 35 MSPS, RGB,
3-Channel D/A Converter
August 1997
Features
Description
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . .Triple 8-Bit
The HI20206 is a triple 8-bit, high-speed, bipolar D/A
• Maximum Conversion Speed . . . . . . . . . . . . . . . 35MHz converter designed for video band use. It has three sepa-
rate, 8-bit pixel inputs, one each for red, green, and blue
• RGB 3-Channel Input/Output
video data. A single 5.0V power supply and pixel clock input
is all that is required to make the device operational. A bias
voltage generator is internal. For lower CMOS power
consumption, refer to the HI1178.
1
• Differential Linearity Error . . . . . . . . . . . . . . . ± / LSB
2
• Digital Input Voltage . . . . . . . . . . . . . . . . . . . .TTL Level
• Output Voltage Full-Scale . . . . . . . . . . . . . . 1V
P-P
(Typ)
• Low Power Consumption . . . . . . . . . . . . . 360mW (Typ)
• +5V Single Power Supply
Ordering Information
TEMP.
o
• Direct Replacement for Sony CX20206
PART NUMBER RANGE ( C)
PACKAGE
PKG. NO.
Applications
• Digital TV
HI20206JCP
-20 to 75
42 Ld PDIP
E42.6B-S
• Graphics Display
• High Resolution Color Graphics
• Video Reconstruction
• Instrumentation
• Image Processing
• I/Q Modulation
Pinout
HI20206 (PDIP)
TOP VIEW
R5
R6
R7
R8
G1
G2
G3
G4
G5
1
2
3
4
5
6
7
8
9
42 R4
41 R3
40 R2
39 R1
38 NC
37 DGND
36 NC
35 ROUT
34 NC
G6 10
G7 11
G8 12
B1 13
B2 14
B3 15
B4 16
B5 17
33 GOUT
32 NC
31 BOUT
30 NC
29 AV
CC
28 NC
27
26
V
V
SET
REF
B6 18
B7 19
25 AGND
24 NC
B8 20
23 NC
CLK 21
22 DV
CC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 4111.1
Copyright © Harris Corporation 1997
10-1
HI20206
Functional Block Diagram
DGND
37
33 ROUT
33 GOUT
31 BOUT
R1 39
R2 40
DECODER
R
R
R
R
R
2
3
3
2R
2R
2R
R3 41
R4 42
INPUT
CURRENT
SWITCH
(R)
BUFFER
(R)
6
6
R5
R6
R7
R8
G1
G2
G3
G4
G5
1
2
3
4
5
6
7
8
9
R
R
2R
2R
R
DECODER
2
3
3
6
R
R
R
R
R
2R
2R
2R
INPUT
BUFFER
(G)
CURRENT
SWITCH
(G)
6
G6 10
G7 11
G8 12
B1 13
B2 14
B3 15
B4 16
B5 17
B6 18
B7 19
B8 20
R
R
2R
2R
R
3
R
R
R
R
R
DECODER
2
3
2R
2R
2R
INPUT
BUFFER
(B)
CURRENT
SWITCH
(B)
6
6
R
R
2R
2R
R
29 AV
CC
CLOCK
INTERNAL
BUFFER
REFERENCE
VOLTAGE
SOURCE
-
+
21
CLK
22
23
26
27
DV
CC
AGND
V
V
REF
RET
10-2
HI20206
Pin Descriptions
PIN NO.
SYMBOL
EQUIVALENT CIRCUIT
DESCRIPTION
1 To 20
39 To 42
R1 To R8
G1 To G8
B1 To B8
Digital Input pin. From pins 39 to 42 and from 1
to 4 are for RED. R1 is MSB and R8 is LSB.
From pins 5 to 12 are for GREEN. G1 is MSB
and G8 is LSB. From pins 13 to 20 are for
BLUE. B1 is MSB and B8 is LSB.
DV
CC
22
39 - 42
1 ~ 20
37
DGND
21
CLK
Clock Input pin.
DV
CC
22
21
37
DGND
22
DV
Digital V .
CC
CC
23
24
NC
No Connect.
25
26
AGND
Analog GND.
V
Bias Input pin. Normally, apply 0.8V.
AV
SET
CC
29
54K
26
25
AGND
27
V
Internal Reference Voltage Output pin 1.2V
(Typ). A pulldown resistance is necessary
externally.
REF
AV
CC
29
27
25
20P
AGND
10-3
HI20206
Pin Descriptions (Continued)
PIN NO.
SYMBOL
EQUIVALENT CIRCUIT
DESCRIPTION
28
NC
No Connect.
Analog V .
CC
29
AV
CC
30
NC
Vacant pin but connect to AV
Analog Output pin for BLUE.
(Note 1).
CC
31
BOUT
AV
CC
29
R
O
31
25
AGND
32
33
NC
Vacant pin but connect to AV
(Note 1).
CC
GOUT
Analog Output pin for GREEN.
AV
CC
29
R
O
33
25
AGND
34
35
NC
Vacant pin but connect to AV
Analog Output pin for RED.
(Note 1).
CC
ROUT
AV
CC
29
R
O
35
25
AGND
36
37
38
NC
DGND
NC
Vacant pin but connect to AV
Digital GND.
(Note 1).
CC
No Connect.
NOTE:
1. Pins 30, 32, 34 and 36 are vacant, but in order to reduce interference between the individual RGB outputs, connect them to AV
.
CC
10-4
HI20206
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 7V Thermal Resistance (Typical, Note 2)
CC
θJA ( C/W)
Input Voltage (Digital) (V , V
) . . . . . . . . . . . . . . . . . -0.3V to V
I
CLK
CC
CC
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
o
o
Output Voltage (Analog) (V ) . . . . . . . . . . . . . . V
SET
-2.1V to V
CC
Maximum Storage Temperature Range (T ) . . . .-65 C to 150 C
STG
o
Output Current
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
Analog (I
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 10mA
OUT
V
Pin (I ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 0mA
REF
REF
Supply Voltage Range (Typ). . . . . . . . . . . . . . . . . . . . . . . 5V to 10V
Recommended Operating Conditions
Supply Voltage
AV , DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
CC
CC
AV -DV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 0.2V
CC
CC
AGND-DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V
Digital Input Voltage
H Level (V , V
) . . . . . . . . . . . . . . . . . . . . . . . .2.0V to DV
CC
IH CLKH
L Level (V , V
IL CLKL
) . . . . . . . . . . . . . . . . . . . . . . . . DGND to 0.8V
V
V
Input Voltage (V
). . . . . . . . . . . . . . . . . . . . . . .0.7V to 0.9V
SET
SET
). . . . . . . . . . . . . . . . . . . . . . -3mA to -0.4mA
Pin Current (I
REF
REF
Clock Pulse Width
t
t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10ns
PW1
PW0
o
o
Temperature Range (T
) . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
OPR
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications T = 25 C, AV = DV = 5V, AGND = DGND = 0V
A
CC
CC
TEST
PARAMETER
SYMBOL
RSL
CONDITIONS
MIN
-
TYP
MAX
-
UNITS
Bit
Resolution
Monotonic
8
MNT
DLE
-
Guarantee
-
-
Differential Linearity Error
Integral Linearity Error
V
- AGND = 0.8V,
-0.5
-0.4
-
-
0.5
0.4
LSB
SET
R > 10kΩ
L
ILE
% of Full
Scale
Maximum Conversion Speed
f
V
- AGND = 0.8V,
SET
35
0.85
0
-
-
1.15
8
MHz
MAX
R > 10kΩ, C < 20pF
L
L
Full Scale Output Voltage (Note 3)
V
1.0
4
V
OFS
FSR
P-P
%
RGB Output Voltage Full Scale Ratio (Note 4)
Output Zero Offset Voltage
Output Resistance
V
-40
270
54
-6
0
mV
Ω
OFFSET
R
340
72
420
90
O
Dissipation Current
I
V
- AGND = 0.8V,
mA
D
SET
R > 10kΩ, I
= -400µA
L
REF
Digital Data Input
Current
H Level
L Level
Upper 2 Bits
Lower 6 Bits
Upper 2 Bits
Lower 6 Bits
H Level
I
V = DV
CC
-
-
1.2
0.6
0
20
10
10
10
30
10
0
µA
µA
µA
µA
µA
µA
µA
V
IH(U)
I
I
IH(L)
IL(U)
IL(U)
I
V = DGND
-10
-10
-
I
I
0
Clock Input Current
I
V
V
V
= DV
CC
3
CLKH
CLK
CLK
SET
REF
L Level
I
= DGND
-10
-5
0
CLKL
V
Input Current
I
- AGND = 0.8V
-0.3
1.20
-
SET
SET
Internal Reference Voltage
Set-Up Time
V
I
= -400µA
1.08
12
3
1.32
-
REF
t
ns
ns
dB
S
Hold Time
t
-
-
H
Crosstalk Among R, G and B
CT
D/A OUT: 1V
, R >10kΩ,
-
-40
-33
P-P
L
C <20pF, f
= 7MHz,
L
DATA
f
= 14MHz, See Figure 5
CLK
10-5
HI20206
o
Electrical Specifications T = 25 C, AV = DV = 5V, AGND = DGND = 0V (Continued)
A
CC
CC
TEST
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Glitch Energy
GE
V
- AGND = 0.8V,
-
160
-
pV/s
SET
R >10kΩ, f
= 1MHz,
L
CLK
Digital Ramp Output,
See Figure 6 (Note 5)
Rise Time (Note 6)
Fall Time (Note 6)
Settling Time
t
V
- AGND = 0.8V
SET
-
-
-
5.5
5.0
16
-
-
-
ns
ns
ns
r
See Figure 4
t
f
t
SET
NOTES:
3. AV
- V .
O
CC
4. Maximum value among
V
V
V
OFS(B)
V
OFS(R)
OFS(R)
OFS(G)
.
100 × ----------------------- – 1 , 100 × ----------------------- – 1 , or 100 × ----------------------- – 1
V
V
OFS(G)
OFS(B)
5. Observe the glitch which is generated when the digital input varies as follows:
0
0
1 1
1
1
1
1
1
1
1
1
1
1
1
1
— 0
— 1
— 1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
01 1 1 1
10 1 1 1
6. The time required for the D/A OUT to arrive at 90% of its final value from 10%.
INPUT CORRESPONDING TABLE
INPUT CODE OUTPUT VOLTAGE
MSB
LSB
1 1 1 1 1 1 1 1
V
+ V
OFFSET
CC
•
•
•
1 0 0 0 0 0 0 0
V
V
+ V
-0.5V
CC
OFFSET
•
•
•
•
•
•
0 0 0 0 0 0 0 0
+ V
-1.0V
CC
OFFSET
NOTE: In case the output voltage full scale is 1V (1 LSB = 3.92mV).
Test Circuits
37
D1 ~ D8
DV
CC
39 - 42
1 ~ 4
8 (R)
ROUT
D1
D2
35
D1 ~ D8
GOUT
BOUT
5 ~ 12
33
31
29
27
26
8 (G)
V
D1 ~ D8
AV
CC
REF
SET
13 ~ 20
D8
V
V
8 (B)
3K
+
-
DGND
V
25
22
33µF
CLK TTL LEVEL
21
CLK
HI20206
FIGURE 1. DIFFERENTIAL LINEARITY AND INTEGRAL LINEARITY TEST CIRCUITS
10-6
HI20206
Test Circuits (Continued)
(MSB)
OUT D1
DIGITAL RAMP
WAVEFORM GENERATION
37
35
D1 ~ D8
39 - 42
1 ~ 4
D2
8 (R)
ROUT
D1 ~ D8
8-BIT
COUNTER
(TTL OUTPUT)
GOUT
BOUT
5 ~ 12
33
31
8 (G)
(LSB)
D8
OSCILLOSCOPE
D1 ~ D8
13 ~ 20
R
C
= 1MΩ
= 10pF
29
26
IN
IN
8 (B)
V
SET
IN
BW = 20MHZ
12.5K
+
V
-
25
22
32µF
21
CLK
HI20206
MCLK
f = 35MHz
TTL LEVEL
RECTANGULAR
WAVE
AGND DGND
CLK
2ns ~ 10ns
AV
DV
CC
CC
D1 ~ D8
TIMING BETWEEN CLK AND DATA
FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT
37
D1 ~ D8
39 - 42
1 ~ 4
8 (R)
8 (G)
8 (B)
DV
ROUT
GOUT
CC
35
33
31
29
27
26
5 ~ 12
BOUT
V
13 ~ 20
AV
CC
V
V
REF
SET
3K
+
-
V
25
22
33µF
CLK TTL LEVEL
21
CLK
HI20206
FIGURE 3. OUTPUT VOLTAGE FULL SCALE PRECISION, RGB OUTPUT VOLTAGE FULL SCALE RATIO, AND OUTPUT ZERO
OFFSET VOLTAGE TEST CIRCUITS
10-7
HI20206
Test Circuits (Continued)
HI20206
1m
COAXAL CABLE
37
D1 ~ D8
8 (R)
ROUT
GOUT
BOUT
39 - 42
1 ~ 4
COAXAL
CABLE
35
33
OBSERVE DATA
WAVEFORM WITH
AN OSCILLOSCOPE
50
50
50
330 51
330 51
330 51
OBSERVE WITH
AN OSCILLOSCOPE
(
R
= 1MΩ
R
= 1MΩ
5 ~ 12
IN
IN
COAXAL
CABLE
(
(
8 (G)
8 (B)
BW = 200MHz
BW = 200MHz
13 ~ 20
COAXAL CABLE (1m)
1.2K
COAXAL
CABLE
31
29
26
25
22
47
50
V
SET
12.5K
+
-
CLK
1.2K
21
(TTL)
33µF
1
/
2
DIVIDER
OBSERVE CLK WITH
AN OSCILLOSCOPE
COAXIAL CABLE (1m)
f = 35MHz
(
R
= 1MΩ
IN
TTL LEVEL
(
50
BW = 200MHz
47
PULSE GENERATOR
8082A (YHP)
f = 35MHz
TTL LEVEL RECTANGULAR WAVE
AGND DGND AV
DV
CC
CC
PULSE GENERATOR
8082A (YHP)
D
DELAY
ADJUSTMENT
FIGURE 4. SET-UP TIME, HOLD TIME, AND RISE AND FALL TIME TEST CIRCUITS
D1 ~ D8
39 - 42
37
1 ~ 4
8 (R)
8 (G)
8 (B)
50Ω
EXIT
ROUT
35
5 ~ 12
FET
PROBE
SPECTRUM
ANALYZER
GOUT
BOUT
f = 7MHz
TTL LEVEL
RECTANGULAR WAVE
33
31
13 ~ 20
P6202 (TEKTRONIX)
1
30, 32
34, 36
/
2
DIVIDER
AV
CC
29
26
V
SET
12.5K
+
-
25
22
MCLK
f = 14MHz
TTL LEVEL
33µF
21
CLK
RECTANGULAR WAVE
HI20206
Measuring Method, in case the measuring crosstalk of G → R:
1. Apply the data to G only, and measure the power of the frequency component of the data at R
2. Apply the data to R only, and measure the power of the frequency component of the data at R
3. Take the difference of the above two powers; the unit is in dB.
.
.
OUT
OUT
FIGURE 5. CROSSTALK AMONG R, G, AND B TEST CIRCUIT
10-8
HI20206
Test Circuits (Continued)
(MSB)
D1
DIGITAL RAMP
WAVEFORM GENERATION
37
35
D1 ~ D8
OUT
39 - 42
1 ~ 4
D2
8 (R)
ROUT
D1 ~ D8
8-BIT
COUNTER
(TTL OUTPUT)
GOUT
BOUT
5 ~ 12
33
31
8 (G)
(LSB)
D8
OSCILLOSCOPE
D1 ~ D8
R
C
= 1MΩ
= 20 F
P
13 ~ 20
IN
29
27
26
8 (B)
V
IN
REF
100pF
BW = 5MHZ
IN
V
SET
3K
+
-
V
25
22
33µF
21
CLK
HI20206
MCLK
f = 35MHz
TTL LEVEL
RECTANGULAR
WAVE
AGND DGND
CLK
5ns ~ 300ns
AV
DV
CC
CC
D1 ~ D8
TIMING OF CLK AND DATA
FIGURE 6. GLITCH ENERGY TEST CIRCUIT
37
39 - 42
1 ~ 4
DATA (R)
(TTL LEVEL)
R
†
8
8
8
-
ROUT
LPF
LPF
LPF
ROUT
+
35
33
31
(G)
(B)
5 ~ 12
R
R
†
†
-
GOUT
BOUT
GOUT
BOUT
+
13 ~ 20
-
+
BW = 16MHz
30, 32
34, 36
29
27
V
V
REF
SET
AGND DGND
AV
DV
CC
CC
26
3K
+
-
25
22
33µF
CLK
(TTL LEVEL)
21
CLK
HI20206
†R is matching resistance for LPF.
FIGURE 7. APPLIED CIRCUIT EXAMPLE
10-9
HI20206
Timing Diagram
t
t
t
t
t
t
4
1
12
2
3
34
t
t
PW0
PW1
CLK
V
V
= 1.5V
= 1.4V
TH
TH
t
t
Y
X
DATA
t
t
H
H
t
t
S
S
100%
V
: THRESHOLD LEVEL
TH
0%
90%
10%
D/A OUT
10%
0%
90%
100%
t
t
f
r
NOTE: At the time t = t , the data of individual bits are switched and
NOTE: At the time t = t , the data of individual bits are switched and
Y
X
thereafter, when the CLK becomes L → H at t = t , the D/A OUT is
thereafter when the CLK becomes L → H at t = t , the D/A OUT is
2
4
varied synchronous with it. That is, the D/A OUT is synchronous with
varied synchronous with it. That is, the D/A OUT is synchronous with
the rise of the CLK. [In this case, fetching of the data is carried out at
the rise of the CLK. [In this case, fetching of the data is carried out at
the fall of the CLK (at the time when t = t )].
12
the fall of the CLK (at the time when t = t )].
4
FIGURE 8. TIMING CHART
Notes On Use
(1) Setting of pin 26 (V
SET
)
See R vs I
of Figure 14. The calculation
REF
expression is as follows:
R = V /I
The full scale of the D/A output voltage changes by apply-
ing voltage to pin 26 (V ). When load is connected to
.
REF REF
SET
pin 27 (V
), DC voltage of 1.2V is issued and the said
2. Adjust the volume so that the RGB output voltage
full scale becomes 1V.
REF
voltage is dropped to 0.8V by resistance division.
(At this point, it becomes R1: R2 = 1:2).
When the 0.8V is applied to pin 26 (V ), the D/A
SET
output of 1V
can be obtained.
P-P
5.0
(Example of use):
V
V
REF
27
26
25
R1
SET
1.0
R
R2
0.3
0.1
AGND
FIGURE 9.
0.1
0.2
1
5
(Adjustment Method)
PIN CURRENT I
(mA)
REF
1. The resistance R is determined in accordance with
the recommended operating condition of I
(current flowing through resistance R).
,
FIGURE 10. RESISTANCE vs V
PIN CURRENT
REF
REF
10-10
HI20206
(2) Phase Relationship Between Data and Clock
• When mounting onto the printed board, allow as
much space as possible to the ground surface and
In order to obtain the desired characteristics as a D/A
converter, it is necessary to set the phase relationship
correctly between the externally applied data and
clock.
the V
surface on the board and reduce the para-
CC
sitic inductance and resistance.
• It is desirable that the AGND and DGND be sepa-
rated in the pattern on the board. It is similar with
Satisfy the standard of the set-up time (t ) and hold
S
AV
and DV . As shown in the diagram below, for
CC
CC
time (t ) indicated in the electrical characteristics. As to
H
example, it is recommended that the wiring to the
the meaning of t and t , see the timing chart.
S
H
electric supply of AGND and DGND as also AV
CC
be conducted separately, and then mak-
and DV
Moreover, the clock pulse width is desired to be as
indicated in the recommended operating condition.
CC
ing AGND and DGND as also AV
and DV in
CC
CC
common right near the power supply respectively.
• Insert in parallel a 47µF tantalum capacitor and a
(3) Regarding the Load of D/A Output Pin
Receive the D/A output of the next stage with high
impedance. In other words perform so that it becomes
as follows:
100pF ceramic capacitor between the V surface
CC
on the printed board and the nearmost ground sur-
face. (A of diagram below). It is also desirable to
insert the above between the V
CC
surface near the
R > 10kΩ
L
pin of the IC and the ground surface (see Figure 11).
They are bypass capacitors to prevent bad effects
from occurring to the characteristics when the power
supply voltage fluctuates due to the clock, etc.
C < 20pF.
L
The temperature characteristics indicated in the
characteristics diagram has been measured under this
condition.
It is recommended to reduce noise which overlaps
the D/A output by inserting a capacitor of over 0.1µF
between pin 25 (AGND) and pin 26 (V
However, when it is made R ≤ 10kΩ the temperature
characteristics may change considerably. In addition,
when it is made to C ≥ 20pF, the rise and fall of the
L
).
SET
L
D/A output become slow and will not operate at high
speed.
(4) Noise Reduction Measures
As the D/A output voltage is a minute voltage of
approximately 4mV per one step, ingenuity is required
in reducing the noise entering from the outside of the
IC as much as possible. Therefore, use the items given
below as reference.
HI20206
B
DGND
AV
CC
A
POWER SUPPLY
AGND
DV
CC
PRINTED BOARD
FIGURE 11.
10-11
HI20206
Typical Performance Curves
0
o
T
= 25 C
A
o
AV
= DV
= 5 C
CC
CC
> 10kΩ
2
1
R
L
DEVIATION
RANGE
-10
B
o
T
= 25 C
A
AV
= DV
CC
= 5V
CC
G
R
R
> 10kΩ
L
-20
0
1
2
0
1.0
AGND (V)
2.0
AGND (V)
FIGURE 12. OUTPUT VOLTAGE FULL SCALE vs V
- AGND
SET
FIGURE 13. OUTPUT ZERO OFFSET VOLTAGE vs V
- AGND
SET
0
V
IS CREATED
SET
BY RESISTANCE
1000
DIVISION OF V
REF
/3)
(V
= 2V
SET
REF
REF = -400µA
AV = DV
= 5V
CC
CC
R
> 10kΩ
L
V
IS CREATED
-5
SET
BY RESISTANCE
DIVISION OF V
REF
/3)
950
(V
= 2V
REF
SET
= -400µA
I
REF
AV
= DV
= 5.0V
CC
CC
R
> 10kΩ
L
-10
-20
0
20
40
60
80
-20
0
20
40
60
80
o
o
AMBIENT TEMPERATURE ( C)
AMBIENT TEMPERATURE ( C)
FIGURE 14. OUTPUT VOLTAGE FULL SCALE vs AMBIENT
TEMPERATURE
FIGURE 15. OUTPUT ZERO OFFSET vs AMBIENT
TEMPERATURE
0
o
o
= 25 C
T
V
R
= 25 C
A
T
A
- AGND = 0.8V
> 10kΩ
SET
V
R
- AGND = 0.8V
SET
1000
L
> 10kΩ
L
-5
950
10
4
5
6
4
5
6
POWER SUPPLY VOLTAGE (V)
POWER SUPPLY VOLTAGE (V)
FIGURE 16. OUTPUT VOLTAGE FULL SCALE vs POWER
SUPPLY VOLTAGE
FIGURE 17. OUTPUT ZERO OFFSET VOLTAGE vs POWER
SUPPLY VOLTAGE
10-12
HI20206
Typical Performance Curves (Continued)
1.20
1.15
1.20
1.15
o
I
= -400µA
T
= -25 C
REF
AV
A
= DV
= 5V
CC
I
= 400µA
CC
REF
-20
0
20
40
60
80
4
5
6
POWER SUPPLY VOLTAGE (V)
o
AMBIENT TEMPERATURE ( C)
FIGURE 18. INTERNAL REFERENCE VOLTAGE vs AMBIENT
TEMPERATURE
FIGURE 19. INTERNAL REFERENCE VOLTAGE vs POWER
SUPPLY VOLTAGE
0
-20
-40
o
T
= 25 C
A
-60
-80
OUTPUT VOLTAGE FULL SCALE 1V
P-P
f
= 2f
DATA
CLK
AV
R
L
= DV
= 5V
CC
> 10kΩ, C <20pF
CC
L
PINS 30, 32, 34 AND 36
ARE CONNECTED TO AV
CC
-100
10
20
DATA RATE (MHz)
FIGURE 20. CROSSTALK AMONG R, G, AND B vs DATA RATE
10-13
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