HI4P0548-5 [INTERSIL]
Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection; 单16和8 ，差分8通道和4通道CMOS模拟的MUX与Active过压保护
| 型号： | HI4P0548-5 |
| 厂家： | 
Intersil |
| 描述： | Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection |
| 文件： | 总15页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-546, HI-547, HI-548, HI-549
Data Sheet
June 1999
File Number 3150.2
Single 16 and 8, Differential 8-Channel
and 4-Channel CMOS Analog MUXs with
Active Overvoltage Protection
Features
• Analog Overvoltage Protection. . . . . . . . . . . . . . . . . . 70V
• No Channel Interaction During Overvoltage
P-P
The HI-546, HI-547, HI-548 and HI-549 are analog
multiplexers with active overvoltage protection and
• Guaranteed r
Matching
ON
guaranteed r
matching. Analog input levels may greatly
• Maximum Power Supply. . . . . . . . . . . . . . . . . . . . . . . 44V
• Break-Before-Make Switching
ON
exceed either power supply without damaging the device or
disturbing the signal path of other channels. Active
protection circuitry assures that signal fidelity is maintained
even under fault conditions that would destroy other
multiplexers.
• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 500ns
• Standby Power (Typical). . . . . . . . . . . . . . . . . . . . . 7.5mW
Analog inputs can withstand constant 70V
P-P
levels with
±15V supplies. Digital inputs will also sustain continuous
faults up to 4V greater than either supply. In addition, signal
sources are protected from short circuiting should
Applications
• Data Acquisition
• Industrial Controls
• Telemetry
multiplexer supply loss occur. Each input presents 1kΩ of
resistance under this condition. These features make the
HI-546, HI-547, HI-548 and HI-549 ideal for use in systems
where the analog inputs originate from external equipment
or separately powered circuitry. All devices are fabricated
with 44V Dielectrically Isolated CMOS technology. The
HI-546 is a single 16-Channel, the HI-547 is an 8-Channel
differential, the HI-548 is a single 8-Channel and the HI-549
is a 4-Channel differential device. If input overvoltage
protection is not needed the HI-506/507/508/509
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
HI1-0546-5
HI1-0546-2
HI3-0546-5
HI4P0546-5
HI9P0546-9
HI1-0547-5
HI3-0547-5
HI4P0547-5
HI9P0547-9
HI1-0548-2
HI1-0548-5
HI3-0548-5
HI4P0548-5
HI9P0548-5
HI9P0548-9
HI1-0549-2
HI3-0549-5
HI4P0549-5
HI9P0549-5
HI9P0549-9
0 to 75
28 Ld CERDIP
F28.6
-55 to 125 28 Ld CERDIP
F28.6
0 to 75
0 to 75
28 Ld PDIP
28 Ld PLCC
28 Ld SOIC
28 Ld CERDIP
28 Ld PDIP
28 Ld PLCC
28 Ld SOIC
E28.6
multiplexers are recommended. For further information see
Application Notes AN520 and AN521.
N28.45
M28.3
F28.6
-40 to 85
0 to 75
For MIL-STD-883 compliant parts, request the HI-546/883,
HI-547/883, HI-548/883 and HI-549/883 datasheets.
0 to 75
E28.6
0 to 75
N28.45
M28.3
F16.3
-40 to 85
-55 to 125 16 Ld CERDIP
0 to 75
0 to 75
0 to 75
0 to 75
-40 to 85
16 Ld CERDIP
16 Ld PDIP
20 Ld PLCC
16 Ld SOIC
16 Ld SOIC
F16.3
E16.3
N20.35
M16.15
M16.15
F16.3
-55 to 125 16 Ld CERDIP
0 to 75
0 to 75
16 Ld PDIP
20 Ld PLCC
16 Ld SOIC
16 Ld SOIC
E16.3
N20.35
M16.15
M16.15
0 to 75
-40 to 85
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HI-546, HI-547, HI-548, HI-549
Pinouts
HI-546 (CERDIP, PDIP, SOIC)
HI-547 (CERDIP, PDIP, SOIC)
TOP VIEW
TOP VIEW
+V
1
2
3
4
5
6
7
8
9
28 OUT A
27 -V
+V
1
2
3
4
5
6
7
8
9
28 OUT
27 -V
SUPPLY
OUT B
SUPPLY
NC
SUPPLY
SUPPLY
26 IN 8A
25 IN 7A
24 IN 6A
23 IN 5A
22 IN 4A
21 IN 3A
NC
IN 8B
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
21 IN 3
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
20
IN 2A
20
IN 2
IN 2B 10
IN 1B 11
GND 12
19 IN 1A
IN 10 10
IN 9 11
GND 12
19 IN 1
18 ENABLE
18 ENABLE
17 ADDRESS A
16 ADDRESS A
15 ADDRESS A
17 ADDRESS A
16 ADDRESS A
15 ADDRESS A
0
1
2
0
1
2
V
13
V
13
REF
REF
NC 14
ADDRESS A 14
3
HI-546 (PLCC)
HI-547 (PLCC)
TOP VIEW
TOP VIEW
4
3
2
1
28 27 26
4
3
2
1
28 27 26
5
6
25
24
23
22
21
20
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
5
25 IN 7
IN 7A
IN 6A
IN 5A
IN 4A
IN 3A
IN 2A
IN 15
6
7
24
23
22
21
20
19
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
7
8
8
9
9
10
11
10
11
19 IN 1A
12 13 14 15 16 17 18
12 13 14 15 16 17 18
HI-548 (CERDIP, PDIP, SOIC)
HI-549 (CERDIP, PDIP, SOIC)
TOP VIEW
TOP VIEW
A
1
2
3
4
5
6
7
8
16 A
15 A
A
1
2
3
4
5
6
7
8
16 A
1
0
1
2
0
ENABLE
ENABLE
15 GND
14 +V
SUPPLY
-V
14 GND
13 +V
-V
SUPPLY
IN 1
SUPPLY
IN 1A
13 IN 1B
12 IN 2B
11 IN 3B
10 IN 4B
SUPPLY
IN 2
IN 3
IN 4
OUT
12 IN 5
11 IN 6
10 IN 7
IN 2A
IN 3A
IN 4A
9
IN 8
9 OUT B
OUT A
2
HI-546, HI-547, HI-548, HI-549
Pinouts (Continued)
HI-548 (PLCC)
TOP VIEW
HI-549 (PLCC)
TOP VIEW
3
2
1
20 19
3
2
1
20 19
-V
+V
SUPPLY
4
5
6
7
8
18
17
16
15
SUPPLY
IN 1A
4
5
6
7
8
18
17
16
15
14
-V
SUPPLY
IN 1
GND
+V
IN 1B
NC
SUPPLY
NC
IN 2A
IN 3A
NC
IN 2
IN 3
NC
IN 2B
IN 5
IN 6
14 IN 3B
9
10 11 12 13
9
10 11 12 13
TRUTH TABLE HI-547 (Continued)
TRUTH TABLE HI-546
A
A
A
0
EN
H
“ON” CHANNEL PAIR
A
A
A
A
0
EN
L
“ON” CHANNEL
2
1
3
2
1
H
L
H
6
7
8
X
X
X
X
None
1
H
H
H
H
L
H
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
L
L
H
H
L
3
TRUTH TABLE HI-548
L
L
H
L
4
A
A
A
0
EN
L
“ON” CHANNEL
2
1
L
H
H
H
H
L
5
X
L
X
L
X
None
L
L
H
L
6
L
H
L
H
H
H
H
H
H
H
H
1
2
3
4
5
6
7
8
L
H
H
L
7
L
L
L
H
L
8
L
H
H
L
H
H
H
H
H
H
H
H
9
L
H
L
L
L
H
L
10
11
12
13
14
15
16
H
H
H
H
L
H
H
L
L
H
L
L
H
L
H
H
H
H
H
H
H
L
H
L
H
H
TRUTH TABLE HI-549
H
A
A
EN
L
“ON” CHANNEL PAIR
1
0
X
X
None
TRUTH TABLE HI-547
L
L
L
H
L
H
1
2
3
4
A
A
A
0
EN
L
“ON” CHANNEL PAIR
2
1
H
X
X
X
None
H
H
H
L
L
L
L
H
L
L
L
H
L
H
H
H
H
H
1
2
3
4
5
H
H
H
H
L
H
L
3
HI-546, HI-547, HI-548, HI-549
Functional Diagrams
HI-546
HI-547
OUT
A
OUT
1K
1K
1K
IN 1
IN 2
IN 1A
1K
1K
OUT
B
IN 8A
IN 1B
DECODER/
DRIVER
1K
1K
DECODER/
DRIVER
IN 8B
IN 16
OVERVOLTAGE
CLAMP AND
SIGNAL
OVERVOLTAGE
CLAMP AND
SIGNAL
5V
REF
LEVEL
SHIFT
5V
REF
LEVEL
SHIFT
ISOLATION
ISOLATION
† DIGITAL INPUT
†
†
†
†
† DIGITAL INPUT
† † † †
†
PROTECTION
PROTECTION
V
A
A
A
2
EN
V
A
A
A
A EN
3
REF
0
1
REF
0
1
2
HI-548
HI-549
OUT
A
OUT
1K
1K
1K
IN 1A
IN 1
IN 2
1K
1K
OUT
B
IN 4A
IN 1B
DECODER/
DRIVER
1K
1K
DECODER/
DRIVER
IN 4B
IN 8
OVERVOLTAGE
CLAMP AND
SIGNAL
OVERVOLTAGE
CLAMP AND
SIGNAL
5V
REF
LEVEL
SHIFT
5V
REF
LEVEL
SHIFT
ISOLATION
ISOLATION
† DIGITAL INPUT
†
†
†
† DIGITAL INPUT
†
†
†
†
PROTECTION
PROTECTION
A
A
EN
A
A
A
2
EN
0
1
0
1
4
HI-546, HI-547, HI-548, HI-549
Schematic Diagrams
ADDRESS DECODER
V+
P
P
P
P
P
P
P
N
TO P-CHANNEL
DEVICE OF
THE SWITCH
N
N
A
OR A
0
0
N
N
N
N
A
OR A
1
1
TO N-CHANNEL
DEVICE OF
THE SWITCH
A
OR A
2
2
A
OR A
3
3
ENABLE
DELETE A OR A INPUT FOR HI-547, HI-548, HI-549
3
3
DELETE A OR A INPUT FOR HI-549
2
2
V-
MULTIPLEX SWITCH
FROM
DECODE
OVERVOLTAGE PROTECTION
N
V+
P
Q5
D6
D7
D4
D5
R11
1K
N
OUT
IN
N
Q6
V-
P
FROM
DECODE
5
HI-546, HI-547, HI-548, HI-549
Schematic Diagrams (Continued)
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
TTL REFERENCE
CIRCUIT
V+
R10
R9
Q1
V
REF
Q4
D3
GND
LEVEL SHIFTER
V+
P
N
P
P
P
P
P
P
P
P
OVERVOLTAGE
P
R2
R3
PROTECTION
LEVEL
R5
R7
R8
SHIFTED
ADDRESS
TO
V+
D2
R4
DECODE
R6
N
N
N
N
N
N
N
N
R1
200
Ω
D1
N
V-
V-
GND
ADD
IN
6
HI-546, HI-547, HI-548, HI-549
Absolute Maximum Ratings
Thermal Information
o
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
16 Ld CERDIP Package. . . . . . . . . . .
28 Ld CERDIP Package. . . . . . . . . . .
28 Ld PDIP Package . . . . . . . . . . . . .
16 Ld PDIP Package . . . . . . . . . . . . .
28 Ld PLCC Package. . . . . . . . . . . . .
20 Ld PLCC Package. . . . . . . . . . . . .
28 Ld SOIC Package . . . . . . . . . . . . .
16 Ld SOIC Package . . . . . . . . . . . . .
Maximum Junction Temperature
85
55
60
90
70
80
75
105
32
18
Digital Input Voltage (V , V ) . . . . . . . . . . . . . (V-) -4V to (V+) +4V
EN
A
N/A
N/A
N/A
N/A
N/A
N/A
Analog Signal (V , V
). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V
IN OUT
or 20mA, Whichever Occurs First
Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, IN or OUT (Pulsed 1ms, 10% Duty Cycle Max) . . 40mA
Operating Conditions
o
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 C
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
Temperature Ranges
HI-546/548/549-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HI-546/547/548/549-5 . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
HI-546/547/548/549-9 . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
o
o
o
o
o
o
o
o
(PLCC, SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications Supplies = +15V, -15V; V
Pin = Open; V (Logic Level High) = 4V; V (Logic Level Low) = 0.8V; Unless
AH AL
Otherwise Specified. For Test Conditions, Consult Test Circuits Section
REF
-2
-5, -9
TYP
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
MIN
MAX
UNITS
SWITCHING CHARACTERISTICS
Access Time, t
25
Full
25
-
-
0.5
-
-
-
-
0.5
-
-
µs
µs
ns
ns
ns
ns
ns
µs
µs
dB
pF
A
1.0
1.0
Break-Before Make Delay, t
25
-
80
300
-
-
25
-
80
300
-
-
OPEN
Enable Delay (ON), t
25
500
-
ON(EN)
Full
25
-
1000
-
1000
Enable Delay (OFF), t
Settling Time
-
300
-
500
-
300
-
-
OFF(EN)
Full
25
-
1000
-
1000
To 0.1%
-
1.2
3.5
68
10
-
-
-
-
-
1.2
3.5
68
10
-
-
-
-
To 0.01%
Note 6
25
-
-
Off Isolation
25
50
-
50
-
Channel Input Capacitance, C
S(OFF)
25
Channel Output Capacitance C
HI-546
D(OFF)
25
25
25
25
25
-
-
-
-
-
52
30
25
12
0.1
-
-
-
-
-
-
-
-
-
-
52
30
25
12
0.1
-
-
-
-
-
pF
pF
pF
pF
pF
HI-547
HI-548
HI-549
Input to Output Capacitance, C
DS(OFF)
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, TTL Drive, V
Full
Full
25
-
4.0
-
-
-
-
-
-
0.8
-
-
4.0
-
-
-
-
-
-
0.8
-
V
V
AL
Input High Threshold, V (Note 8)
AH
MOS Drive, V (HI-546/547 Only)
V
V
= 10V
= 10V
0.8
-
0.8
-
V
AL
REF
REF
MOS Drive, V (HI-546/547 Only)
AH
25
6.0
-
6.0
-
V
Input Leakage Current (High or Low), I
Note 5
Full
1.0
1.0
µA
A
7
HI-546, HI-547, HI-548, HI-549
Electrical Specifications Supplies = +15V, -15V; V
Pin = Open; V (Logic Level High) = 4V; V (Logic Level Low) = 0.8V; Unless
AH AL
REF
Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued)
-2
-5, -9
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, V
Full
25
-15
-
-
+15
1.5
1.8
7.0
-
-15
-
-
+15
1.8
2.0
7.0
-
V
IN
On Resistance, r
Note 2
1.2
1.5
kΩ
kΩ
%
ON
Full
25
-
1.5
-
1.8
∆r , (Any Two Channels)
-
-
-
-
ON
Off Input Leakage Current, I
Note 3
Note 3
25
-
0.03
-
0.03
nA
nA
nA
nA
nA
nA
nA
nA
µA
nA
nA
nA
nA
nA
nA
S(OFF)
Full
25
-
-
50
-
-
50
-
Off Output Leakage Current, I
-
0.1
-
-
0.1
D(OFF)
HI-546
HI-547
HI-548
HI-549
Full
Full
Full
Full
25
-
-
300
200
200
100
-
-
-
300
200
200
100
-
-
-
-
-
-
-
-
-
-
-
-
-
I
With Input Overvoltage Applied
Note 4
Note 3
-
4.0
-
4.0
D(OFF)
Full
25
-
-
2.0
-
-
-
-
On Channel Leakage Current, I
-
0.1
-
0.1
-
D(ON)
HI-546
HI-547
HI-548
HI-549
Full
Full
Full
Full
Full
-
-
-
-
-
-
300
200
200
100
50
-
-
-
-
-
-
300
200
200
100
50
-
-
-
-
-
-
Differential Off Output Leakage Current
(HI-547, HI-549 Only)
-
-
I
DIFF
POWER SUPPLY CHARACTERISTICS
Power Dissipation, P
Current, I+
Full
Full
Full
-
-
-
7.5
0.5
-
-
-
-
7.5
0.5
-
mW
mA
mA
D
Note 7
Note 7
2.0
1.0
2.0
1.0
Current, I-
0.02
0.02
NOTES:
±
2. V
OUT
= ±10V, I
=
100µA.
OUT
3. 10nA is the practical lower limit for high speed measurement in the production test environments.
4. Analog Overvoltage = ±33V.
o
5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25 C.
6. V = 0.8V, R = 1K, C = 15pF, V = 7V , f = 100kHz.
EN
L
L
S
RMS
7. V , V = 0V or 4V.
EN
A
8. To drive from DTL/TTLCircuits, 1kΩ pull-up resistors to +5V supply are recommended.
8
HI-546, HI-547, HI-548, HI-549
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 4V, V = 0.8V, V
= Open, Unless Otherwise Specified
REF
A
SUPPLY
AH AL
100µA
V
2
IN
OUT
r
V
2
V
=
IN
ON
100µA
FIGURE 1A. ON RESISTANCE TEST CIRCUIT
1.4
o
1.3
1.2
1.1
125 C
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
o
25 C
1.0
0.9
o
-55 C
0.8
0.7
0.6
-10
-8
-6
-4
-2
0
2
4
6
8
10
5
6
7
8
9
10
11
12
13
14
15
ANALOG INPUT (V)
SUPPLY VOLTAGE (±V)
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE
FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY
VOLTAGE
FIGURE 1. ON RESISTANCE
100nA
10nA
1nA
OFF OUTPUT
CURRENT
+0.8V
EN
I
ON LEAKAGE
CURRENT
D(OFF)
OUT
I
D(ON)
I
D(OFF)
A
±
±10V
10V
OFF INPUT
100pA
LEAKAGE CURRENT
I
S(OFF)
10pA
25
50
75
100
125
o
TEMPERATURE ( C)
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE
FIGURE 2B. I
TEST CIRCUIT (NOTE 9)
D(OFF)
9
HI-546, HI-547, HI-548, HI-549
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 4V, V = 0.8V, V
AH AL REF
= Open, Unless Otherwise Specified (Continued)
A
SUPPLY
OUT
OUT
I
A
S(OFF)
+0.8V
A
I
D(ON)
EN
EN
±
±10V
10V
±
±10V
10V
4V
FIGURE 2C. I
S(OFF)
TEST CIRCUIT (NOTE 9)
FIGURE 2D. I
D(ON)
TEST CIRCUIT (NOTE 9)
NOTE:
±
±
9. Two measurements per channel: ±10V and 10V. (Two measurements per device for I
: ±10V and 10V.)
D(OFF)
FIGURE 2. LEAKAGE CURRENTS
18
ANALOG INPUT
CURRENT (I
)
15
12
9
5
4
3
2
1
0
IN
I
I
D(OFF)
A
A
IN
6
±V
IN
OUTPUT OFF LEAKAGE
3
CURRENT ID
(OFF)
0
15
18
21
24
27
30
33
36
ANALOG INPUT OVERVOLTAGE (±V)
FIGURE 3A. ANALOG INPUT CURRENT AND OUTPUT OFF
LEAKAGE CURRENT vs ANALOG INPUT
OVER-VOLTAGE
FIGURE 3B. TEST CIRCUIT
FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS
±14
±12
±10
±8
o
-55 C
o
25 C
o
125 C
±6
A
±V
IN
±4
±2
0
0
2
4
6
8
10
12
14
VOLTAGE ACROSS SWITCH (±V)
FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE
FIGURE 4. ON CHANNEL CURRENT
FIGURE 4B. TEST CIRCUIT
10
HI-546, HI-547, HI-548, HI-549
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 4V, V = 0.8V, V
= Open, Unless Otherwise Specified (Continued)
A
SUPPLY AH AL REF
8
6
4
2
0
+15V/+10V
+I
SUPPLY
A
V+
±10V/±5V
A
A
A
A
IN 1
3
2
1
0
HI-546†
IN 2
THRU
IN 15
V
= ± 15V
SUPPLY
V
50Ω
A
V
= ± 10V
SUPPLY
±
±
IN 16
10V/ 5V
EN
OUT
V-
+4V
GND
10MΩ
SUPPLY
-15V/-10V
14pF
-I
A
1K
10K
100K
1M
10M
TOGGLE FREQUENCY (Hz)
†Similar connection for HI-547/HI-548/HI-549.
FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY
FIGURE 5. DYNAMIC SUPPLY CURRENT
FIGURE 5B. TEST CIRCUIT
+15V
900
800
700
600
500
400
300
V
V
= OPEN FOR LOGIC HIGH LEVEL < 6V
= LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V
REF
REF
V
V+
IN 1
REF
±10V
A
A
A
A
3
2
1
0
IN 2 THRU
IN 15
V
50Ω
A
HI-546†
±
10V
IN 16
EN
OUT
+4V
V-
GND
10kΩ
50pF
-15V
3
4
5
6
7
8
9
10 11 12 13 14
15
LOGIC LEVEL (HIGH) (V)
†Similar connection for HI-547/HI-548/HI-549.
FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH)
FIGURE 6B. TEST CIRCUIT
V
INPUT
A
V
= 4.0V
2V/DIV.
AH
ADDRESS
DRIVE (V )
A
50%
0V
S
ON
1
+10V
OUTPUT
-10V
OUTPUT
5V/DIV.
10%
S
ON
16
t
A
200ns/DIV.
FIGURE 6C. MEASUREMENT POINTS
FIGURE 6D. WAVEFORMS
FIGURE 6. ACCESS TIME
11
HI-546, HI-547, HI-548, HI-549
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 4V, V = 0.8V, V = Open, Unless Otherwise Specified (Continued)
AH AL REF
A
SUPPLY
A
A
3
2
HI-546†
+5V
V
= 4V
AH
IN 1
IN 2 THRU
IN 15
ADDRESS
DRIVE (V )
V
50Ω
A
A
A
1
0
A
0V
IN 16
V
OUT
OUTPUT
+4V
EN
OUT
GND
50pF
1kΩ
50%
50%
t
OPEN
†Similar connection for HI-547/HI-548/HI-549
FIGURE 7A. TEST CIRCUIT
FIGURE 7B. MEASUREMENT POINTS
V
INPUT
A
2V/DIV.
S
ON
S
ON
16
1
OUTPUT
0.5V/DIV.
100ns/DIV.
FIGURE 7C. WAVEFORMS
FIGURE 7. BREAK-BEFORE-MAKE DELAY
A
A
3
2
HI-546†
+10V
IN 1
V
= 4V
AH
ENABLE DRIVE
(V )
A
50%
50%
IN 2 THRU
IN16
A
A
1
0
0V
V
OUT
90%
EN
OUT
OUTPUT
10%
GND
V
50pF
50Ω
1kΩ
A
0V
t
ON(EN)
t
OFF(EN)
†Similar connection for HI-547/HI-548/HI-549
FIGURE 8A. TEST CIRCUIT
FIGURE 8B. MEASUREMENT POINTS
12
HI-546, HI-547, HI-548, HI-549
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 4V, V = 0.8V, V
= Open, Unless Otherwise Specified (Continued)
A
SUPPLY
AH
AL
REF
ENABLE
DRIVE
2V/DIV.
DISABLED
OUTPUT
2V/DIV.
ENABLED (S ON)
1
100ns/DIV.
FIGURE 8C. WAVEFORMS
FIGURE 8. ENABLE DELAYS
13
HI-546, HI-547, HI-548, HI-549
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
83.9 mils x 159 mils
Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±1kÅ
Silox Thickness: 12kÅ ±2kÅ
METALLIZATION:
Type: CuAl
Thickness: 16kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
5
2
1.4 x 10 A/cm
SUBSTRATE POTENTIAL (NOTE):
TRANSISTOR COUNT:
-V
SUPPLY
485
PROCESS:
CMOS-DI
NOTE: The substrate appears resistive to the -V
SUPPLY
terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a
conductor at -V
potential.
SUPPLY
Metallization Mask Layouts
HI-546
HI-547
NC
V
(14)
A
A
V
A
A
(17)
A
A
(17)
A
1
EN
(18)
GND
(12)
EN
(18)
GND
(12)
2
3
REF
2
REF
(13)
0
1
0
(16) (15)
(14) (13)
(16) (15)
IN 1
(19)
IN 9
(11)
IN 1B
(11)
IN 1A
(19)
IN 2B
(10)
IN 2A
(20)
IN 2
(20)
IN 10
(10)
IN 3
(21)
IN 11
(9)
IN 3A
(21)
IN 3B
(9)
IN 4A
(22)
IN 4B
(8)
IN 4
(22)
IN 12
(8)
IN 5
(23)
IN 13
(7)
IN 5A
(23)
IN 5B
(7)
IN 6
(24)
IN 14
(6)
IN 6A
(24)
IN 6B
(6)
IN 7
(25)
IN 15
(5)
IN 7A
(25)
IN 7B
(5)
IN 8
(26)
IN 16
(4)
IN 8A
(26)
IN 8B
(4)
V- (27)
OUT (28)
+V (1)
NC (2)
V- (27)
OUT A (28)
+V (1)
OUT B(2)
14
HI-546, HI-547, HI-548, HI-549
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
83 mils x 108 mils
Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±1kÅ
Silox Thickness: 12kÅ ±2kÅ
METALLIZATION:
Type: CuAl
Thickness: 16kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
5
1.4 x 10 A/cm
SUBSTRATE POTENTIAL (NOTE):
TRANSISTOR COUNT:
-V
SUPPLY
253
PROCESS:
CMOS-DI
NOTE: The substrate appears resistive to the -V
terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a
SUPPLY
conductor at -V
potential.
SUPPLY
Metallization Mask Layouts
HI-548
HI-549
IN 6 IN 7 IN 8
(11) (10) (9)
OUT
(8)
IN 4 IN 3
IN 3B IN 4B OUT B
OUT A IN 4A IN 3A
(8) (7) (6)
(7)
(6)
(11) (10)
(9)
IN 5
(12)
IN 2
(5)
IN 2B
(12)
IN 2A
(5)
+V
(13)
IN 1
(4)
IN 1B
(13)
IN 1A
(4)
GND
(14)
-V
(3)
+V
(14)
-V
(3)
A
2
(15)
A
A
GND
(15)
A
A
0
EN
(2)
EN
(2)
1
0
1
(16) (1)
(16) (1)
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
15
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