HI5660EVAL1 [INTERSIL]
8-Bit, 165/125/60MSPS, High Speed D/A Converter; 8位165 /125 / 60MSPS ，高速D / A转换器
| 型号： | HI5660EVAL1 |
| 厂家： | 
Intersil |
| 描述： | 8-Bit, 165/125/60MSPS, High Speed D/A Converter |
| 文件： | 总11页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5660
Data Sheet
November 1999
File Number 4521.4
8-Bit, 165/125/60MSPS, High Speed D/A
Converter
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .125MSPS
• Low Power . . . . . . . . . . . . . . . 165mW at 5V, 27mW at 3V
• Power Down Mode . . . . . . . . . . 23mW at 5V, 10mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . ±0.25 LSB
• Adjustable Full Scale Output Current. . . . . 2mA to 20mA
• SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . .60dBc
• Internal 1.2V Bandgap Voltage Reference
The HI5660 is an 8-bit, 125MSPS, high speed, low power,
D/A converter which is implemented in an advanced CMOS
process. Operating from a single +3V to +5V supply, the
converter provides 20mA of full scale output current and
includes edge-triggered CMOS input data latches. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented current source architecture. For
an equivalent performance dual version, see the HI5628.
This device complements the CommLink™ HI5X60 family of
high speed converters offered by Intersil, which includes 8,
10, 12, and 14-bit devices.
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
Ordering Information
Applications
TEMP.
PART
NUMBER
RANGE
( C)
PKG.
NO.
CLOCK
SPEED
• Medical Instrumentation
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
o
PACKAGE
HI5660/16IB †
HI5660/16IA †
HI5660IB
-40 to 85 28 Ld SOIC
M28.3
165MHz
-40 to 85 28 Ld TSSOP M28.173 165MHz
-40 to 85 28 Ld SOIC M28.3 125MHz
-40 to 85 28 Ld TSSOP M28.173 125MHz
-40 to 85 28 Ld SOIC M28.3 60MHz
-40 to 85 28 Ld TSSOP M28.173 60MHz
25 Evaluation Platform 125MHz
• Test Instrumentation
HI5660IA †
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
HI5660/6IB †
HI5660/6IA
Pinout
HI5660EVAL1 †
HI5660 (SOIC, TSSOP)
TOP VIEW
† Contact factory for availability.
D7 (MSB)
D6
1
2
3
4
5
6
7
8
9
CLK
28
27 DV
DD
26 DCOM
25 NC
D5
D4
D3
24 AV
DD
D2
23 NC
D1
22 IOUTA
21 IOUTB
D0 (LSB)
DCOM
20
ACOM
DCOM 10
DCOM 11
DCOM 12
DCOM 13
DCOM 14
19 COMP1
18 FSADJ
17 REFIO
16 REFLO
15 SLEEP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CommLink™ is a trademark of Intersil Corporation.
1
HI5660
Typical Applications Circuit
HI5660
(15) SLEEP
(16) REFLO
DCOM
ACOM
(9-14, 25)
DCOM
(17) REFIO
0.1µF
D7 (MSB) (1)
D6 (2)
D7
D6
D5
D4
D3
D2
D1
(18) FSADJ
(22) IOUTA
D5 (3)
R
SET
1.91kΩ
D4 (4)
D3 (5)
D/A OUT
50Ω
50Ω
D2 (6)
D1 (7)
D0 (LSB) (8)
D0
(21) IOUTB
D/A OUT
CLK (28)
(23) NC
50Ω
(19) COMP1
DCOM (26)
0.1µF
(20) ACOM
FERRITE
BEAD
FERRITE
BEAD
+5V OR +3V (V
)
DD
(24) AV
DD
DV
DD
(27)
+
+
10µH
10µH
10µF
0.1µF
10µF
0.1µF
Functional Block Diagram
IOUTA IOUTB
(LSB) D0
D1
CASCODE
CURRENT
SOURCE
34
34
D2
SWITCH
MATRIX
D3
3 LSBs
+
LATCH
LATCH
31 MSB
D4
D5
UPPER
5-BIT
31
SEGMENTS
DECODER
D6
(MSB) D7
COMP1
CLK
INT/EXT
VOLTAGE
REFERENCE
BIAS
GENERATION
INT/EXT
REFERENCE
SELECT
FSADJ
SLEEP
AV
ACOM DV
DD
DCOM
REFLO
REFIO
DD
2
HI5660
Absolute Maximum Ratings
Thermal Information
o
Digital Supply Voltage DV
DD
to DCOM . . . . . . . . . . . . . . . . . . +5.5V
to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
Analog Supply Voltage AV
DD
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
117
Grounds, ACOM TO DCOM. . -0.3V To +0.3V Digital Input Voltages
(D9-D0, CLK, SLEEP) . . . . . . . . . . . . . . . . . . . . . . . . . DV + 0.3V
o
DD
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . ±50µA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV + 0.3V
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
o
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Analog Output Current (I
OUT
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications AV = DV = +5V, V
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values
A
DD
DD
REF
o
o
T
= -40 C TO 85 C
A
PARAMETER
SYSTEM PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNITS
8
-0.5
-0.5
-0.025
-
-
-
Bits
LSB
LSB
Integral Linearity Error, INL
Differential Linearity Error, DNL
“Best Fit” Straight Line (Note 7)
±0.25
±0.25
+0.5
+0.5
(Note 7)
(Note 7)
(Note 7)
Offset Error, I
+0.025 % FSR
OS
Offset Drift Coefficient
0.1
-
ppm
o
FSR/ C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
With External Reference (Note 7)
-10
-10
-
±2
±1
+10
+10
-
% FSR
% FSR
ppm
Full Scale Gain Drift
±50
o
FSR/ C
With Internal Reference (Note 7)
(Note 3)
-
±100
-
ppm
FSR/ C
o
Full Scale Output Current, I
2
-
-
20
mA
V
FS
Output Voltage Compliance Range
-0.3
1.25
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
Output Settling Time, (t
(Notes 3, 9)
125
-
-
-
-
-
-
-
MHz
ns
CLK
)
0.8% (±1 LSB, equivalent to 7 Bits) (Note 7)
0.4% (±1/2 LSB, equivalent to 8 Bits) (Note 7)
-
-
-
-
-
5
SETT
15
5
ns
Singlet Glitch Area (Peak Glitch)
Output Rise Time
R
= 25Ω (Note 7)
pV•s
ns
L
Full Scale Step
Full Scale Step
1.5
1.5
10
50
30
Output Fall Time
ns
Output Capacitance
Output Noise
pF
IOUTFS = 20mA
IOUTFS = 2mA
-
-
-
-
pA/√Hz
pA/√Hz
AC CHARACTERISTICS HI5660/16IB, HI5660/16IA - 165MHz
Spurious Free Dynamic Range,
SFDR Within a Window
f
= 165MSPS, f
= 165MSPS, f
= 125MSPS, f
= 100MSPS, f
= 66.7MHz, 50MHz Span (Notes 4, 7, 9)
= 20.2MHz, 30MHz Span (Notes 4, 7, 9)
= 32.9MHz, 10MHz Span (Notes 4, 7)
= 5.04MHz, 4MHz Span (Notes 4, 7)
-
-
-
-
60
69
70
73
-
-
-
-
dBc
dBc
dBc
dBc
CLK
OUT
OUT
OUT
OUT
f
CLK
f
CLK
f
CLK
3
HI5660
o
Electrical Specifications AV = DV = +5V, V
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values (Continued)
A
DD
DD
REF
o
o
T
= -40 C TO 85 C
A
PARAMETER
TEST CONDITIONS
MIN
TYP
64
67
46
54
51
61
48
56
68
MAX
UNITS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Total Harmonic Distortion (THD) to
Nyquist
f
f
f
f
f
f
f
f
f
= 165MSPS, f
= 100MSPS, f
= 8.2MHz (Notes 4, 7)
= 2.00MHz (Notes 4, 7)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
OUT
OUT
Spurious Free Dynamic Range,
SFDR to Nyquist
= 165MSPS, f
= 165MSPS, f
= 125MSPS, f
= 125MSPS, f
= 100MSPS, f
= 100MSPS, f
= 100MSPS, f
= 66.7MHz, 82.5MHz Span (Notes 4, 7, 9)
= 20.2MHz, 82.5MHz Span (Notes 4, 7, 9)
= 32.9MHz, 62.5MHz Span (Notes 4, 7)
= 10.1MHz, 62.5MHz Span (Notes 4, 7)
= 40.4MHz, 50MHz Span (Notes 4, 7)
= 20.2MHz, 50MHz Span (Notes 4, 7)
= 5.04MHz, 50MHz Span (Notes 4, 7)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
AC CHARACTERISTICS HI5660IB, HI5660IA - 125MHz
Spurious Free Dynamic Range,
SFDR Within a Window
f
= 125MSPS, f
= 100MSPS, f
= 32.9MHz, 10MHz Span (Notes 4, 7)
= 5.04MHz, 4MHz Span (Notes 4, 7)
-
-
-
70
73
67
-
-
-
dBc
dBc
dBc
CLK
OUT
f
CLK
OUT
Total Harmonic Distortion (THD) to
Nyquist
f
= 100MSPS, f
= 2.00MHz (Notes 4, 7)
OUT
CLK
Spurious Free Dynamic Range,
SFDR to Nyquist
f
= 125MSPS, f
= 125MSPS, f
= 100MSPS, f
= 100MSPS, f
= 100MSPS, f
= 100MSPS, f
= 32.9MHz, 62.5MHz Span (Notes 4, 7)
= 10.1MHz, 62.5MHz Span (Notes 4, 7)
= 40.4MHz, 50MHz Span (Notes 4, 7)
= 20.2MHz, 50MHz Span (Notes 4, 7)
= 5.04MHz, 50MHz Span (Notes 4, 7)
= 2.51MHz, 50MHz Span (Notes 4, 7)
-
-
-
-
-
-
51
61
48
56
68
68
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
CLK
OUT
OUT
OUT
OUT
OUT
OUT
f
CLK
f
CLK
f
CLK
f
CLK
f
CLK
AC CHARACTERISTICS HI5660/6IB, HI5660/6IA - 60MHz
Spurious Free Dynamic Range,
SFDR Within a Window
f
= 60MSPS, f
= 50MSPS, f
= 50MSPS, f
= 10.1MHz, 10MHz Span (Notes 4, 7)
= 5.02MHz, 2MHz Span (Notes 4, 7)
= 1.00MHz, 2MHz Span (Notes 4, 7)
-
-
-
-
-
-
-
-
-
-
-
-
62
73
74
67
68
54
60
53
67
68
68
71
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
CLK
OUT
OUT
OUT
f
CLK
f
CLK
Total Harmonic Distortion (THD) to
Nyquist
f
f
= 50MSPS, f
= 50MSPS, f
= 2.00MHz (Notes 4, 7)
= 1.00MHz (Notes 4, 7)
CLK
CLK
OUT
OUT
Spurious Free Dynamic Range,
SFDR to Nyquist
f
= 60MSPS, f
= 60MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 50MSPS, f
= 25MSPS, f
= 20.2MHz, 30MHz Span (Notes 4, 7)
= 10.1MHz, 30MHz Span (Notes 4, 7)
= 20.2MHz, 25MHz Span (Notes 4, 7)
= 5.02MHz, 25MHz Span (Notes 4, 7)
= 2.51MHz, 25MHz Span (Notes 4, 7)
= 1.00MHz, 25MHz Span (Notes 4, 7)
= 5.02MHz, 25MHz Span (Notes 4, 7)
CLK
OUT
OUT
OUT
OUT
OUT
OUT
OUT
f
CLK
f
CLK
f
CLK
f
CLK
f
CLK
f
CLK
VOLTAGE REFERENCE
Internal Reference Voltage, V
FSADJ
Voltage at Pin 18 with Internal Reference
1.04
1.16
±60
0.1
1.28
V
o
Internal Reference Voltage Drift
-
-
-
-
ppm/ C
Internal Reference Output Current
Sink/Source Capability
µA
Reference Input Impedance
-
-
1
-
-
MΩ
Reference Input Multiplying Bandwidth (Note 7)
1.4
MHz
DIGITAL INPUTS D7-D0, CLK
Input Logic High Voltage with
5V Supply, V
(Note 3)
(Note 3)
3.5
2.1
5
3
-
-
V
V
IH
Input Logic High Voltage with
3V Supply, V
IH
4
HI5660
o
Electrical Specifications AV = DV = +5V, V
= Internal 1.2V, IOUTFS = 20mA, T = 25 C for All Typical Values (Continued)
A
DD
DD
REF
o
o
T
= -40 C TO 85 C
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Logic Low Voltage with
(Note 3)
(Note 3)
-
0
1.3
V
5V Supply, V
IL
Input Logic Low Voltage with
3V Supply, V
-
0
0.9
V
IL
Input Logic Current, I
-10
-10
-
-
-
+10
+10
-
µA
µA
pF
IH
IL
Input Logic Current, I
Digital Input Capacitance, C
IN
5
TIMING CHARACTERISTICS
Data Setup Time, t
See Figure 3 (Note 3)
See Figure 3 (Note 3)
See Figure 3
3
3
-
-
-
-
-
-
-
ns
ns
ns
ns
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
1
-
PD
CLK Pulse Width, t
, t
PW1 PW2
See Figure 3 (Note 3)
4
POWER SUPPLY CHARACTERISTICS
AV
DV
Power Supply
Power Supply
(Note 8, 9)
(Note 8, 9)
2.7
5.0
5.0
23
4
5.5
V
V
DD
2.7
5.5
DD
Analog Supply Current (I
)
5V or 3V, IOUTFS = 20mA
-
30
mA
AVDD
5V or 3V, IOUTFS = 2mA
-
-
mA
Digital Supply Current (I
DVDD
)
5V, IOUTFS = Don’t Care (Note 5)
3V, IOUTFS = Don’t Care (Note 5)
5V or 3V, IOUTFS = Don’t Care
5V, IOUTFS = 20mA (Note 6)
5V, IOUTFS = 20mA (Note 10)
5V, IOUTFS = 2mA (Note 6)
3.3V, IOUTFS = 20mA (Note 10)
3V, IOUTFS = 20mA (Note 6)
3V, IOUTFS = 20mA (Note 10)
3V, IOUTFS = 2mA (Note 6)
Single Supply (Note 7)
-
3
5
mA
-
1.5
1.6
165
150
70
75
85
67
27
-
-
mA
Supply Current (I
) Sleep Mode
-
3
mA
AVDD
Power Dissipation
-
-
mW
mW
mW
mW
mW
mW
mW
% FSR/V
-
-
-
-
-
-
-
-
-
-
-
-
Power Supply Rejection
NOTES:
-0.2
+0.2
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
ratio should be 32.
(typically 625µA). Ideally the
SET
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz.
7. See ‘Definition of Specifications’.
8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DV
and
DD
AV
DD
do not have to be equal.
9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS
and the power supply below 3.3V, but performance is degraded (valid for 165MHz version only).
10. Measured with the clock at 60MSPS and the output frequency at 10MHz.
5
HI5660
Timing Diagrams
50%
CLK
D7-D0
1
GLITCH AREA =
/ (H x W)
2
V
1
/
LSB ERROR BAND
2
HEIGHT (H)
I
OUT
t(ps)
WIDTH (W)
t
SETT
t
PD
FIGURE 1. OUTPUT SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
t
t
PW2
PW1
50%
CLK
t
t
t
SU
SU
SU
t
HLD
t
t
HLD
HLD
D7-D0
t
SETT
t
PD
I
OUT
t
t
SETT
SETT
t
t
PD
PD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
6
HI5660
Power Supply Rejection, is measured using a single power
supply. Its nominal +5V is varied ±10% and the change in the
DAC full scale output is noted.
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is 0.707
of its original value.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. In the case of the
HI5660, the measurement was done by switching from code
0 to 64, or quarter scale. Termination impedance was 25Ω
due to the parallel resistance of the output 50Ω and the
oscilloscope’s 50Ω input. This also aids the ability to resolve
the specified error band without overdriving the oscilloscope.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either T
or T .
MAX
MIN
The units are ppm per degree C.
Detailed Description
The HI5660 is an 8-bit, current out, CMOS, digital to analog
converter. Its maximum update rate is 165MSPS and can be
powered by either single or dual power supplies in the
recommended range of +3V to +5V. It consumes less than
165mW of power when using a +5V supply with the data
switching at 100MSPS. The architecture is based on a
segmented current source arrangement that reduces glitch
by reducing the amount of current switching at any one time.
The five MSBs are represented by 31 major current sources
of equivalent current. The three LSBs are comprised of
binary weighted current sources. Consider an input pattern
to the converter which ramps through all the codes from 0 to
255. The three LSB current sources would begin to count up.
When they reached the all high state (decimal value of 7)
and needed to count to the next code, they would all turn off
and the first major current source would turn on. To continue
counting upward, the 3 LSBs would count up another 7
codes, and then the next major current source would turn on
and the three LSBs would all turn off. The process of the
single, equivalent, major current source turning on and the
three LSBs turning off each time the converter reaches
another 7 codes greatly reduces the glitch at any one
switching point. In previous architectures that contained all
binary weighted current sources or a binary weighted
resistor ladder, the converter might have a substantially
larger amount of current turning on and off at certain, worst-
case transition points such as midscale and quarter scale
transitions. By greatly reducing the amount of current
switching at certain ‘major’ transitions, the overall glitch of
the converter is dramatically reduced, improving settling
times and transient problems.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through R
).
SET
Full Scale Gain Drift, is measured by setting the data inputs
to all ones and measuring the output voltage through a
known resistance as the temperature is varied from T
to
. It is defined as the maximum deviation from the value
MIN
T
MAX
measured at room temperature to the value measured at
either T or . The units are ppm of FSR (full scale
MIN
MAX
range) per degree C.
Total Harmonic Distortion, THD, is the ratio of the DAC output
fundamental to the RMS sum of the first five harmonics.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental to the largest harmonically or
non-harmonically related spur within the specified window.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance load should
be chosen such that the voltage developed does not violate
the compliance range.
Offset Error, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance. Offset error is defined as the maximum deviation
of the output current from a value of 0mA.
Digital Inputs and Termination
Offset Drift, is measured by setting the data inputs to all
The HI5660 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
zeros and measuring the output voltage through a known
resistance as the temperature is varied from T
to
. It
MAX
MIN
is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either T or T . The units are ppm of FSR (full scale
MIN
MAX
range) per degree C.
implemented. If the lines driving the clock and the digital
7
HI5660
inputs are 50Ω lines, then 50Ω termination resistors should
be placed as close to the converter inputs as possible
connected to the digital ground plane (if separate grounds
are used).
Outputs
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
Ground Plane(s)
If separate digital and analog ground planes are used, then
all of the digital functions of the device and their
corresponding components should be over the digital ground
plane and terminated to the digital ground plane. The same
is true for the analog components and the analog ground
plane.
compliance range of -0.3V to 1.25V. R
should be
LOAD
chosen so that the desired output voltage is produced in
conjunction with the output full scale current, which is
described above in the ‘Reference’ section. If a known line
impedance is to be driven, then the output load resistor
should be chosen to match this impedance. The output
voltage equation is:
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should
be placed as close as possible to the converter’s power
supply pins, AV
designed using separate digital and analog ground planes,
and DV . Also, should the layout be
DD
DD
V
= I
OUT
X R .
LOAD
OUT
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 21
and 22 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
these capacitors should be terminated to the digital ground
for DV
and to the analog ground for AV . Additional
DD
DD
filtering of the power supplies on the board is
recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ±60 ppm/oC drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1µF capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO
pin (16) selects the reference. The internal reference can
be selected if pin 16 is tied low (ground). If an external
reference is desired, then pin 16 should be tied high (to the
analog supply voltage) and the external reference driven
into REFIO, pin 17. The full scale output current of the
converter is a function of the voltage reference used and
is -300mV, imposing a maximum of 600mV
amplitude
P-P
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
V
= (2 x I
x R )V
OUT EQ
OUT
50Ω
100Ω
50Ω
IOUTB
IOUTA
PIN 21
50Ω
PIN 22
HI5660
the value of R
. I should be within the 2mA to 20mA
SET OUT
range, through operation below 2mA is possible, with
performance degradation.
If the internal reference is used, V
FSADJ
will equal
FIGURE 4.
approximately 1.16V (pin 18). If an external reference is
used, V will equal the external reference. The
FSADJ
calculation for I
V
= 2 x I
x R , where R is ~12.5Ω.
EQ EQ
OUT
OUT
(full scale) is:
OUT
I
(Full Scale) = (V
/R
)x 32.
OUT
FSADJ SET
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86kΩ R
SET
resistor, then the input coding to output current will resemble
the following:
TABLE 1. INPUT CODING vs OUTPUT CURRENT
INPUT CODE (D7-D0)
111 11111
IOUTA (mA)
IOUTB (mA)
20
10
0
0
100 00000
10
20
000 00000
8
HI5660
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
1-8
D7 (MSB) Through Digital Data Bit 7, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
D0 (LSB)
9-14
15
DCOM
SLEEP
Connect to digital ground.
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20µA active pulldown current.
16
17
18
REFLO
REFIO
FSADJ
Connect to analog ground to enable internal 1.2V reference or connect to AV
ence.
to disable internal refer-
DD
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is en-
abled. Use 0.1µF cap to ground when internal reference is enabled.
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x V
/R .
FSADJ SET
19
20
21
COMP1
ACOM
IOUTB
For use in reducing bandwidth/noise. Recommended: connect 0.1µF to AV
.
DD
Analog Ground.
The complimentary current output of the device. Full scale output current is achieved when all input bits
are set to binary 0.
22
23
IOUTA
NC
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
Internally connected to ACOM via a resistor. Recommend leave disconnected. Adding a capacitor to
ACOM for upward compatibility is valid. Grounding to ACOM is valid. (For upward compatibility to 12-bit
and 14-bit devices, pin 23 needs the ability to have a 0.1µF capacitor to ACOM.)
24
25
26
27
28
AV
DD
Analog Supply (+3V to +5V).
NC
DCOM
DV
No Connect (for upward compatibility to 12 and 14b, pin 25 needs to be grounded to ACOM).
Digital Ground.
Digital Supply (+3V to +5V).
DD
CLK
Input for clock. Positive edge of clock latches data.
9
HI5660
Thin Shrink Small Outline Plastic Packages (TSSOP)
M28.173
N
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.386
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
9.80
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.378
0.169
0.05
0.80
0.19
0.09
9.60
4.30
-
L
-
0.25
0.010
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
E1
e
3
-C-
4
α
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
α
28
28
7
o
o
o
o
NOTES:
0
8
0
8
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
Rev. 0 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
10
HI5660
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
-A-
0.7125 17.70
3
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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