HI5735 [INTERSIL]
12-Bit, 80 MSPS, High Speed Video D/A Converter; 12位， 80 MSPS ，高速视频D / A转换器
| 型号： | HI5735 |
| 厂家： | 
Intersil |
| 描述： | 12-Bit, 80 MSPS, High Speed Video D/A Converter |
| 文件： | 总12页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5735
12-Bit, 80 MSPS,
High Speed Video D/A Converter
January 1998
Features
Description
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 80 MSPS The HI5735 is a 12-bit, 80 MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
-20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser trim-
ming assures 12-bit linearity is maintained along the entire
transfer curve.
• Integral Linearity Error . . . . . . . . . . . . . . . . . . 0.75 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . .3.0pV-s
• TTL/CMOS Compatible Inputs
• Improved Hold Time . . . . . . . . . . . . . . . . . . . . . . 0.25ns
• Excellent Spurious Free Dynamic Range
Applications
Ordering Information
• Professional Video
• Cable TV Headend Equipment
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
28 Lead PDIP
28 Lead SOIC
HI5735KCP
HI5735KCB
0 to 70
0 to 70
E28.6
M28.3
Pinout
HI5735
(PDIP, SOIC)
TOP VIEW
D11 (MSB)
1
2
3
4
5
6
7
8
9
28
DGND
D10
D9
D8
D7
D6
D5
D4
D3
27 AGND
26 REF OUT
25 CTRL OUT
24 CTRL IN
23 R
SET
22 AV
EE
OUT
21 I
20
I
OUT
19 ARTN
18 DV
D2 10
D1 11
EE
17 DGND
16 DV
D0 (LSB) 12
NC 13
CC
15 CLOCK
NC 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 4133.3
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1621
HI5735
Typical Application Circuit
+5V
HI5735
0.01µF
V
(16)
CC
D11 (MSB) (1)
D10 (2)
D9 (3)
D11
0.1µF
D10
D9
D8
D7
D6
D5
D4
D3
(24) CTRL IN
(25) CTRL OUT
D8 (4)
-5.2V (AV
)
EE
D7 (5)
(26) REF OUT
D6 (6)
D5 (7)
D/A OUT
(21) I
OUT
64Ω
D4 (8)
D3 (9)
64Ω
D2 (10)
D2
D1
D0
(20) I
OUT
D1 (11)
(23) R
SET
D0 (LSB) (12)
976Ω
(19) ARTN
(27) AGND
CLK (15)
50Ω
DGND (17, 28)
(22) AV
EE
DV (18)
EE
0.01µF
0.1µF
0.01µF
0.1µF
- 5.2V(AV
)
- 5.2V(DV
)
EE
EE
Functional Block Diagram
(LSB) D0
D1
D2
D3
8 LSBs
CURRENT
CELLS
R2R
NETWORK
D4
DATA
BUFFER/
LEVEL
12-BIT
MASTER
REGISTER
D5
D6
D7
D8
ARTN
SLAVE
REGISTER
SHIFTER
227Ω
227Ω
15
15
15
D9
D10
UPPER
4-BIT
DECODER
SWITCHED
CURRENT
CELLS
I
I
OUT
(MSB) D11
OUT
REF CELL
CTRL
IN
CLK
25Ω
+
OVERDRIVEABLE
VOLTAGE
REFERENCE
CTRL
OUT
-
R
SET
AV
AGND DV
DGND
V
CC
REF OUT
EE
EE
1622
HI5735
Absolute Maximum Ratings
Thermal Information
o
Digital Supply Voltage V
to DGND . . . . . . . . . . . . . . . . . . .+5.5V Thermal Resistance (Typical, Note 1)
θJA ( C/W)
CC
Negative Digital Supply Voltage DV to DGND . . . . . . . . . . . -5.5V
EE
Negative Analog Supply Voltage AV to AGND, ARTN . . . . . -5.5V
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
55
70
EE
Digital Input Voltages (D11-D0, CLK) to DGND . . . . . DV
to -0.5V
CC
Internal Reference Output Current . . . . . . . . . . . . . . . . . . . . ±2.5mA
o
o
o
Voltage from CTRL IN to AV . . . . . . . . . . . . . . . . . . . . . 2.5V to 0V
EE
o
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
(SOIC - Lead Tips Only)
Reference Input Voltage Range . . . . . . . . . . . . . . . . . -3.7V to AV
EE
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . .30mA
Operating Conditions
Temperature Range
HI5735BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications AV , DV = -4.94 to -5.46V, V = +4.75 to +5.25V, V = Internal
REF
EE
EE
CC
o
T = 25 C for All Typical Values
A
HI5735BI
= 0 C TO 70 C
o
o
T
A
PARAMETER
SYSTEM PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
12
-
0.75
0.5
20
1
-
1.5
1.0
75
10
0.05
-
Bits
LSB
LSB
µA
Integral Linearity Error, INL
Differential Linearity Error, DNL
(Note 4) (“Best Fit” Straight Line)
-
(Note 4)
-
Offset Error, I
(Note 4)
-
OS
Full Scale Gain Error, FSE
Offset Drift Coefficient
(Notes 2, 4)
(Note 3)
-
%
o
-
-
-
µA/ C
Full Scale Output Current, I
20.48
-
mA
V
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Throughput Rate
(Note 3)
(Note 5)
-1.25
0
80
-
-
-
-
MSPS
ns
Output Voltage Full Scale Step
To ±0.5 LSB Error Band R = 50Ω
20
L
Settling Time, t
SETT
Full Scale
(Note 3)
Single Glitch Area, GE (Peak)
Doublet Glitch Area, (Net)
Output Slew Rate
R
= 50Ω (Note 3)
-
-
-
5
3
-
-
-
pV-s
pV-s
V/µs
L
L
R
= 50Ω, DAC Operating in Latched Mode
1,000
(Note 3)
Output Rise Time
Output Fall Time
R
= 50Ω, DAC Operating in Latched Mode
-
-
675
470
-
-
ps
ps
L
(Note 3)
R
= 50Ω, DAC Operating in Latched Mode
L
(Note 3)
Differential Gain
R
R
= 50Ω (Note 3)
= 50Ω (Note 3)
-
-
0.15
0.07
-
-
%
L
L
Differential Phase
Deg
1623
HI5735
Electrical Specifications AV , DV = -4.94 to -5.46V, V = +4.75 to +5.25V, V = Internal
REF
EE
EE
CC
o
T = 25 C for All Typical Values (Continued)
A
HI5735BI
= 0 C TO 70 C
o
o
T
A
PARAMETER
TEST CONDITIONS
MIN
TYP
70
MAX
UNITS
dBc
Spurious Free Dynamic Range to Nyquist
(Note 3)
f
f
= 40MHz, f
= 80MHz, f
= 2.02MHz, 20MHz Span
= 2.02MHz, 40MHz Span
-
-
-
-
CLK
OUT
70
dBc
CLK
OUT
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, V
REF
(Note 4)
(Note 3)
(Note 3)
-1.27
-
-1.23
50
-1.17
-
V
o
Internal Reference Voltage Drift
µV/ C
Internal Reference Output Current Sink/Source
Capability
-125
-
+50
µA
Internal Reference Load Regulation
Input Impedance at REF OUT pin
I
= 0 to I
= -125µA
REF
-
-
-
-
-
-
50
1.4
3
-
-
-
-
-
-
µV
kΩ
REF
(Note 3)
Amplifier Large Signal Bandwidth (0.6V
Amplifier Small Signal Bandwidth (0.1V
Reference Input Impedance
)
Sine Wave Input, to Slew Rate Limited (Note 3)
Sine Wave Input, to -3dB Loss (Note 3)
(Note 3)
MHz
MHz
kΩ
P-P
)
10
12
200
P-P
Reference Input Multiplying Bandwidth (CTL IN)
R
= 50Ω, 100mV Sine Wave, to -3dB Loss at
MHz
L
I
(Note 3)
OUT
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, V
IH
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 3)
2.0
-
-
V
Input Logic Low Voltage, V
-
-
-
-
-
-
0.8
400
700
-
V
IL
Input Logic Current, I
Input Logic Current, I
µA
µA
pF
IH
-
IL
Digital Input Capacitance, C
IN
3.0
TIMING CHARACTERISTICS
Data Setup Time, t
See Figure 1 (Note 3)
See Figure 1 (Note 3)
See Figure 1 (Note 3)
See Figure 1 (Note 3)
3.0
0.5
-
2.0
0.25
4.5
-
-
-
-
-
ns
ns
ns
ns
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
PD
CLK Pulse Width, t
, t
PW1 PW2
3.0
POWER SUPPLY CHARACTERISITICS
I
I
I
(Note 4)
(Note 4)
(Note 4)
(Note 4)
-
-
-
-
-
42
70
13
650
5
50
85
20
-
mA
mA
EEA
EED
CCD
mA
Power Dissipation
Power Supply Rejection Ratio
NOTES:
mW
µA/V
V
±5%, V ±5%
EE
-
CC
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
the ratio should be 16.
(typically 1.28mA). Ideally
SET
3. Parameter guaranteed by design or characterization and not production tested.
o
4. All devices are 100% tested at 25 C. 100% production tested at temperature extremes for military temperature devices, sample tested
for industrial temperature devices.
5. Dynamic Range must be limited to a 1V swing within the compliance range.
1624
HI5735
Timing Diagrams
50%
CLK
1
GLITCH AREA =
/ (H x W)
2
V
D11-D0
HEIGHT (H)
1
± / LSB ERROR BAND
2
I
OUT
t(ps)
WIDTH (W)
t
t
SETT
PD
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
t
t
PW2
PW1
50%
CLK
t
t
SU
t
SU
SU
t
HLD
t
t
HLD
HLD
D11-D0
t
PD
I
OUT
t
t
PD
PD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
1625
HI5735
Typical Performance Curves
-1.21
680
CLOCK FREQUENCY DOES NOT
ALTER POWER DISSIPATION
-1.23
-1.25
-1.27
640
600
560
-1.29
-50
-30
-10
10
30
50
70
90
-50
-30
-10
10
30
50
70
90
TEMPERATURE
TEMPERATURE
FIGURE 4. TYPICAL POWER DISSIPATION OVER
TEMPERATURE
FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER
TEMPERATURE
1.5
0.5
0.8
0.4
0.0
-0.5
1.5
-0.4
-0.8
0
600
1200
1800
2400
3000
3600
4200
400
1000
1600
2200
2800
3400
4000
CODE
CODE
FIGURE 6. TYPICAL INL
FIGURE 7. TYPICAL DNL
ATTEN 20dB
RL -10.0dBm
∆MKR -87.33dB
28
-73kHz
10dB/
f
= 10 MSPS
C
24
20
16
12
S
C
-40
-20
-0
20
40
60
80
100
TEMPERATURE
CENTER 1.237MHz
SPAN 2.000MHz
FIGURE 8. OFFSET CURRENT OVER TEMPERATURE
FIGURE 9. SPURIOUS FREE DYNAMIC RANGE = 87.3dBc
1626
HI5735
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1-12
D11 (MSB)
Digital Data Bit 11, the Most Significant Bit thru Digital Data Bit 0, the Least Significant Bit.
thru D0 (LSB)
15
13, 14
16
CLK
NC
Data Clock Pin DC to 80 MSPS.
No Connect.
V
Digital Logic Supply +5V.
Digital Ground.
CC
17, 28
18
DGND
DV
-5.2V Logic Supply.
EE
23
R
External resistor to set the full scale output current. I = 16 x (V
FS
/ R ). Typically 976Ω.
SET
SET
REF OUT
27
AGND
ARTN
Analog Ground supply current return pin.
Analog Signal Return for the R/2R ladder.
Current Output Pin.
19
21
I
I
OUT
20
Complementary Current Output Pin.
-5.2V Analog Supply.
OUT
22
AV
EE
24
CTRL IN
CTRL OUT
REF OUT
Input to the current source base rail. Typically connected to CTRL OUT and a 0.1µF capacitor to AV
Allows external control of the current sources.
.
EE
25
26
Control Amplifier Out. Provides precision control of the current sources when connected to CTRL IN such
that I = 16 x (V / R ).
FS SET
REF OUT
-1.23V (typical) bandgap reference voltage output. Can sink up to 125µA or be overdriven by an external
reference capable of delivering up to 2mA.
Detailed Description
The HI5735 is a 12-bit, current out D/A converter. The DAC to minimize reflections and clock noise into the part, proper
can convert at 80 MSPS and runs on +5V and -5.2V supplies. termination should be used. In PCB layout clock runs should
The architecture is an R/2R and segmented switching current be kept short and have a minimum of loads. To guarantee
cell arrangement to reduce glitch. Laser trimming is employed consistent results from board to board, controlled impedance
to tune linearity to true 12-bit levels. The HI5735 achieves its PCBs should be used with a characteristic line impedance
low power and high speed performance from an advanced
BiCMOS process. The HI5735 consumes 650mW (typical)
and has an improved hold time of only 0.25ns (typical).
Z of 50Ω.
O
To terminate the clock line, a shunt terminator to ground is
the most effective type at a 80 MSPS clock rate. A typical
value for termination can be determined by the equation:
Digital Inputs
R = Z ,
T
O
The HI5735 is a TTL/CMOS compatible D/A. Data is latched
by a Master register. Once latched, data inputs D0 (LSB)
thru D11 (MSB) are internally translated from TTL to ECL.
The internal latch and switching current source controls are
implemented in ECL technology to maintain high switching
speeds and low noise characteristics.
for the termination resistor. For a controlled impedance
board with a Z of 50Ω, the R = 50Ω. Shunt termination is
best used at the receiving end of the transmission line or as
O
T
close to the HI5735 CLK pin as possible.
Decoder/Driver
The architecture employs a split R/2R ladder and Seg-
mented Current source arrangement. Bits D0 (LSB) thru D7
directly drive a typical R/2R network to create the binary
weighted current sources. Bits D8 thru D11 (MSB) pass thru
a “thermometer” decoder that converts the incoming data
into 15 individual segmented current source enables. This
split architecture helps to improve glitch, thus resulting in a
more constant glitch characteristic across the entire output
transfer function.
HI5735
DAC
Z
= 50Ω
CLK
O
R
= 50Ω
T
FIGURE 10. CLOCK LINE TERMINATION
Rise and Fall times and propagation delay of the line will be
affected by the Shunt Terminator. The terminator should be
connected to DGND.
Clocks and Termination
The internal 12-bit register is updated on the rising edge of
the clock. Since the HI5735 clock rate can run to 80 MSPS,
1627
HI5735
Noise Reduction
TABLE 2. INPUT CODING vs CURRENT OUTPUT
To reduce power supply noise, separate analog and digital
power supplies should be used with 0.1µF and 0.01µF
ceramic capacitors placed as close to the body of the
INPUT CODE (D11-D0)
1111 1111 1111
I
(mA)
I
(mA)
OUT
OUT
-20.48
0
HI5735 as possible on the analog (AV ) and digital (DV
)
EE EE
supplies. The analog and digital ground returns should be
connected together back at the device to ensure proper
1000 0000 0000
-10.24
0
-10.24
-20.48
0000 0000 0000
operation on power up. The V
power pin should also be
CC
decoupled with a 0.1µF capacitor.
Settling Time
Reference
The settling time of the HI5735 is measured as the time it
takes for the output of the DAC to settle to within a 1/2 LSB
error band of its final value during a full scale (code 0000...
to 1111.... or 1111... to 0000...) transition. All claims made by
Intersil with respect to the settling time performance of the
HI5735 have been fully verified by the National Institute of
Standards and Technology (NIST) and are fully traceable.
The internal reference of the HI5735 is a -1.23V (typical)
bandgap voltage reference with 50µV/ C of temperature drift
o
(typical). The internal reference is connected to the Control
Amplifier which in turn drives the segmented current cells.
Reference Out (REF OUT) is internally connected to the
Control Amplifier. The Control Amplifier Output (CTRL OUT)
should be used to drive the Control Amplifier Input (CTRL
Glitch
IN) and a 0.1µF capacitor to analog V . This improves set-
EE
The output glitch of the HI5735 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically, the switching time of digital
inputs are asymmetrical, meaning that the turn off time is
faster than the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
to change before another. In order to minimize this, the Inter-
sil HI5735 employes an internal register, just prior to the cur-
rent sources, which is updated on the clock edge. Lastly, the
worst case glitch on traditional D/A converters usually occurs
at the major transition (i.e., code 2047 to 2048). However,
due to the split architecture of the HI5735, the glitch is
moved to the 255 to 256 transition (and every subsequent
256 code transitions thereafter). This split R/2R segmented
current source architecture, which decreases the amount of
current switching at any one time, makes the glitch practi-
cally constant over the entire output range. By making the
glitch a constant size over the entire output range, this effec-
tively integrates this error out of the end application.
tling time by providing an AC ground at the current source
base node. The Full Scale Output Current is controlled by
the REF OUT pin and the set resistor (R
). The ratio is:
SET
I
(Full Scale) = (V
/R ) x 16.
REF OUT SET
OUT
The internal reference (REF OUT) can be overdriven with a
more precise external reference to provide better
performance over temperature. Figure 11 illustrates a typical
external reference configuration.
HI5735
-1.25V
R
(26) REF OUT
-5.2V
FIGURE 11. EXTERNAL REFERENCE CONFIGURATION
Outputs
In measuring the output glitch of the HI5735 the output is
terminated into a 64Ω load. The glitch is measured at any
one of the current cell carry (code 255 to 256 transition or
any multiple thereof) throughout the DACs output range.
The outputs I
and I
OUT
are complementary current
or I in proportion
OUT
outputs. Current is steered to either I
OUT
OUT
to the digital input code. The sum of the two currents is always
equal to the full scale current minus one LSB. The current out-
put can be converted to a voltage by using a load resistor. Both
current outputs should have the same load resistor (64Ω typi-
cally). By using a 64Ω load on the output, a 50Ω effective output
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 13 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt-seconds (pV-s).
resistance (R
) is achieved due to the 227Ω (±15%) parallel
OUT
resistance seen looking back into the output. This is the nomi-
nal value of the R2R ladder of the DAC. The 50Ω output is
needed for matching the output with a 50Ω line. The load resis-
tor should be chosen so that the effective output resistance
HI5735
100MHz
SCOPE
(R
) matches the line resistance. The output voltage is:
LOW PASS
FILTER
(21) I
OUT
OUT
V
= I x R
.
OUT
OUT
OUT
64Ω
50Ω
I
is defined in the reference section. I is not trimmed
OUT
OUT
to 12 bits, so it is not recommended that it be used in
conjunction with I in a differential-to-single-ended appli-
OUT
cation. The compliance range of the output is from -1.25V to
0V, with a 1V voltage swing allowed within this range.
FIGURE 12. GLITCH TEST CIRCUIT
P-P
1628
HI5735
Definition of Specifications
Applications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Bipolar Applications
Differential Linearity Error, DNL, is the measure of the
error in step size between adjacent codes along the con-
verter’s transfer curve. Ideally, the step size is 1 LSB from
one code to the next, and the deviation from 1 LSB is known
as DNL. A DNL specification of greater than -1 LSB guaran-
tees monotonicity.
a (mV)
Feedthru, is the measure of the undesirable switching noise
coupled to the output.
GLITCH ENERGY = (a x t)/2
Output Voltage Full Scale Settling Time, is the time
t (ns)
required from the 50% point on the clock input for a full scale
1
step to settle within an ± / LSB error band.
2
FIGURE 13. MEASURING GLITCH ENERGY
Output Voltage Small Scale Settling Time, is the time
required from the 50% point on the clock input for a 100mV
step to settle within an / LSB error band. This is used by
2
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
1
To convert the output of the HI5735 to a bipolar 4V swing, the
following applications circuit is recommended. The reference
can only provide 125µA of drive, so it must be buffered to
create the bipolar offset current needed to generate the -2V
output with all bits “off”. The output current must be converted
to a voltage and then gained up and offset to produce the
proper swing. Care must be taken to compensate for the
voltage swing and error
Glitch Area, GE, is the switching transient appearing on the
output during a code transition. It is measured as the area
under the curve and expressed as
specification (typically pV•s).
a picoVolt•Time
Differential Gain, ∆A , is the gain error from an ideal sine
V
wave with a normalized amplitude.
5kΩ
Differential Phase, ∆Φ, is the phase error from an ideal
sine wave.
-
-
REF OUT
(26)
+
+
5kΩ
60Ω
1/2 CA2904
1/2 CA2904
Signal to Noise Ratio, SNR, is the ratio of a fundamental to
the noise floor of the analog output. The first 5 harmonics
are ignored, and an output filter of / the clock frequency is
2
used to eliminate alias products.
1
0.1µF
240Ω
240Ω
HI5735
Total Harmonic Distortion, THD, is the ratio of the DAC
50Ω
output fundamental to the RMS sum of the harmonics. The
I
V
OUT
OUT
(21)
-
1
first 5 harmonics are included, and an output filter of / the
2
+
clock frequency is used to eliminate alias products.
HFA1100
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from a fundamental to the largest harmonically or
FIGURE 14. BIPOLAR OUTPUT CONFIGURATION
non-harmonically related spur. A sine wave is loaded into the
1
D/A and the output filtered at
/
the clock frequency to
2
eliminate noise from clocking alias terms.
Intermodulation Distortion, IMD, is the measure of the
sum and difference products produced when a two tone
input is driven into the D/A. The distortion products created
will arise at sum and difference frequencies of the two tones.
IMD can be calculated using the following equation:
20Log (RMS of Sum and Difference Distortion Products)
IMD =
.
------------------------------------------------------------------------------------------------------------------------------------------------------
(RMS Amplitude of the Fundamental)
1629
HI5735
Die Characteristics
DIE DIMENSIONS:
DIE ATTACH:
161.5 mils x 160.7 mils x 19 mils ±1 mil
Silver Filled Epoxy
METALLIZATION:
SUBSTRATE POTENTIAL (Powered Up):
Type: AlSiCu
Thickness: M1 - 8kÅ, M2 - 17kÅ
V
EED
PASSIVATION:
Type: Sandwich Passivation
Undoped Silicon Glass (USG) + Nitride
Thickness: USG - 8kÅ, Nitride - 4.2kÅ
Total 12.2kÅ ± +2kÅ
Metallization Mask Layout
HI5735
D11
D8
D9
D10
DGND
CTRL OUT
CTRL IN
D7
D6
R
SET
D5
AV
EE
D4
I
OUT
D3
D2
I
OUT
ARTN
D1
D0
CLK
DV
CC
DGND
DV
EE
1630
HI5735
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-001-BF ISSUE D)
28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC
PACKAGE
N
E1
INDEX
AREA
1 2
3
N/2
INCHES
MILLIMETERS
-B-
-C-
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
BASE
PLANE
A2
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
39.7
-
-
A
SEATING
PLANE
-
L
C
L
B1
C
8
D1
B1
eA
A1
A
D1
-
e
C
eC
B
D
35.1
5
eB
0.010 (0.25)
C
B
S
M
D1
E
0.13
15.24
12.32
5
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
e
e
6
A
B
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
-
0.700
0.200
-
17.78
5.08
7
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
N
28
28
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
Rev. 0 12/93
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
1631
HI5735
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
M
M
B
0.25(0.010)
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
-A-
0.7125 17.70
3
o
D
h x 45
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
α
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
M
M
S
B
0.25(0.010)
C
A
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
1632
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