HI5812JIBZ [INTERSIL]
CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold; CMOS 20微秒, 12位,采样A / D转换器,内置跟踪保持型号: | HI5812JIBZ |
厂家: | Intersil |
描述: | CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
文件: | 总16页 (文件大小:365K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HI5812
®
Data Sheet
March 31, 2005
FN3214.6
CMOS 20 Microsecond, 12-Bit, Sampling
A/D Converter with Internal Track and
Hold
Features
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µs
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 50 kSPS
• Built-In Track and Hold
The HI5812 is a fast, low power, 12-bit, successive
approximation analog-to-digital converter. It can operate
from a single 3V to 6V supply and typically draws just 1.9mA
when operating at 5V. The HI5812 features a built-in track
and hold. The conversion time is as low as 20µs with a 5V
supply.
• Guaranteed No Missing Codes Over Temperature
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V
• Maximum Power Consumption. . . . . . . . . . . . . . . . 25mW
• Internal or External Clock
The twelve data outputs feature full high speed CMOS
three-state bus driver capability, and are latched and held
through a full conversion cycle. The output is user
selectable, i.e., 12-bit, 8-bit (MSBs), and/or 4-bit (LSBs). A
data ready flag, and conversion-start input complete the
digital interface.
• Pb-Free Available (RoHS Compliant)
Applications
• Remote Low Power Data Acquisition Systems
• Digital Audio
An internal clock is provided and is available as an output.
The clock may also be over-driven by an external source.
• DSP Modems
• General Purpose DSP Front End
• µP Controlled Measurement System
• Professional Audio Positioner/Fader
Ordering Information
INL (LSB)
TEMP.
PART
(MAX OVER RANGE
PKG.
DWG. #
o
NUMBER
TEMP.)
±1.5
( C)
PACKAGE
Pinout
HI5812JIP
-40 to 85 24 Ld PDIP
E24.3
E24.3
HI5812
(PDIP, SOIC)
TOP VIEW
HI5812JIPZ
(See Note)
±1.5
-40 to 85 24 Ld PDIP*
(Pb-free)
DRDY
(LSB) D0
D1
1
2
3
4
5
6
7
8
9
24
V
HI5812JIB
±1.5
±1.5
-40 to 85 24 Ld SOIC
M24.3
M24.3
DD
23 OEL
22 CLK
21 STRT
HI5812JIBZ
(See Note)
-40 to 85 24 Ld SOIC
(Pb-free)
D2
HI5812KIB
±1.0
±1.0
-40 to 85 24 Ld SOIC
M24.3
M24.3
D3
20 V
19 V
-
REF
REF
D4
+
HI5812KIBZ
(See Note)
-40 to 85 24 Ld SOIC
(Pb-free)
D5
18
V
IN
D6
17 V
+
AA
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
D7
16
V
-
AA
D8 10
D9 11
15 OEM
14 D11 (MSB)
13 D10
V
12
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI5812
Functional Block Diagram
STRT
V
DD
TO INTERNAL LOGIC
V
SS
V
IN
CLK
CLOCK
CONTROL
+
TIMING
DRDY
32C
OEM
V
+
REF
16C
8C
D11 (MSB)
50Ω
SUBSTRATE
D10
D9
4C
2C
V
+
AA
C
D8
D7
V
-
32C
AA
64C
63
16C
8C
12-BIT
12-BIT EDGE
TRIGGERED
“D” LATCHES
SUCCESSIVE
APPROXIMATION
REGISTER
D6
D5
D4
D3
4C
2C
C
C
P1
D2
D1
V
-
REF
D0 (LSB)
OEL
2
HI5812
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
V
to V
. . . . . . . . . . . . . . . . . . . . (V -0.5V) < V
SS
< +6.5V
DD
DD
SS
PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
70
75
V
+ to V - . . . . . . . . . . . . . . . . . . . (V -0.5V) to (V +6.5V)
+ to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
AA AA SS SS
V
AA DD
o
Analog and Reference Inputs
, V +, V - . . . . . . . . (V -0.3V) < V
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C
ο
o
V
< (V
+0.3V)
+0.3V)
IN REF REF SS
INA
DD
DD
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
o
Digital I/O Pins . . . . . . . . . . . . . . . (V -0.3V) < V < (V
SS I/O
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300 C
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications
V
= V + = 5V, V
AA
+ = +4.608V, V = V - = V
REF SS AA
- = GND, CLK = External 750kHz,
REF
DD
Unless Otherwise Specified
o
o
o
25 C
-40 C TO 85 C
PARAMETER
ACCURACY
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
Resolution
12
-
-
-
-
-
-
-
-
-
-
-
12
-
-
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Linearity Error, INL
(End Point)
J
±1.5
±1.0
±2.0
±1.0
±3.0
±2.5
±2.0
±1.0
±1.5
±1.0
±2.0
±1.0
±3.0
±2.5
±2.0
±1.0
K
J
-
-
Differential Linearity Error, DNL
-
-
K
J
-
-
Gain Error, FSE
(Adjustable to Zero)
-
-
K
J
-
-
Offset Error, V
OS
(Adjustable to Zero)
-
-
K
-
-
Power Supply Rejection, PSRR
Offset Error PSRR
Gain Error PSRR
V
V
V
= 4V
-
-
REF
= V + = 5V ±5%
±0.1
±0.1
±0.5
±0.5
±0.5
±0.5
LSB
LSB
DD
DD
AA
= V + = 5V ±5%
AA
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
J
f
f
= Internal Clock, f = 1kHz
IN
-
-
-
-
-
-
68.8
69.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
S
S
= 750kHz, f = 1kHz
IN
RMS Noise + Distortion
K
J
f
f
= Internal Clock, f = 1kHz
IN
71.0
71.5
dB
dB
S
S
= 750kHz, f = 1kHz
IN
Signal to Noise Ratio, SNR
RMS Signal
f
f
= Internal Clock, f = 1kHz
IN
70.5
71.1
dB
dB
S
S
= 750kHz, f = 1kHz
IN
RMS Noise
K
J
f
f
= Internal Clock, f = 1kHz
IN
71.5
72.1
dB
dB
S
S
= 750kHz, f = 1kHz
IN
Total Harmonic Distortion, THD
f
f
= Internal Clock, f = 1kHz
IN
-73.9
-73.8
dBc
dBc
S
S
= 750kHz, f = 1kHz
IN
K
f
f
= Internal Clock, f = 1kHz
IN
-80.3
-79.0
dBc
dBc
S
S
= 750kHz, f = 1kHz
IN
3
HI5812
Electrical Specifications
V
= V + = 5V, V
AA
+ = +4.608V, V = V - = V
- = GND, CLK = External 750kHz,
REF
DD
REF
SS
AA
Unless Otherwise Specified (Continued)
o
o
o
25 C
-40 C TO 85 C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
Spurious Free Dynamic Range,
SFDR
J
f
f
=Internal Clock, f = 1kHz
IN
-
-75.4
-75.1
-
-
-
dB
dB
S
S
= 750kHz, f = 1kHz
IN
K
f
f
= Internal Clock, f = 1kHz
IN
-
-80.9
-79.6
-
-
-
dB
dB
S
S
= 750kHz, f = 1kHz
IN
ANALOG INPUT
Input Current, Dynamic
Input Current, Static
Input Bandwidth -3dB
Reference Input Current
At V = V
IN
+, 0V
-
-
-
-
-
-
-
±50
±0.4
1
±100
-
-
-
-
-
-
-
±100
µA
µA
MHz
µA
W
REF
Conversion Stopped
±10
±10
-
-
-
-
-
-
-
-
-
-
160
420
380
20
Input Series Resistance, R
In Series with Input C
During Sample State
During Hold State
S
SAMPLE
HOLD
SAMPLE
Input Capacitance, C
Input Capacitance, C
pF
pF
DIGITAL INPUTS OEL, OEM, STRT
High-Level Input Voltage, V
2.4
-
-
-
2.4
-
0.8
±10
-
V
V
IH
Low-Level Input Voltage, V
IL
-
-
-
0.8
±10
-
-
-
-
Input Leakage Current, I
Except CLK, V = 0V, 5V
IN
-
µA
pF
IL
Input Capacitance, C
10
IN
DIGITAL OUTPUTS
High-Level Output Voltage, V
I
I
= -400µA
4.6
-
-
-
0.4
±10
-
4.6
-
0.4
±10
-
V
V
OH
SOURCE
Low-Level Output Voltage, V
= 1.6mA
-
-
-
-
-
-
OL
SINK
Three-State Leakage, I
Except DRDY, V
Except DRDY
= 0V, 5V
OUT
-
µA
pF
OZ
Output Capacitance, C
20
OUT
CLOCK
High-Level Output Voltage, V
I
I
= -100µA (Note 2)
4
-
-
-
-
-
4
-
-
V
V
OH
SOURCE
Low-Level Output Voltage, V
Input Current
= 100µA (Note 2)
1
1
OL
SINK
CLK Only, V = 0V, 5V
IN
-
±5
-
±5
mA
TIMING
Conversion Time (t
+ t
)
20
-
-
20
-
µs
CONV
ACQ
(Includes Acquisition Time)
Clock Frequency
Internal Clock, (CLK = Open)
External CLK (Note 2)
External CLK (Note 2)
(Note 2)
200
0.05
100
-
300
2
400
1.5
-
150
0.05
100
-
500
1.5
-
kHz
MHz
ns
Clock Pulse Width, t
, t
LOW HIGH
-
Aperture Delay, t APR
35
105
100
30
60
4
50
150
160
-
70
180
195
-
ns
D
Clock to Data Ready Delay, t DRDY
D1
(Note 2)
-
-
ns
Clock to Data Ready Delay, t DRDY
D2
(Note 2)
-
-
ns
Start Removal Time, t STRT
(Note 2)
75
85
10
-
75
100
15
-
ns
R
Start Setup Time, t STRT
SU
(Note 2)
-
-
ns
Start Pulse Width, t STRT
(Note 2)
-
-
ns
W
Start to Data Ready Delay, t DRDY
D3
(Note 2)
65
105
120
ns
4
HI5812
Electrical Specifications
V
= V + = 5V, V
AA
+ = +4.608V, V = V - = V
- = GND, CLK = External 750kHz,
REF
DD
REF
SS
AA
Unless Otherwise Specified (Continued)
o
o
o
25 C
-40 C TO 85 C
PARAMETER
TEST CONDITIONS
(Note 2)
MIN
TYP
60
MAX
-
MIN
MAX
-
UNITS
ns
Clock Delay from Start, t STRT
-
-
-
-
-
-
D
Output Enable Delay, t
(Note 2)
20
30
95
50
ns
EN
Output Disabled Delay, t
(Note 2)
80
120
ns
DIS
POWER SUPPLY CHARACTERISTICS
Supply Current, I
NOTE:
+ I
-
1.9
5
-
8
mA
DD
AA
2. Parameter guaranteed by design or characterization, not production tested.
Timing Diagrams
5 - 14
4
15
1
3
1
2
2
3
CLK
(EXTERNAL
OR INTERNAL)
t
LOW
t
DRDY
D1
t
HIGH
STRT
DRDY
t
DRDY
D2
DATA N - 1
D0 - D11
DATA N
HOLD N
V
IN
TRACK N
TRACK N + 1
OEL = OEM = V
SS
FIGURE 1. CONTINUOUS CONVERSION MODE
5
HI5812
Timing Diagrams (Continued)
2
2
3
15
2
4
1
5
CLK
(EXTERNAL)
t
STRT
t STRT
SU
R
t
STRT
W
STRT
t
DRDY
D3
DRDY
HOLD
HOLD
TRACK
V
IN
FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK
15
1
2
3
4
5
CLK
(INTERNAL)
t STRT
t STRT
D
R
t
STRT
W
STRT
DRDY
DON’T CARE
DRDY
t
D3
HOLD
HOLD
TRACK
V
IN
FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK
6
HI5812
Timing Diagrams (Continued)
OEL OR OEM
t
t
DIS
EN
1.6mA
90%
50%
D0 - D3 OR D4 - D11
HIGH IMPEDANCE
TO HIGH
TO
OUTPUT
PIN
+2.1V
50pF
HIGH
IMPEDANCE
50%
TO LOW
10%
-1.6mA
FIGURE 4A.
FIGURE 4. OUTPUT ENABLE/DISABLE TIMING DIAGRAM
FIGURE 4B.
1.6mA
+2.1V
50pF
-400µA
FIGURE 5. GENERAL TIMING LOAD CIRCUIT
7
HI5812
Typical Performance Curves
1.0
1.5
V
V
= V + = 5V
AA
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
DD
V
= V + = 5V, V + = 4.608V
AA REF
DD
+ = 4.608V
REF
C
0.75
0.5
0.25
0
1
C
B
A
0.5
A
B
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
0
-60
-20
0
20
40
60
o
80
100 120 140
-40
-60
-20
0
20
40
60
o
80 100 120 140
-40
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 6. INL vs TEMPERATURE
FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE
1.0
0.75
0.5
2
1.5
1
o
C
V
= V + = 5V, T = 25 C
V
= V + = 5V, V
AA
+ = 4.608V
REF
DD
AA
A
DD
CLK = 750kHz
B
FSE
A
DNL
INL
0.25
0
0.5
0
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
V
OS
3
3.2
3.4
3.6
3.8
4
4.2
(V)
4.4
4.6
-60
-20
0
20
40
60
80 100 120 140
-40
o
REFERENCE VOLTAGE, V
REF
TEMPERATURE ( C)
FIGURE 9. ACCURACY vs REFERENCE VOLTAGE
FIGURE 8. DNL vs TEMPERATURE
2
1.5
1
0.5
V
= V + = 5V,
AA
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
DD
V
= V + = 5V ±5%
AA
DD
V
+ = 4.608V
REF
CLK = 750kHz
+ = 4.0V
V
REF
0.375
0.25
0.125
0
C
B
0.5
0
PSRR V
OS
A
PSRR FSE
-60
-20
0
20
40
60
o
80 100 120 140
-60
-20
0
20
40
60
o
80 100 120 140
-40
-40
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 10. FULL SCALE ERROR vs TEMPERATURE
FIGURE 11. POWER SUPPLY REJECTION vs TEMPERATURE
8
HI5812
Typical Performance Curves (Continued)
8
INPUT FREQUENCY = 1kHz
SAMPLING RATE = 50kHz
SNR = 72.1dB
SINAD = 71.4dB
EFFECTIVE BITS = 11.5
THD = -79.1dBc
0.0
V
= V + = 5V, V + = 4.608V
AA REF
DD
-10.0
-20.0
-30.0
7
6
5
4
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-100.0
PEAK NOISE = -80.9dB
SFDR = -80.9dB
INTERNAL CLOCK
3
2
1
0
-110.0
-120.0
-130.0
-140.0
-60
-20
0
20
40
60
o
80
100 120 140
-40
0
500
1000
FREQUENCY BINS
1500
2000
TEMPERATURE ( C)
FIGURE 12. SUPPLY CURRENT vs TEMPERATURE
FIGURE 13. FFT SPECTRUM
500
450
400
350
300
250
200
150
12
V
= V + = 5V, V
AA
+ = 4.608V
REF
DD
11
10
B
V
= V + = 5V
AA
DD
V
+ = 4.608V
o
REF
9
8
T
= 25 C
A
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
C
A
7
-60
-20
0
20
40
60
80 100 120 140
-40
0.1
1
10
100
o
TEMPERATURE ( C)
INPUT FREQUENCY (kHz)
FIGURE 14. INTERNAL CLOCK FREQUENCY vs TEMPERATURE
-80
FIGURE 15. EFFECTIVE BITS vs INPUT FREQUENCY
75
70
65
B
C
-70
V
V
= V + = 5V
AA
DD
V
V
= V + = 5V
AA
DD
+ = 4.608V
o
REF
+ = 4.608V
o
A
REF
T
= 25 C
A
60
T
= 25 C
A
-60
-50
A. CLK =INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
B
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
55
50
C
A
0.1
1
10
100
0.1
1
10
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
FIGURE 16. TOTAL HARMONIC DISTORTION vs INPUT
FREQUENCY
FIGURE 17. SIGNAL NOISE RATIO vs INPUT FREQUENCY
9
HI5812
connected to the V
+ terminal; and the remaining
REF
-. The capacitor-common node, after the
TABLE 1. PIN DESCRIPTIONS
capacitors to V
REF
charges balance out, will indicate whether the input was
1
PIN NO. NAME
DESCRIPTION
above / of (V
+ - V -). At the end of the fourth
REF
2
REF
1
DRDY
Output flag signifying new data is available.
Goes high at end of clock period 15. Goes low
when new conversion is started.
period, the comparator output is stored and the MSB
capacitor is either left connected to V + (if the comparator
REF
was high) or returned to V
comparison to be at either / or / of (V
-. This allows the next
2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Bit 0 (Least Significant Bit, LSB).
REF
3
1
+ - V
-).
4
4
REF
REF
3
Bit 1.
4
Bit 2.
At the end of periods 5 through 14, capacitors representing
D10 through D1 are tested, the result stored, and each
5
Bit 3.
capacitor either left at V
+ or at V -.
REF
REF
6
Bit 4.
7
Bit 5.
At the end of the 15th period, when the LSB (D0) capacitor is
tested, (D0) and all the previous results are shifted to the
output registers and drivers. The capacitors are reconnected
to the input, the comparator returns to the balance state, and
the data-ready output goes active. The conversion cycle is
now complete.
8
Bit 6.
9
Bit 7.
10
11
12
13
14
15
16
17
18
19
Bit 8.
Bit 9.
V
Digital Ground (0V).
SS
Analog Input
D10
D11
OEM
Bit 10.
The analog input pin is a predominately capacitive load that
changes between the track and hold periods of the
conversion cycle. During hold, clock period 4 through 15, the
input loading is leakage and stray capacitance, typically less
than 5µA and 20pF.
Bit 11 (Most Significant Bit, MSB).
Three-State Enable for D4-D11. Active low input.
Analog Ground, (0V).
Analog Positive Supply. (+5V) (See text.)
Analog Input.
V
V
V
V
-
AA
AA
IN
+
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have
low enough impedance to dissipate the current spike by the
end of the tracking period as shown in Figure 18. The
amount of charge is dependent on supply and input
voltages. The average current is also proportional to clock
frequency.
+
-
Reference Voltage Positive Input, sets 4095
code end of input range.
REF
20
21
22
V
Reference Voltage Negative Input, sets 0 code
end of input range.
REF
STRT
CLK
Start Conversion Input Active Low, recognized
after end of clock period 15.
CLK Input or Output. Conversion functions are
synchronized to positive going edge. (See
text.)
23
24
OEL
Three-State Enable for D0 D3. Active Low Input.
Digital Positive Supply (+5V).
20mA
V
DD
I
IN
10mA
0mA
Theory of Operation
HI5812 is a CMOS 12-Bit Analog-to-Digital Converter that
uses capacitor-charge balancing to successively approximate
the analog input. A binarily weighted capacitor network forms
the A/D heart of the device. See the block diagram for the
HI5812.
CLK
5V
0V
5V
The capacitor network has a common node which is
connected to a comparator. The second terminal of each
DRDY
0V
200ns/DIV.
capacitor is individually switchable to the input, V
+ or
REF
CONDITIONS: V
= V + = 5.0V, V
+ = 4.608V,
REF
V
-.
DD
AA
REF
o
V
= 4.608V, CLK = 750kHz, T = 25 C
IN
A
During the first three clock periods of a conversion cycle, the
switchable end of every capacitor is connected to the input
and the comparator is being auto-balanced at the capacitor
common node.
FIGURE 18. TYPICAL ANALOG INPUT CURRENT
As long as these current spikes settle completely by end of
the signal acquisition period, converter accuracy will be
preserved. The analog input is tracked for 3 clock cycles.
With an external clock of 750kHz the track period is 4µs.
During the fourth period, all capacitors are disconnected
from the input; the one representing the MSB (D11) is
10
HI5812
A simplified analog input model is presented in Figure 19.
The HI5812 is specified with a 4.608V reference, however, it
will operate with a reference down to 3V having a slight
degradation in performance. A typical graph of accuracy vs
reference voltage is presented.
During tracking, the A/D input (V ) typically appears as a
IN
380pF capacitor being charged through a 420Ω internal
switch resistance. The time constant is 160ns. To charge this
capacitor from an external “zero Ω” source to 0.5 LSB
(1/8192), the charging time must be at least 9 time constants
Full Scale and Offset Adjustment
In many applications the accuracy of the HI5812 would be
sufficient without any adjustments. In applications where
accuracy is of utmost importance full scale and offset errors
may be adjusted to zero.
or 1.4µs. The maximum source impedance (R
for a 4µs acquisition time settling to within 0.5LSB is 750Ω.
Max)
SOURCE
If the clock frequency was slower, or the converter was not
restarted immediately (causing a longer sample time), a
higher source impedance could be tolerated.
The V
+ and V
REF
- pins reference the two ends of the
REF
analog input range and may be used for offset and full scale
adjustments. In a typical system the V - might be
REF
returned to a clean ground, and the offset adjustment done
on an input amplifier. V + would then be adjusted to null
V
IN
R
≈ 420Ω
SW
REF
out the full scale error. When this is not possible, the V
C
≈ 380pF
SAMPLE
-
REF
R
SOURCE
input can be adjusted to null the offset error, however, V
must be well decoupled.
-
–t
REF
ACQ
-------------------------------------------------------------
– R
SW
R
=
SOURCE(MAX)
–(N + 1)
C
In[2
]
SAMPLE
Full scale and offset error can also be adjusted to zero in the
signal conditioning amplifier driving the analog input (V ).
IN
FIGURE 19. ANALOG INPUT MODEL IN TRACK MODE
Control Signal
Reference Input
The HI5812 may be synchronized from an external source
by using the STRT (Start Conversion) input to initiate
conversion, or if STRT is tied low, may be allowed to free
run. Each conversion cycle takes 15 clock periods.
The reference input V
impedance source and be well decoupled.
+ should be driven from a low
REF
As shown in Figure 20, current spikes are generated on the
reference pin during each bit test of the successive
approximation part of the conversion cycle as the charge-
The input is tracked from clock period 1 through period 3,
then disconnected as the successive approximation takes
place. After the start of the next period 1 (specified by t
balancing capacitors are switched between V
- and
D
REF
data), the output is updated.
V
+ (clock periods 5 - 14). These current spikes must
REF
settle completely during each bit test of the conversion to not
degrade the accuracy of the converter. Therefore V + and
The DRDY (Data Ready) status output goes high (specified
REF
- should be well bypassed. Reference input V
by t DRDY) after the start of clock period 1, and returns low
D1
V
- is
REF
REF
normally connected directly to the analog ground plane. If
- is biased for nulling the converters offset it must be
(specified by t DRDY) after the start of clock period 2.
D2
The 12 data bits are available in parallel on three-state bus
driver outputs. When low, the OEM input enables the most
significant byte (D4 through D11) while the OEL input
V
REF
stable during the conversion cycle.
enables the four least significant bits (D0 - D3). t
specify the output enable and disable times.
and t
DIS
EN
20mA
I
10mA
REF+
If the output data is to be latched externally, either the trailing
edge of data ready or the next falling edge of the clock after
data ready goes high can be used.
0mA
When STRT input is used to initiate conversions, operation is
slightly different depending on whether an internal or
external clock is used.
5V
CLK
0V
Figure 3 illustrates operation with an internal clock. If the
5V
DRDY
STRT signal is removed (at least t STRT) before clock
R
0V
period 1, and is not reapplied during that period, the clock
will shut off after entering period 2. The input will continue to
track and the DRDY output will remain high during this time.
2µs/DIV.
CONDITIONS: V
= V + = 5.0V, V
AA
= 2.3V, CLK = 750kHz, T = 25 C
A
+ = 4.608V,
o
DD
REF
V
IN
A low signal applied to STRT (at least t STRT wide) can
W
now initiate a new conversion. The STRT signal (after a
FIGURE 20. TYPICAL REFERENCE INPUT CURRENT
delay of (t STRT)) causes the clock to restart.
D
11
HI5812
Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.
Power Supplies and Grounding
V
and V are the digital supply pins: they power all
DD
SS
internal logic and the output drivers. Because the output
drivers can cause fast current spikes in the V and V
DD SS
The input will continue to track until the end of period 3, the
same as when free running.
lines, V should have a low impedance path to digital
SS
ground and V
should be well bypassed.
DD
Figure 2 illustrates the same operation as above but with an
Except for V +, which is a substrate connection to V , all
AA
DD
external clock. If STRT is removed (at least t STRT) before
R
pins have protection diodes connected to V
and V .
DD
SS
clock period 2, a low signal applied to STRT will drop the
DRDY flag as before, and with the first positive-going clock
Input transients above V
the digital supplies.
or below V will get steered to
SS
DD
edge that meets the (t STRT) setup time, the converter will
SU
continue with clock period 3.
The V + and V - terminals supply the charge-balancing
AA AA
comparator only. Because the comparator is autobalanced
between conversions, it has good low-frequency supply
rejection. It does not reject well at high frequencies however;
Clock
The HI5812 can operate either from its internal clock or from
one externally supplied. The CLK pin functions either as the
clock output or input. All converter functions are
V
- should be returned to a clean analog ground and V +
AA AA
should be RC decoupled from the digital supply as shown in
Figure 22.
synchronized with the rising edge of the clock signal.
Figure 21 shows the configuration of the internal clock. The
clock output drive is low power: if used as an output, it
should not have more than 1 CMOS gate load applied, and
stray wiring capacitance should be kept to a minimum.
There is approximately 50Ω of substrate impedance
between V
and V +. This can be used, for example, as
AA
DD
part of a low-pass RC filter to attenuate switching supply
noise. A 10µF capacitor from V + to ground would
AA
The internal clock will shut down if the A/D is not restarted
after a conversion. The clock could also be shut down with
an open collector driver applied to the CLK pin. This should
only be done during the sample portion (the first three clock
periods) of a conversion cycle, and might be useful for using
the device as a digital sample and hold.
attenuate 30kHz noise by approximately 40dB. Note that
back-to-back diodes should be placed from V
to V + to
DD
AA
handle supply to capacitor turn-on or turn-off current spikes.
Dynamic Performance
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the A/D. A low
distortion sine wave is applied to the input of the A/D
converter. The input is sampled by the A/D and its output
stored in RAM. The data is than transformed into the
frequency domain with a 4096 point FFT and analyzed to
evaluate the converters dynamic performance such as SNR
and THD. See typical performance characteristics.
If an external clock is supplied to the CLK pin, it must have
sufficient drive to overcome the internal clock source. The
external clock can be shut off, but again, only during the
sample portion of a conversion cycle. At other times, it must
be above the minimum frequency shown in the
specifications. In the above two cases, a further restriction
applies in that the clock should not be shut off during the
third sample period for more than 1ms. This might cause an
internal charge-pump voltage to decay.
Signal-To-Noise Ratio
The signal to noise ratio (SNR) is the measured RMS signal
to RMS sum of noise at a specified input and sampling
frequency. The noise is the RMS sum of all except the
fundamental and the first five harmonic signals. The SNR is
dependent on the number of quantization levels used in the
converter. The theoretical SNR for an N-bit converter with no
differential or integral linearity error is: SNR = (6.02N + 1.76)
dB. For an ideal 12-bit converter the SNR is 74dB.
If the internal or external clock was shut off during the
conversion time (clock cycles 4 through 15) of the A/D, the
output might be invalid due to balancing capacitor droop.
An external clock must also meet the minimum t
and
LOW
times shown in the specifications. A violation may
t
HIGH
cause an internal miscount and invalidate the results.
Differential and integral linearity errors will degrade SNR.
INTERNAL
ENABLE
Sinewave Signal Power
SNR = 10 Log
Total Noise Power
CLOCK
CLK
OPTIONAL
EXTERNAL
CLOCK
Signal-To-Noise + Distortion Ratio
100kΩ
SINAD is the measured RMS signal to RMS sum of noise
plus harmonic power and is expressed by the following:
18pF
Sinewave Signal Power
SINAD = 10 Log
FIGURE 21. INTERNAL CLOCK CIRCUITRY
Noise + Harmonic Power (2nd - 6th)
12
HI5812
the fundamental RMS signal for a specified input and
sampling frequency.
Effective Number of Bits
The effective number of bits (ENOB) is derived from the
SINAD data;
Total Harmonic Power (2nd - 6th Harmonic)
THD = 10 Log
SINAD - 1.76
Sinewave Signal Power
ENOB =
6.02
Spurious-Free Dynamic Range
The spurious-free dynamic range (SFDR) is the ratio of the
fundamental RMS amplitude to the RMS amplitude of the
next largest spur or spectral component. If the harmonics are
buried in the noise floor it is the largest peak.
Total Harmonic Distortion
The total harmonic distortion (THD) is the ratio of the RMS
sum of the second through sixth harmonic components to
Sinewave Signal Power
SFDR = 10 Log
Highest Spurious Signal Power
TABLE 2. CODE TABLE
BINARY OUTPUT CODE
INPUT VOLTAGE†
= 4.608V
V
MSB
D11
LSB
REF+
CODE
DESCRIPTION
V
= 0.0V
DECIMAL
COUNT
REF-
(V)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Full Scale (FS)
4.6069
4.6058
3.4560
2.3040
1.1520
0.001125
0
4095
4094
3072
2048
1024
1
1
1
1
1
0
0
0
1
1
1
0
1
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
FS - 1 LSB
3
/
/
/
FS
FS
FS
4
2
4
1
1
1 LSB
Zero
0
† The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage.
+5V
0.1µF
4.7µF
10µF
0.1µF
0.1µF
0.01µF
V
+
V
DD
AA
D11
.
.
.
OUTPUT
DATA
D0
V
REF
V
REF+
4.7µF
0.001µF
DRDY
OEM
OEL
ANALOG
INPUT
V
V
IN
STRT
CLK
750kHz CLOCK
V
V
SS
REF-
AA-
FIGURE 22. GROUND AND SUPPLY DECOUPLING
13
HI5812
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
3200µm x 3940µm
Type: PSG
Thickness: 13kÅ ±2.5kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: AlSi
Thickness: 11kÅ ±1kÅ
5
2
1.84 x 10 A/cm
Metallization Mask Layout
HI5812
DRDY
D0
(LSB)
D1
V
OEL
DD
CLK
D2
D3
STRT
V
-
REF
D4
D5
D6
V
REF
+
D7
D8
V
IN
V
+
-
AA
V
AA
D9
V
D10
D11
(MSB)
OEM
SS
14
HI5812
Dual-In-Line Plastic Packages (PDIP)
E24.3 (JEDEC MS-001-AF ISSUE D)
24 LEAD NARROW BODY DUAL-IN-LINE PLASTIC
PACKAGE
N
E1
INDEX
AREA
1 2
3
N/2
INCHES
MILLIMETERS
-B-
-C-
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
0.015
0.115
0.014
0.045
0.008
1.230
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
31.24
0.13
7.62
6.10
4
BASE
PLANE
A2
A
0.195
0.022
0.070
0.014
1.280
-
4.95
0.558
1.77
0.355
32.51
-
-
SEATING
PLANE
-
L
C
L
B1
C
8
D1
B1
eA
A1
A
D1
-
e
eC
C
B
D
5
eB
0.010 (0.25) M
C
B S
D1
E
5
0.325
0.280
8.25
7.11
6
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
E1
e
5
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
e
e
6
A
B
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
-
0.430
0.150
-
10.92
3.81
7
4. Dimensions A, A1 and L are measured with the package seated in
L
0.115
2.93
4
9
JEDEC seating plane gauge GS-3.
N
24
24
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
Rev. 0 12/93
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
15
HI5812
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
15.60
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.5985
0.2914
0.0125
-
-A-
o
0.6141 15.20
3
h x 45
D
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
α
µ
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C A M B S
N
α
24
24
7
o
o
o
o
0
8
0
8
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
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