HI9P0303-9Z [INTERSIL]
Dual, SPDT CMOS Analog Switch; 双通道，单刀双掷CMOS模拟开关
| 型号： | HI9P0303-9Z |
| 厂家： | 
Intersil |
| 描述： | Dual, SPDT CMOS Analog Switch |
| 文件： | 总11页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-303
®
Data Sheet
November 17, 2004
FN3125.10
Dual, SPDT CMOS Analog Switch
Features
The HI-303 switch is a monolithic device fabricated using
CMOS technology and the Intersil dielectric isolation
process. This switch features break-before-make switching,
low and nearly constant ON resistance over the full analog
signal range, and low power dissipation.
• Analog Signal Range (±15V Supplies) . . . . . . . . . . ±15V
o
• Low Leakage at 25 C . . . . . . . . . . . . . . . . . . . . . . . 40pA
o
• Low Leakage at 125 C . . . . . . . . . . . . . . . . . . . . . . . 1nA
o
• Low On Resistance at 25 C . . . . . . . . . . . . . . . . . . . 35Ω
The HI-303 is TTL compatible and has a logic “0” condition
with an input less than 0.8V and a logic “1” condition with an
input greater than 4V. (See pinouts for switch conditions with
a logic “1” input.)
• Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns
• Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pC
• TTL, CMOS Compatible
• Symmetrical Switch Elements
Functional Diagram
S
• Low Operating Power (Typ) . . . . . . . . . . . . . . . . . . . . 1.0mW
• Pb-Free Available (RoHS Compliant)
IN
N
P
D
Applications
• Sample and Hold (i.e., Low Leakage Switching)
• Op Amp Gain Switching (i.e., Low On Resistance)
• Portable, Battery Operated Circuits
• Low Level Switching Circuits
Pinout Switch States Shown For A Logic “1” Input
HI-303 (PDIP, CERDIP, SOIC)
TOP VIEW
NC
1
2
3
4
5
6
14
13
12
11
10
9
V+
• Dual or Single Supply Systems
S
3
S
4
D
3
D
4
Ordering Information
D
1
D
2
PART
NUMBER
TEMP.
PKG. DWG.
#
S
1
S
2
o
RANGE ( C)
-55 to 125
0 to 75
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
IN
1
IN
2
HI1-0303-2
HI1-0303-5
HI3-0303-5
F14.3
F14.3
E14.3
E14.3
GND 7
8
V-
0 to 75
LOGIC
SW1, SW2 SW3, SW4
HI3-0303-5Z
(See Note)
0 to 75
14 Ld PDIP
(Pb-free)
0
1
OFF
ON
ON
HI9P0303-9
-40 to 85
-40 to 85
14 Ld SOIC
M14.15
M14.15
OFF
HI9P0303-9Z
(See Note)
14 Ld SOIC
(Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2004. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HI-303
Schematic Diagrams
A
V+
MN1B
MN2B MN3B
MP5B
MP4B
MN4B
IN
OUT
MN6B
MP3B MP2B
MP1B
V-
A
SWITCH CELL
V+
D2A
MP1A
MN1A
MP2A
MN2A
MP3A
MN3A
MP4A
MP5A
MN5A
MP6A
MP7A
MP8A
MN8A
200Ω
A
A
LOGIC
IN
D1A
MN4A
MN6A
MN7A
GND
V-
SWITCH CELL DRIVER
(ONE PER SWITCH CELL)
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
FN3125.10
November 17, 2004
2
HI-303
Absolute Maximum Ratings
Thermal Information
o
o
Voltage Between Supplies (V+ to V-). . . . . . . . . . . . . . . .44V (±22V)
Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V
Analog Input Voltage . . . . . . . . . . . . . . . . . . (V+) +1.5V to (V-) -1.5V
Typical Derating Factor . . . . . . . . . 1.5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
CERDIP Package. . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
80
90
120
24
N/A
N/A
o
Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
Operating Conditions
o
o
Temperature Range
HI-303-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HI-303-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
HI-303-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
o
(SOIC - Lead Tips Only)
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Supplies = +15V, -15V; V = Logic Input. V - for Logic “1” = 4V, for Logic “0” = 0.8V.
IN
IN
Unless Otherwise Specified
-2
-5, -9
TYP
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
MIN
MAX
UNITS
DYNAMIC CHARACTERISTICS
Switch ON Time, t
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
210
160
60
3
300
-
-
-
-
-
-
-
-
-
210
160
60
3
300
ns
ns
ON
Switch OFF Time, t
250
250
OFF
Break-Before-Make Delay, t
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
OPEN
Charge Injection Voltage, ∆V (Note 7)
mV
dB
pF
pF
pF
pF
OFF Isolation (Note 6)
60
16
14
35
5
60
16
14
35
5
Input Switch Capacitance, C
S(OFF)
Output Switch Capacitance, C
Output Switch Capacitance, C
D(OFF)
D(ON)
Digital Input Capacitance, C
IN
DIGITAL INPUT CHARACTERISTICS
Input Low Level, V
Full
Full
Full
Full
-
4
-
-
-
-
-
0.8
-
-
4
-
-
-
-
-
0.8
-
V
V
INL
Input High Level, V
(Note 10)
INH
Input Leakage Current (Low), I
(Note 5)
1
1
µA
µA
INL
Input Leakage Current (High), I
(Note 5)
-
1
-
1
INH
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range
Full
25
-15
-
+15
50
75
1
-15
-
+15
50
75
5
V
ON Resistance, r
(Note 2)
-
-
-
-
-
-
-
-
35
-
-
-
-
-
-
-
-
35
Ω
ON
Full
25
40
40
Ω
OFF Input Leakage Current, I
(Note 3)
0.04
1
0.04
0.2
0.04
0.2
0.03
0.2
nA
nA
nA
nA
nA
nA
S(OFF)
Full
25
100
1
100
5
OFF Output Leakage Current, I
(Note 3)
0.04
1
D(OFF)
Full
25
100
1
100
5
ON Leakage Current, I
(Note 4)
0.03
0.5
D(ON)
Full
100
100
FN3125.10
3
November 17, 2004
HI-303
Electrical Specifications Supplies = +15V, -15V; V = Logic Input. V - for Logic “1” = 4V, for Logic “0” = 0.8V.
IN
IN
Unless Otherwise Specified (Continued)
-2
-5, -9
TYP
TEMP
o
PARAMETER
POWER SUPPLY CHARACTERISTICS
Current, I+ (Note 8)
( C)
MIN
TYP
MAX
MIN
MAX
UNITS
25
Full
25
-
-
-
-
-
-
-
-
0.09
0.5
1
-
-
-
-
-
-
-
-
0.09
0.5
1
mA
mA
µA
µA
µA
µA
µA
µA
-
-
Current, I- (Note 8)
Current, I+ (Note 9)
Current, I- (Note 9)
NOTES:
0.01
10
0.01
100
-
Full
25
-
0.01
-
100
10
-
0.01
-
100
-
Full
25
100
10
0.01
-
0.01
-
100
-
Full
100
2. V = ±10V, I
OUT
=
10mA. On resistance derived from the voltage measured across the switch under these conditions.
14V.
S
3. V = ±14V, V
=
S
D
4. V = V = ±14V.
S
D
5. The digital inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected.
6. V = 1V , f = 500kHz, C = 15pF, R = 1K.
S
RMS
L
L
7. V = 0V, C = 10nF, Logic Drive = 5V pulse. Switches are symmetrical; S and D may be interchanged. Charge Injection = Q = C x ∆V.
S
L
L
8. V = 4V (one input, all other inputs = 0V).
IN
9. V = 0.8V (all inputs).
IN
10. To drive from DTL/TTL circuits, pullup resistors to +5V supply are recommended.
Test Circuits and Waveforms
V+
15V
LOGIC “1” = SWITCH ON
S
V
O
D
R
V
LOGIC
INPUT
0V
SWITCH
OUTPUT
INH
V
= +3V
S
50%
50%
C
L
L
300Ω
33pF
V
S
LOGIC
INPUT
90%
10%
V-
-15V
0V
SWITCH
OUTPUT
GND
t
OFF
t
ON
SWITCH TYPE
V
INH
4V
HI-303
FIGURE 1B. MEASUREMENT POINTS
FIGURE 1A. TEST CIRCUIT
FIGURE 1. SWITCH t
AND t
OFF
ON
FN3125.10
November 17, 2004
4
HI-303
Test Circuits and Waveforms (Continued)
+15V
V+
6
4
2
0
R
= 0
GEN
S
D
R
C
10pF
L
L
V
GEN
10kΩ
LOGIC INPUT
IN
V-
-15V
GND
V
LOGIC
0
0.4
0.8
TIME (µs)
1.2
1.6
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. TTL LOGIC INPUT
10
5
(NOTE 11)
5
0
V
= 10V
GEN
0
V
= 5V
GEN
0
0.4
0.8
TIME (µs)
1.2
1.6
0
0.4
0.8
1.2
1.6
TIME (µs)
FIGURE 2C. V
= 10V
FIGURE 2D. V
= 5V
ANALOG
ANALOG
5
0
0
V
= 0V
GEN
-5
-5
V
= -5V
GEN
0
0.4
0.8
1.2
1.6
0
0.4
0.8
1.2
1.6
TIME (µs)
TIME (µs)
FIGURE 2F. V
ANALOG
= -5V
FIGURE 2E. V
ANALOG
= 0V
FN3125.10
November 17, 2004
5
HI-303
Test Circuits and Waveforms (Continued)
0
-5
-10
V
= -10V
GEN
0
0.4
0.8
1.2
1.6
TIME (µs)
FIGURE 2G. V
ANALOG
= -10V
NOTE:
11. If R
, R or C is increased, there will be proportional increases in rise and/or fall RC times.
GEN
L
L
FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES
15V
LOGIC “1” = SWITCH ON
V+
S
D
R
C
= R = 300Ω
L2
LOGIC
INPUT
1
1
2
L1
L1
V
OUT 1
OUT 2
INH
V
V
= +3V
= C = 33pF
S1
L2
S
D
2
0V
= +3V
S2
R
C
R
C
L1
L2
L2
L1
50%
50%
LOGIC
INPUT
OUT 1
OUT 2
0V
SWITCH
V-
-15V
OUTPUTS
GND
50%
0V
50%
SWITCH TYPE
V
INH
t
t
OPEN
OPEN
HI-303
5V
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE DELAY (t
FIGURE 3A. TEST CIRCUIT
)
OPEN
Typical Performance Curves
80
80
o
= 25 C
D
C
T
V+ = +15V, V- = -15V
A
60
40
20
0
60
o
125 C
o
25 C
B
A
40
20
0
o
-55 C
A V+ = +15V, V- = -15V
B V+ = +10V, V- = -10V
C V+ = +7.5V, V- = -7.5V
D V+ = +5V, V- = -5V
-15
-10
-5
0
5
10
15
-15
-10
-5
0
5
10
15
DRAIN VOLTAGE (V)
DRAIN VOLTAGE (V)
FIGURE 5. r
DS(ON)
vs V
D
FIGURE 4. r
vs V
D
DS(ON)
FN3125.10
November 17, 2004
6
HI-303
Typical Performance Curves (Continued)
100
80
60
40
20
0
100
V+ = +15V, V- = -15V
V+ = +15V, V- = -15V
= 30pF, V = 1V
RMS
o
C
LOAD
S
T
= 25 C, V = 15V, R = 2K
A
S
L
R
= 100Ω
L
10
1.0
0.1
R
= 1kΩ
L
5
6
7
8
1
10
100
1K
10K
100K
1M
10
10
10
10
FREQUENCY (Hz)
LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz)
FIGURE 7. OFF ISOLATION vs FREQUENCY
FIGURE 6. DEVICE POWER DISSIPATION vs SWITCHING
FREQUENCY (SINGLE LOGIC INPUT)
10.0
1.0
10.0
V+ = +15V, V- = -15V
V+ = +15V, V- = -15V
| V | = | V | = 14V
D
S
1.0
0.1
0.1
0.01
0.01
25
75
125
o
25
75
125
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 9. I
D(ON)
vs TEMPERATURE*
FIGURE 8. I
OR I
vs TEMPERATURE*
D(OFF)
S(OFF)
* The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero
depending on the analog voltage and temperature, and will vary greatly from unit to unit.
16
60
12
50
8
40
TRANSITION (INDETERMINATE
DUE TO ACTIVE INPUT)
4
30
20
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
DRAIN VOLTAGE (V)
FIGURE 11. DIGITAL INPUT CAPACITANCE vs INPUT
VOLTAGE
FIGURE 10. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE
FN3125.10
7
November 17, 2004
HI-303
Typical Performance Curves (Continued)
300
o
V+ = +15V, T = 25 C
V+ = +15V, V- = -15V
A
V
= 4V, V = 0V
V
= 4.0V, V = 0V
INL
INH
INL
INH
300
200
100
t
ON
t
ON
200
100
t
OFF
t
OFF
0
5
10
15
-55
-35
-15
5
25
45
65
85
105 125
o
NEGATIVE SUPPLY (V)
TEMPERATURE ( C)
FIGURE 13. SWITCHING TIME vs NEGATIVE SUPPLY
VOLTAGE
FIGURE 12. SWITCHING TIME vs TEMPERATURE
1.8
7
o
o
V- = -15V, T = 25 C
A
V- = -15V, T = 25 C
A
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 4.0V, V
= 0V
INL
INH
6
5
4
3
2
1
0
t
ON
t
OFF
t
OPEN
ONLY
0
5
10
15
0
5
10
15
POSITIVE SUPPLY VOLTAGE (V)
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 14. SWITCHING TIME AND BREAK-BEFORE-MAKE
TIME vs POSITIVE SUPPLY VOLTAGE
FIGURE 15. INPUT SWITCHING THRESHOLD vs POSITIVE
SUPPLY VOLTAGE
FN3125.10
November 17, 2004
8
HI-303
Dual-In-Line Plastic Packages (PDIP)
N
E14.3 (JEDEC MS-001-AA ISSUE D)
E1
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INDEX
AREA
1 2
3
N/2
INCHES
MILLIMETERS
-B-
-C-
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
BASE
PLANE
A2
A
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
SEATING
PLANE
-
L
C
L
B1
C
8
D1
B1
eA
A1
A
D1
-
e
eC
C
B
D
5
eB
0.010 (0.25) M
C
B S
D1
E
5
NOTES:
0.325
0.280
8.25
7.11
6
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
E1
e
5
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
e
e
6
A
B
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
-
0.430
0.150
-
10.92
3.81
7
4. Dimensions A, A1 and L are measured with the package seated in
L
0.115
2.93
4
9
JEDEC seating plane gauge GS-3.
N
14
14
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
Rev. 0 12/93
e
6. E and
dicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be perpen-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1maximumdimensionsdonotincludedambarprotrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
FN3125.10
9
November 17, 2004
HI-303
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
FN3125.10
10
November 17, 2004
HI-303
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
µ
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C A M B S
L
6
N
α
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3125.10
11
November 17, 2004
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