HIP0061AS1 [INTERSIL]
60V, 3.5A, 3-Transistor Common Source ESD Protected Power MOSFET Array; 60V ， 3.5A ，三晶体管共源ESD保护功率MOSFET阵列
| 型号： | HIP0061AS1 |
| 厂家： | 
Intersil |
| 描述： | 60V, 3.5A, 3-Transistor Common Source ESD Protected Power MOSFET Array |
| 文件： | 总9页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIP0061
60V, 3.5A, 3-Transistor Common Source
ESD Protected Power MOSFET Array
December 1997
Features
Description
• Three 3.5A Power MOS N-Channel Transistors
• Output Voltage to 60V
The HIP0061 is a power MOSFET array that consists of
three matched N-Channel enhancement mode MOS transis-
tors connected in a common source configuration. The
advanced Harris PASIC2 process technology used in this
product utilizes efficient geometries that provides outstand-
ing device performance and ruggedness.
• r
DS(ON)
. . . . . 0.225Ω Max Per Transistor at V = 10V
GS
• Pulsed Current . . . . . . . . . . . . . . . .10A Each Transistor
• Avalanche Energy . . . . . . . . . . 100mJ Each Transistor
• Grounded Tab Eliminates Heat Sink Isolation
The HIP0061 is designed to integrate three power devices in
one chip thus providing board layout area and heat sink sav-
ings for applications such as Motor Controls, Lamps,
Solenoids and Resistive Loads.
Applications
• Automotive
Symbol
• Appliance
• Industrial Control
• Robotics
DRAIN1
2
DRAIN2
5
DRAIN3
7
• Relay, Solenoid, Lamp Drivers
GATE2
3
GATE1
1
GATE3
6
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
4
HIP0061AS1
HIP0061AS2
-40 to 125 7 Ld Staggered
Vertical SIP
Z7.05C
SOURCE, TAB
-40 to 125 7 Ld Gullwing SIP Z7.05B
Pinouts
HIP0061AS1
(SIP - VERTICAL)
TOP VIEW
HIP0061AS2
(SIP - GULLWING)
TOP VIEW
7
6
5
4
3
2
1
DRAIN3
GATE3
DRAIN2
SOURCE
GATE2
DRAIN1
GATE 1
7
6
5
4
3
2
1
DRAIN3
GATE3
DRAIN2
SOURCE
GATE2
DRAIN1
GATE 1
TAB
TAB
TAB (SOURCE) INTERNALLY CONNECTED TO PIN 4
TAB (SOURCE) INTERNALLY CONNECTED TO PIN 4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3982.3
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HIP0061
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
o
o
Drain to Source Voltage, V
DS
Thermal Resistance (Typical, Note 4)
θ
( C/W)
θ
( C/W)
JA
JC
(Over Operating Junction and Case Temperature Range) . . . . 60V
SIP-Vertical Package . . . . . . . . . . . . .
SIP-Gullwing Package . . . . . . . . . . . .
55
55
3
3
Drain to Gate Voltage, V
Gate to Source Voltage, V
GS
. . . . . . . . . . . . . . . . . . . . . . . . . . . 60V
. . . . . . . . . . . . . . . . . . . . . . .-15, +20V
DGR
o
Maximum Junction Temperature, T . . . . . . . . . . . . . . . . . . . . 150 C
J
o
o
Pulsed Drain Current, I , Each Output,
DM
Maximum Storage Temperature Range, T
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
. . . . -55 C to 150 C
STG
o
All Outputs on at V
GS
= 10V (Notes 1, 2). . . . . . . . . . . . . . . . 10A
Continuous Source to Drain Diode Current, I
SD
at V
GS
= 10V (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5A
Die Characteristics
Continuous Drain Current, I , Each Output,
DS
Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . V- (Source, Tab)
All Outputs on at V
GS
= 10V (Note 2) . . . . . . . . . . . . . . . . . .3.5A
Single Pulse Avalanche Energy, E (Note 3) . . . . . . . . . . . . 100mJ
AS
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 125 C
Drain to Source On-State Voltage Range . . . . . . . . . . . . 5V to 10V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Pulse width limited by maximum junction temperature.
2. Drain current limited by package construction.
o
3. V
= 25V, Start T = 25 C, L = 15mH, R
GS
= 50Ω, I = 3.5A. See Figures 1, 2, 12, and 13.
PEAK
DD
J
4. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications
PARAMETERS
T
= 25 C, Unless Otherwise Specified
C
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
o
Drain to Source Breakdown Voltage
BV
DSS
I
= 100µA, V
GS
= 0V
T
= -40 C to
60
-
-
V
D
C
o
125 C
o
T
= 25 C
-
70
-
V
C
Gate Threshold Voltage
V
V
= V , I = 250µA
1.8
2.3
2.7
1
V
GS(TH)
GS
DS
D
o
Zero Gate Voltage Drain Current
I
V
V
= 60V
= 0V
T
T
= 25 C
-
-
-
-
-
-
µA
µA
nA
DSS
DS
GS
C
C
o
= 125 C
10
100
Forward Gate Current, Drain Short
Circuited to Source
I
V
V
= 0V, V
= 20V
GSSF
DS
DS
GS
GS
Reverse Gate Current, Drain Short
Circuited to Source
I
= 0V, V
= -15V
-
-
-100
nA
GSSR
o
Drain to Source On Resistance (Note 5)
r
r
V
V
V
V
= 10V, I = 3.5A
T
T
T
T
T
= 25 C
-
-
-
-
-
-
-
-
-
-
-
-
-
0.215
0.365
0.275
0.465
95
0.265
Ω
Ω
DS(ON)
GS
GS
GS
GS
D
C
C
C
C
C
o
= 10V, I = 3.5A
= 125 C
0.425
D
o
= 5V, I = 2A
= 25 C
0.320
Ω
D
o
= 5V, I = 2A
= 125 C
0.5
Ω
D
o
Drain to Source On Resistance Matching
Forward Transconductance (Note 5)
Turn-On Delay Time (Note 6)
Rise Time (Note 6)
V
= 10V, I = 3.5A
= 25 C
-
%
DS(ON)
GS
D
g
V
= 10V, I = 1A
2.5
-
-
S
fs
DS
D
t
V
= 30V, R = 15Ω,
10
ns
ns
ns
ns
nC
nC
nC
d(ON)
DD
L
V
= +10V, I = 2A, R = 50Ω
GS
D
G
t
25
-
r
See Figure 14
Turn-Off Delay Time (Note 6)
Fall Time (Note 6)
t
18
-
d(OFF)
t
12
-
f
Total Gate Charge (Note 6)
Gate-Source Charge (Note 6)
Gate-Drain Charge (Note 6)
Q
V
= 50V, V
= 10V, I = 2A
8.0
9.5
1.0
4.0
g(TOT)
DS
GS
D
See Figures 16, 17
Q
0.7
gs
gd
Q
3.5
2
HIP0061
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified (Continued)
C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Short-Circuit Input Capacitance,
Common Source
C
V
= 25V, V
GS
= 0V
-
142
-
pF
ISS
DS
f = 1MHz
Short-Circuit Output Capacitance,
Common Source
C
C
-
-
107
24
-
-
pF
pF
OSS
RSS
Short-Circuit Reverse Transfer
Capacitance, Common Source
Source-Drain Diode Ratings and Specifications
PARAMETERS
Diode Forward Voltage (Note 5)
Reverse Recovery Time
NOTES:
SYMBOL
TEST CONDITIONS
= 2A, V = 0V
MIN
TYP
MAX
UNITS
V
V
I
I
-
-
0.9
50
1.1
-
SD
SD
GS
= 2A, dI /dt = 100A/µs
t
ns
rr
SD
SD
5. Pulse test: Pulse width ≤ 300µs, duty cycle ≤ 2%.
6. Independent of operating temperature.
Typical Performance Curves
10
10µs
10
10µs
100µs
100µs
1ms
10ms
100µs
100ms
DC
1
1
OPERATION IN THIS
AREA MAY BE
1ms
OPERATION IN THIS
AREA MAY BE
10ms
100ms
DC
LIMITED BY r
DS(ON)
LIMITED BY r
DS(ON)
o
T
T
= 25 C
o
C
J
T
T
= 105 C
C
J
= MAX RATED
= MAX RATED
0.1
0.1
10
, DRAIN VOLTAGE (V)
100
1
1
10
100
V
o
DS
V
, DRAIN TO SOURCE VOLTAGE (V)
o
DS
FIGURE 1B. 105 C SAFE-OPERATING AREA CURVE
FIGURE 1A. 25 C SAFE-OPERATING AREA CURVE
50
10
o
STARTING T = 25 C
J
o
STARTING T = 125 C
J
10µs
10
5
1
100µs
OPERATION IN THIS
AREA MAY BE
1ms
LIMITED BY r
DS(ON)
10ms
100ms
DC
o
T
T
= 125 C
C
J
= MAX RATED
0.1
1
1
10
100
0.001
0.01
0.1
1.0
V
, DRAIN TO SOURCE VOLTAGE (V)
t
, TIME IN AVALANCHE (ms)
DS
AV
o
FIGURE 1C. 125 C SAFE-OPERATING AREA CURVE
FIGURE 2. UNCLAMPED INDUCTIVE-SWITCHING
3
HIP0061
Typical Performance Curves (Continued)
10.0
20
15
10
5
V
= 10V
= 8V
= 6V
GS
o
V
= 15V
o
DS
25 C
V
-40 C
GS
V
= 5V
= 4V
GS
V
o
GS
125 C
7.5
5.0
2.5
0
V
GS
o
PULSE DURATION = 300µs, T = 25 C
C
0
0
10
0
2
4
6
8
10
2
4
6
8
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
V
, GATE TO SOURCE VOLTAGE (V)
GS
FIGURE 3. TYPICAL SATURATION CHARACTERISTICS
FIGURE 4. TYPICAL TRANSFER CHARACTERISTICS
2.5
1.2
1.1
1.0
0.9
0.8
PULSE DURATION = 300µs, V
GS
= 10V, I = 3.5A
D
I
= 100µA
D
2.0
1.5
1.0
0.5
0
-75
-25
25
75
125
175
-75
-25
25
75
125
175
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 5. NORMALIZED r
vs JUNCTION TEMPERATURE
FIGURE 6. NORMALIZED BV
DSS
vs JUNCTION TEMPERATURE
DS(ON)
2.0
1.5
1.0
12
V
= V , I = 250µA
DS
GS
D
V
V
V
= 50V
= 30V
= 20V
DS
DS
DS
8
4
0
0.5
0
o
I
= 2.0A, T = 25 C
C
D
-75
-25
25
75
125
175
0
2
4
6
8
10
o
T , JUNCTION TEMPERATURE ( C)
Q, GATE CHARGE (nC)
J
FIGURE 7. NORMALIZED V
GS(TH)
vs JUNCTION TEMPERATURE
FIGURE 8. GATE-SOURCE VOLTAGE vs GATE CHARGE
4
HIP0061
Typical Performance Curves (Continued)
750
5
4
3
o
V
= 0V, f = 1MHz, T = 25 C
C
GS
600
450
300
150
0
V
= 10V
= 5V
GS
V
GS
C
C
C
ISS
2
1
0
OSS
RSS
25
50
75
100
125
150
0
5
10
15
20
25
o
V
, DRAIN TO SOURCE VOLTAGE (V)
T , CASE TEMPERATURE ( C)
DS
C
FIGURE 9. TYPICAL CAPACITANCE vs VOLTAGE
FIGURE 10. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10
1
o
T
= 25 C
C
D = 1.0
0.5
0.2
0.1
0.1
0.05
0.02
0.01
NOTES:
1. DUTY FACTOR, D = t /t
1
2
) +T
SINGLE PULSE
2. PEAK T = P
x (Z
J
DM
JC
C
θ
-6
-5
-4
-3
10
-2
-1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
Test Circuits and Waveforms
t
t
AV
P
10 V
0
V
DS
V
GS
L
I
AS
R
+
-
G
DUT
V
DD
V
GS
I
D
0
BV
DSS
t
P
I
0V
D
V
DS
0.01Ω
0
FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 13. UNCLAMPED ENERGY WAVEFORMS
5
HIP0061
Test Circuits and Waveforms
t
t
ON
V
OFF
t
d(OFF)
DD
t
d(ON)
t
t
f
r
R
L
V
DS
90%
90%
V
DS
V
GS
10%
10%
DUT
0V
90%
50%
R
GS
50%
V
GS
PULSE WIDTH
10%
FIGURE 15. RESISTIVE SWITCHING WAVEFORMS
FIGURE 14. RESISTIVE SWITCHING TEST CIRCUIT
+V
DS
CURRENT
Q
g
REGULATOR
SAME TYPE
AS DUT
10V
+
-
25kΩ
0.2µF
10V
BATTERY
0.1µF
Q
Q
gs
gd
V
G
DUT
I
GS
0
CHARGE
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. BASIC GATE CHARGE WAVEFORM
6
HIP0061
PSPICE Model Listing
Device Model Netlist for the HIP0061 Power MOSFET Array
*Rev: 6/12/95
.SUBCKT HIP0061 1 2 3 4 5 6 7
X1 8 1 11 4 HIP0061_1
LS1 2 8 7.5n
X2 9 3 11 4 HIP0061_1
LS2 5 9 7.5n
X3 10 6 11 4 HIP0061_1
LS3 7 10 7.5n
LS4 4 11 7.5n
.ENDS
.SUBCKT HIP0061_1 3 2 11 9
MOS1
JFET
D1
4
2
1 1 NMOS1
13 1 4 J1
5
6
D1
DBODY
1
13 D2
DBREAK
DSUB
3
7
D3
9
13 D4
DESD1
2 12 D5
DESD2 15 12 D5
VBREAK DC 90
750P
13 45P
1100P
7
1
C21
C23
C24
2
2
2
1
4
RDRAIN 13 14 9.0e-02
LDRAIN 14 3 7.5n
RSOURCE 1 15 17.5e-03
LSOURCE 15 11 7.5n
FDSCHRG 4
E41 15 4 1 1.0
DC 10.0
15 DC 0.0
2
VMEAS 1.0
5
VPINCH
VMEAS
6
8
8
.MODEL NMOS1 NMOS LEVEL=3 (VTO=2.75 TOX=5e-08
KP=3.150e-03 PHI=0.65 GAMMA=2.55
+ VMAX=6.42e+07 NSUB=4.33e+16 THETA=0.60973
ETA=0.0015 KAPPA=1.275
+ L=1u W=3050u)
.MODEL J1 NJF (VTO=-15.0 BETA=10.736
LAMBDA=1.15e-02 PB=0.5848 IS=+1.0e-13
+ RD=3.53e-02 ALPHA=0.2)
.MODEL D1 D (IS=1.0e-15 N=0.03 RS=1.0)
.MODEL D2 D (IS=3.0e-13 RS=2.5e-03 TT=20N
CJO=350e-12)
.MODEL D3 D (IS=1.0e-13 N=1.0 RS=2.0)
.MODEL D4 D (IS=1.0e-13 RS=2.0e-03 CJO=80e-12)
.MODEL D5 D (IS=1.0e-15 RS=1.0e-03 CJO=2.5e-12)
.ENDS
NOTE: For further discussion of the PSPICE PowerFET macromodel consult Spicing-Up SPICE II Software for Power MOSFET Modeling,
Harris Application Note AN8610.
7
HIP0061
Single-In-Line Plastic Packages (SIP)
Z7.05B
-A-
E
A
0.006
(0.15)
7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE SURFACE MOUNT
“GULLWING” LEAD FORM
-B-
C2
INCHES
MIN
MILLIMETERS
L2
SYMBOL
MAX
0.180
0.055
0.370
0.405
-
MIN
4.32
1.22
8.89
10.04
7.88
7.88
13.95
1.72
1.15
MAX
4.57
1.39
9.39
10.28
-
NOTES
A
C2
D
0.170
0.048
0.350
0.395
0.310
0.310
0.549
0.068
0.045
-
HEATSLUG
PLANE
D
5
-C-
L
0.00 - 0.0098
(0.00 - 0.25)
-
E
-
L1
PIN
#1
D1
E1
L
-
c
o
-
-
-
o
0 - 8
e
0.569
0.088
0.055
14.45
2.24
1.40
-
b
L1
L2
L3
b
-
0.004
(0.10)
0.010 (0.25) M
B A M C M
-
L3
0.030 BSC
0.76 BSC
4
0.450
(11.43)
0.028
0.018
0.034
0.024
0.71
0.46
0.86
0.60
5, 6, 7
E1
MIN
c
5
-
e
0.050 BSC
1.27 BSC
0.350
(8.89)
MIN
D1
Rev. 2 12/95
NOTES:
0.609
(15.46)
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-169AC, Issue A.
2. Controlling dimension: Inch.
BACK VIEW
3. Dimensioning and tolerance per ANSI Y14.5M-1982.
4. Gauge plane L3 is parallel to heatslug plane.
5. Dimensions include lead finish.
0.129
(3.27)
TYP
0.030
(0.76)
TYP
e
6. Leads are not allowed above the datum -B- .
7. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed the
maximum “b” by more than 0.003’’ (0.08mm).
LAND PATTERN
8
HIP0061
Single-In-Line Plastic Packages (SIP)
Z7.05C
0.006 (0.15)
7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE
STAGGERED VERTICAL LEAD FORM
A
INCHES
MIN
MILLIMETERS
D
SYMBOL
MAX
0.180
0.034
0.024
0.405
0.202
0.605
0.370
MIN
4.32
MAX
4.57
NOTES
-B-
ØP
A
B
0.170
0.028
0.018
0.395
0.198
0.595
0.350
-
D1
F
0.71
0.86
3, 4
E2
C
0.46
0.60
3
-
D
10.04
5.03
10.28
5.13
HEADER
BOTTOM
E
D1
E
-
15.11
8.89
15.37
9.39
-
L1
E1
E1
E2
e
-
0.110 BSC
2.79 BSC
0.050 BSC
0.200 BSC
0.169 BSC
0.300 BSC
1.27 BSC
5.08 BSC
4.29 BSC
7.62 BSC
-
L
e1
e2
e3
F
-
-A-
e
-
B
e3
-
e1
e2
M
0.048
0.055
0.176
0.620
0.152
1.22
1.39
4.47
3
C
7 PLACES
0.010 (0.25)
ALL LEADS
0.024 (0.61)
L
0.150
0.600
0.147
3.81
15.24
3.73
-
A
B
M
M
A
L1
ØP
15.74
3.86
-
3
Rev. 0 6/95
NOTES:
1. Controlling dimension: INCH.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimensions include lead finish.
4. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall not cause lead width to exceed maxi-
mum “B” by more than 0.003 inches (0.08mm).
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
9
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