HIP2100 [INTERSIL]
100V/2A Peak, Low Cost, High Frequency Half Bridge Driver; 100V / 2A峰值，低成本，高频率半桥驱动器
| 型号： | HIP2100 |
| 厂家： | 
Intersil |
| 描述： | 100V/2A Peak, Low Cost, High Frequency Half Bridge Driver |
| 文件： | 总7页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIP2100
Data Sheet
October 1998
File Number 4022.2
100V/2A Peak, Low Cost, High Frequency
Half Bridge Driver
Features
• Drives N-Channel MOSFET Half Bridge
• Space Saving SO8 Package
The HIP2100 is a high frequency, 100V Half Bridge
N-Channel MOSFET driver IC, available in 8 lead plastic
SOIC. The low-side and high-side gate drivers are
independently controlled and matched to 8ns. This gives the
user maximum flexibility in dead-time selection and driver
protocol. Undervoltage protection on both the low-side and
high-side supplies force the outputs low. An on-chip diode
eliminates the discrete diode required with other driver ICs.
A new level-shifter topology yields the low-power benefits of
pulsed operation with the safety of DC operation. Unlike
some competitors, the high-side output returns to its correct
state after a momentary undervoltage of the high-side
supply.
• Bootstrap Supply Max Voltage to 116VDC
• On-Chip 1Ω Bootstrap Diode
• Fast Propagation Times Needed for Multi-MHz Circuits
• Drives 1000pF Load at 1MHz with Rise and Fall Times of
Typically 10ns
• CMOS Input Thresholds for Improved Noise Immunity
• Independent Inputs for Non-Half Bridge Topologies
• No Start-Up Problems
• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground, or HS Slewing at High dv/dt
• Low Power Consumption
• Wide Supply Range
Ordering Information
TEMP.
o
• Supply Undervoltage Protection
• 3Ω Output Resistance
PART NUMBER
RANGE ( C)
PACKAGE
PKG. NO.
o
o
HIP2100IB
-40 C to 85 C 8 Ld SOIC (N)
M8.15
Applications
• Telecom Half Bridge Power Supplies
• Avionic DC-DC Converters
• Two-Switch Forward Converters
• Active Clamp Forward Converters
Pinout
Application Block Diagram
+100V
HIP2100 (SOIC)
TOP VIEW
+12V
SECONDARY
CIRCUIT
1
2
3
4
8
7
6
5
LO
V
V
DD
HB
HO
HS
SS
LI
V
DD
HI
HB
DRIVE
HI
HO
HS
LO
HI
LI
PWM
CONTROLLER
DRIVE
LO
REFERENCE
HIP2100
AND
ISOLATION
V
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HIP2100
Functional Block Diagram
2
3
HB
HO
1
5
V
UNDER
VOLTAGE
DD
HI
LEVEL SHIFT
DRIVER
4
HS
UNDER
VOLTAGE
8
LO
DRIVER
6
7
LI
V
SS
Other Applications
+48V
+12V
SECONDARY
CIRCUIT
HIP
2100
PWM
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
HIP
2100
PWM
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP
2
HIP2100
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
LI and HI Voltages . . . . . . . . . . . . . . . . . . . . . . . . -3V to V
Voltage on LO . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
Voltage on HO . . . . . . . . . . . . . . . . . . . . . . V
Voltage on HS (Continuous) . . . . . . . . . . . . . . . . . . . . . -1V to 110V
V
-V
. . . . . . . . . . . . . . . . . . -0.3V to 18V
Thermal Resistance
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 C/W
SOIC in Thermal Conductive Media. . . . . . . . . . . . . . . . . 70 C/W
HS Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V/ns
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65 C to 150 C
Junction Temperature Range. . . . . . . . . . . . . . . . . . -55 C to 150 C
Lead Temperature (Soldering 10s - Lead Tips Only). . . . . . . 300 C
Maximum Power Dissipation at +25 C in Free Air. . . . . . . . 780mW
θ
θ
DD, HB HS
JA
JC
N/A
o
+0.3V
+0.3V
+0.3V
DD
DD
HB
o
-0.3V to V
HS
o
o
o
o
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V
o
Average Current in V
to HB diode . . . . . . . . . . . . . . . . . . . 100mA
DD
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV)
NOTE: All Voltages Relative to Pin 7, V Unless Otherwise Specified
o
SS
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
Recommended Operating Conditions
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . +9V to +16.5V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . (Repetitive Transient) -5V to 105V
DD
Voltage on HB V
HS
+8V to V
+16.5V and V
-1V to V
+100V
DD
HS
DD
Electrical Specifications
V
= V
= 12V, V = V = 0V, No Load on LO or HO, Unless Otherwise Specified
HB SS HS
DD
o
T = - 40 C
J
TO 125 C
o
o
T
= 25 C
J
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
MIN
MAX UNITS
SUPPLY CURRENTS
V
V
Quiescent Current
Operating Current
I
LI = HI = 0V
f = 500kHz
LI = HI = 0V
f = 500kHz
-
-
-
-
-
-
0.1
1.5
0.15
2.5
0.15
2.5
1
-
-
-
-
-
-
0.2
3
mA
mA
mA
mA
µA
DD
DD
DD
I
I
DDO
Total HB Quiescent Current
Total HB Operating Current
I
0.1
0.2
3
HB
HBO
1.5
HB to V Current, Quiescent
SS
I
V
= V
HB
= 116.5V
0.05
0.7
10
-
HBS
HS
HB to V Current, Operating
SS
I
f = 500kHz
-
mA
HBSO
INPUT PINS
Low Level Input Voltage Threshold
V
4
-
5.4
5.8
0.4
200
-
7
-
3
-
8
V
V
IL
High Level Input Voltage Threshold
Input Voltage Hysteresis
V
-
-
IH
V
-
-
V
IHYS
Input Pulldown Resistance
R
-
-
100
500
kΩ
I
UNDER VOLTAGE PROTECTION
V
V
Rising Threshold
V
V
V
V
7
-
7.3
0.5
6.9
0.4
7.8
-
6.5
8
-
V
V
V
V
DD
DD
DDR
DDH
HBR
HBH
Threshold Hysteresis
-
6
-
HB Rising Threshold
6.5
-
7.5
-
8
-
HB Threshold Hysteresis
BOOT STRAP DIODE
Low-Current Forward Voltage
High-Current Forward Voltage
Dynamic Resistance
V
I
I
I
= 100µA
-
-
-
0.45
0.7
0.55
0.8
1
-
-
-
0.7
1
V
V
Ω
DL
VDD-HB
VDD-HB
VDD-HB
V
= 100mA
= 100mA
DH
R
0.8
1.5
D
LO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
V
I
I
= 100mA
-
-
-
-
0.25
0.25
2
0.3
0.3
-
-
-
-
-
0.4
0.4
-
V
V
A
A
OLL
LO
LO
V
= -100mA, V
OHL
= V -V
DD LO
OHL
I
V
V
= 0V
OHL
LO
LO
Peak Pulldown Current
HO GATE DRIVER
I
= 12V
2
-
-
OLL
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
V
I
I
= 100mA
-
-
-
-
0.25
0.25
2
0.3
0.3
-
-
-
-
-
0.4
0.4
-
V
V
A
A
OLH
HO
HO
V
= -100mA, V
OHH
= V -V
HB HO
OHH
I
V
V
= 0V
OHH
HO
HO
Peak Pulldown Current
I
= 12V
2
-
-
OLH
3
HIP2100
Switching Specifications
V
= V
= 12V, V = V = 0V, No Load on LO or HO, Unless Otherwise Specified
SS HS
DD
HB
o
T
= - 40 C
J
o
o
T
= 25 C
TO 125 C
J
TEST
PARAMETERS
SYMBOL
CONDITIONS
MIN TYP MAX MIN MAX UNITS
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
Delay Matching: Lower Turn-On and Upper Turn-Off
Delay Matching: Lower Turn-Off and Upper Turn-On
Either Output Rise/Fall Time
t
-
-
-
-
-
-
-
-
-
-
-
-
20
20
20
20
2
35
35
35
35
8
-
-
-
-
-
-
-
-
-
-
-
-
45
45
45
45
10
10
-
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
LPHL
t
HPHL
t
LPLH
HPLH
t
t
MON
t
2
8
MOFF
t
t
C = 1000pF
10
0.5
20
10
-
-
RC, FC
L
Either Output Rise/Fall Time (3V to 9V)
t
t
C = 0.1µF
0.6
-
0.8
-
R, F
L
Either Output Rise Time Driving DMOS
t
C = IRFR120
L
RD
Either Output Fall Time Driving DMOS
t
C = IRFR120
L
-
-
FD
Minimum Input Pulse Width that Changes the Output
Bootstrap Diode Turn-On or Turn-Off Time
t
-
50
-
PW
t
10
-
BS
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
2
V
Positive Supply to lower gate drivers. De-couple this pin to V (Pin 7). Bootstrap diode connected to HB (pin 2).
SS
DD
HB
High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to
this pin. Bootstrap diode is on-chip.
3
4
HO
HS
High-Side Output. Connect to gate of High-Side power MOSFET.
High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap
capacitor to this pin.
5
6
7
8
HI
LI
High-Side input.
Low-Side input.
V
Chip negative supply, generally will be ground.
Low-Side Output. Connect to gate of Low-Side power MOSFET.
SS
LO
Timing Diagrams
LI
HI
HI,
LI
t
t
,
t
t
,
HPLH
LO
HO
HPHL
LPHL
LPLH
t
t
MOFF
MON
HO,
LO
FIGURE 3.
FIGURE 4.
4
HIP2100
Typical Performance Curves
10
10
o
T = 150 C
1
1
o
T = -40 C
o
T = 125 C
o
T = 25 C
o
T = 150 C
0.1
0.1
o
T = 125 C
o
T = 25 C
o
T = -40 C
0.01
0.01
10
100
1000
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
FIGURE 5. OPERATING CURRENT vs FREQUENCY
FIGURE 6. LEVEL SHIFTER CURRENT vs FREQUENCY
500
500
400
300
200
100
V
= V
= 9V
V
= V
= 9V
DD
HB
DD
HB
V
= V
= 12V
= 14V
V
= V
= 12V
= 14V
400
300
200
100
HB
HB
DD
DD
HB
HB
DD
DD
V
= V
V
= V
V
= V
= 16.5V
V
= V
= 16.5V
DD
HB
DD
HB
-50
0
50
TEMPERATURE ( C)
100
150
-50
0
50
TEMPERATURE ( C)
100
150
o
o
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
0.54
0.5
7.6
7.4
V
DDH
V
V
DDR
HBR
0.46
0.42
0.38
0.34
0.3
7.2
7.0
6.8
6.6
V
HBH
-50
0
50
100
150
-50
0
50
TEMPERATURE ( C)
100
150
o
o
TEMPERATURE ( C)
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
5
HIP2100
Typical Performance Curves (Continued)
2.5
2.0
1.5
1.0
0.5
0
30
t
t
HPHL
HPLH
t
LPHL
25
20
15
t
LPLH
-50
0
50
TEMPERATURE ( C)
100
150
0
2
4
6
8
10
12
o
V
, V (V)
HO LO
FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE
FIGURE 12. PULLUP CURRENT vs OUTPUT VOLTAGE
1
0.1
2.5
2.0
1.5
1.0
0.5
0
0.01
0.001
-4
1•10
-5
1•10
-6
1•10
0
2
4
6
8
10
12
0.3
0.4
0.5
0.6
0.7
0.8
V
, V
(V)
FORWARD VOLTAGE (V)
LO HO
FIGURE 13. PULLDOWN CURRENT vs OUTPUT VOLTAGE
FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS
60
50
I
vs V
HB
HB
40
30
20
10
0
I
vs V
DD
DD
0
5
10
(V)
15
V
, V
DD HB
FIGURE 15. BIAS CURRENT vs VOLTAGE
6
HIP2100
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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7
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