HIP5061DS_技术文档

HIP5061

7A, High Efﬁciency Current

Mode Controlled PWM Regulator

April 1994

Features

Description

• Single Chip Current Mode Control IC

• 60V, On-Chip DMOS Power Transistor

• Thermal Protection

The HIP5061 is a complete power control IC, incorporating

both the high power DMOS transistor, CMOS logic and low

level analog circuitry on the same Intelligent Power IC. The

standard “Boost”, “Buck-Boost”, “Cuk”, “Forward”, “Flyback”

and the “SEPIC” (Single-Ended Primary Inductance Con-

verter) power supply topologies may be implemented with

this single control IC.

• Over-Current Protection

• 250kHz Operation

Over-temperature and rapid short-circuit recovery circuitry is

incorporated within the IC. These protection circuits disable

the drive to the power transistor to protect the transistor and

insure rapid restarting of the supply after the short circuit is

removed.

• Output Rise and Fall Times - 10ns

• On-Chip Reference Voltage - 5.1V

• Slope Compensation

• V_DDClamp Allows 10.8V to 60V Supply

As a result of the power DMOS transistors current (7A at 30%

duty cycle, 5A DC) and 60V capability, supplies with output

power over 50W are possible.

• Supply Current Does Not Increase When Power

Device is On

Applications

Ordering Information

• Distributed / Board Mounted Power Supplies

• DC - DC Converter Modules

• Voltage Inverters

PART

NUMBER

TEMPERATURE

RANGE

PACKAGE

o

HIP5061DS

0 C to +85 C

7 Lead Staggered “Gullwing” SIP

• Small Uninterruptable Power Supplies

• Cascode Switching for Off Line SMPS

Simpliﬁed Functional Diagram

Pinout

HIP5061 (SIP)

V_IN

TOP VIEW

V_OUT

PIN 7 V_DD

PIN 6 V_G

PIN 5 DRAIN

PIN 4 SOURCE

PIN 3 FB

PIN 2 V_C

PIN 1 GND

V_DD

V_DDCLAMP

V_G

DRAIN

HIP5061

CLOCK

DO NOT

USE

SOURCE

(TAB)

GATE

DRIVER

CONTROL

LOGIC

SOURCE

(TAB)

V_C

FB

OVER

TEMP

AMP

V/I

2.5V

UNDER

VOLTAGE

SLOPE

COMPENSATION

5.1V

REFERENCE

GND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3390.2

7-53

Speciﬁcations HIP5061

Absolute Maximum Ratings (Note 1)

Thermal Information

DC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Thermal Resistance

θ

JC

2 C/W

DD

o

DC Supply Current, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .105mA

Plastic SIP Package . . . . . . . . . . . . . . . . . . . . . . . .

DD

o

DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V Maximum Package Power Dissipation at +85 C

Average DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 5A

DMOS Source Voltage, V , TAB . . . . . . . . . . . . -0.1V to 0.1V

(Depends Upon Mounting, Heat Sink and Application) . . . . . 10W

Max. Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . +105 C

o

SOURCE

DC Supply Voltage, V . . . . . . . . . . . . . . . . . . . .-0.3V to V + 0.3V

(Controlled By Thermal Shutdown Circuit)

G

DD

o

Compensation Pin Current, I

. . . . . . . . . . . . . . . . . -5mA to 35mA Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265 C

VC

Voltage at All Other Pins. . . . . . . . . . . . . . . . . . .-0.3V to V + 0.3V

DD

o

Operating Junction Temperature Range. . . . . . . . . . .0 C to +105 C

o

Storage Temperature Range . . . . . . . . . . . . . . . . . -55 C to +150 C

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 - 2KV

Single Pulse Avalanche Energy Rating, µs (Note 2) . . . EAS 100mJ

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

o

Electrical Speciﬁcations

V

= V =12V, V = 5V, V = 5.1V, SOURCE = GND = DRAIN = 0V, T = 0 C to +105 C,

DD

G

C

FB

J

Unless Otherwise Speciﬁed

SYMBOL

PARAMETER TEST CONDITIONS

MIN

TYP

MAX

UNITS

DEVICE PARAMETERS

I

Quiescent Supply Current

V

= V = 13.2V, V = 0V,

= 4V

6

12

18

mA

DD

FB

G

C

I

Operating Supply Current

Quiescent Current to Gate Driver

Operating Current to Gate Driver

Clamp Voltage

V

= V = 13.2V, V = 8.5V, V = 4V

-

24

0

31

10

2

mA

µA

mA

V

DD

G

C

FB

IV

= V = 13.2V, V = 0V

G

C

= 3V

-

1

G

C

V

I

= 100mA

13.3

5.0

14

5.1

15

5.2

DDC

DD

VC

V

Reference Voltage

= 0µA, V = V

FB

V

REF

C

AMPLIFIERS

|I

|

Input Current

V

= V

REF

-

-0.85

30

0.5

43

µA

FB

g

(V

)

V

Transconductance

/I / = 500µA, Note 3

20

mS

m

FB

VC

I

/(V - V

)

REF

VC

FB

IV

Maximum Source Current

Maximum Sink Current

Voltage Gain

V

= 4.6V

= 5.6V

-4

1

-1.8

1.8

50

-1

4

mA

dB

V

CMAX

FB

A

/I / = 500µA, Note 3

44

5.4

-

OL

VC

V

Short Circuit Recovery Compara-

tor Rising Threshold Voltage

6.6

8.9

CMAX

V

Short Circuit Recovery

Comparator Hysteresis Voltage

0.7

0

1.1

10

1.8

25

V

CHYS

IVC

V

Over-Voltage Current

V

= V = 10.8V, V = V

CMAX

mA

OVER

C

DD

G

C

CLOCK

fq

Internal Clock Frequency

210

250

290

kHz

DMOS TRANSISTOR

r_DS

Drain-Source On-State

Resistance

I

= 5A, V = V = 10.8V

-

0.15

-

0.22

0.33

Ω

(ON)

DRAIN

DD

G

o

T = +25 C

J

r_DS

Drain-Source On-State

Resistance

I

= 5A, V = V = 10.8V

(ON)

DRAIN DD G

o

T = +105 C

J

I

Drain-Source Leakage Current

V

= 60V

-

0.5

-

10

5

µA

DSS

DRAIN

I

Average Drain Short Circuit

Current

= 5V, Note 4

A

DSH

C

DRAIN Capacitance

Note 4

-

200

-

pF

DRAIN

7-54

Speciﬁcations HIP5061

o

Electrical Speciﬁcations

V

= V =12V, V = 5V, V = 5.1V, SOURCE = GND = DRAIN = 0V, T = 0 C to +105 C,

DD

G

C

FB

J

Unless Otherwise Speciﬁed (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

CURRENT CONTROLLED PWM

g (V )

∆I

/∆V

C

Note 3

1.4

2.4

2.2

2.8

3.0

3.1

A/V

V

m

C

DRAIN, PEAK

V/I

Voltage to Current Converter Ref-

erence Voltage

I

= 0.25A, Note 3

REF

DRAIN

t

Current Comparator Blanking

Time

Note 3

40

100

175

ns

BT

t

Minimum DMOS “ON” Time

Minimum DMOS “OFF” Time

Note 3

60

40

-

150

125

100

250

200

250

ns

ONMIN

t

OFFMIN

MinCI

Minimum Controllable DMOS

Peak Current

mA

MaxCI

Maximum Controllable DMOS

Peak Current

Duty Cycle = 6% to 30%, Note 3

Duty Cycle = 30% to 96%, Note 3

7

5

9.5

8

12

A

Maximum Controllable DMOS

Peak Current

CURRENT COMPENSATION RAMP

∆I/∆t

Compensation Ramp Rate

Compensation Ramp Delay

∆I

/∆Time, Note 3

-1.4

1.3

-0.85

1.5

-0.45

1.8

A/µs

µs

DRAIN, PEAK

t

Note 3

RD

START-UP

V

Rising V Threshold Voltage

V

= 4V

9.3

0.3

1.0

10.3

0.45

1.5

10.8

0.6

V

DDMIN

DDHYS

DD

FB

V

Power-On Hysteresis

V

Enable Comparator Threshold

Voltage

2.0

CEN

R

Power-Up Resistance

4V < V < 10.8V, V = 0.8V

50

500

3000

Ω

VC

DD

C

THERMAL MONITOR

o

T

Substrate Temperature for

Thermal Monitor to Trip

Note 4

105

-

145

-

C

J

o

T

Temperature Hysteresis

5

C

JHY

NOTES:

1. All Voltages relative to pin 1, GND.

o

2. V = 10V, Starting T = +25 C, L = 4mH, I

= 7A.

D

J

PEAK

3. Test is performed at wafer level only.

4. Determined by design, not a measured parameter.

TABLE 1. CONDITIONS FOR UNCLAMPED ENERGY CIRCUIT

7

1

L

I

L

+

V

(V)

(PEAK AMPS)

L (mH)

40

EAS (mJ)

550

D

HIP5061

I_L

V_D

-

10

5

7

VARY t_PTO OBTAIN

REQUIRED PEAK I_L

10

6

4TZ

120

10

12.5

0.33

0.14

18

12V

t_P

6

12

NOTE: Device Selected to Obtain Peak Current without Clocking

FIGURE 1. UNCLAMPED ENERGY TEST CIRCUIT

7-55

HIP5061

V

_CHYS, V_CMAXHysteresis - The voltage on V_Cthat causes

Deﬁnitions of Electrical Speciﬁcations

the NMOS transistor to turnoff if it had been turned on by V_C

exceeding V_CMAX. At this voltage the current out of the Voltage-

to-Current Converter is at roughly three quarters of full-scale.

Refer to the Functional Block Diagram of Figure 1 for loca-

tions of functional blocks and devices.

Device Parameters

IVC_OVER, V_COver-Voltage Current - The current drawn

through the V_Cpin after the NMOS transistor is turned on

due to excessive voltage on V_C. The NMOS transistor con-

nected to the V_Cpin draws more than enough current to

overcome the full scale source current of the Error Ampliﬁer.

I_DD, Quiescent Supply Current - Supply current with the

chip disabled. The Clock, Error Ampliﬁer, Voltage-to-Current

Converter, and Current Ramp circuits draw only quiescent

current. The supply voltage must be kept lower than the

turn-on voltage of the V_DDclamp or else the supply current

increases dramatically.

Clock

fq, Frequency - The frequency of the DC/DC converter. The

Clock actually runs faster than this value so that various con-

trol signals can be internally generated.

I_DD, Operating Supply Current - Supply current with the

chip enabled. The Error Ampliﬁer is drawing its maximum

current because V_FBis less than its reference voltage. The

voltage-to-current ampliﬁer is drawing its maximum because

V_Cis at its maximum. The ramp circuit is drawing its maxi-

mum because it is not being disabled by the DMOS transis-

tor turning off.

DMOS Transistor

r_DS(ON), “On” Resistance - Resistance from DMOS transis-

tor Drain to Source at maximum drain current and minimum

Gate Driver voltage, V_G.

IV_G, Quiescent Gate Driver Current - Gate Drivers supply

current with the IC disabled. The Gate Driver is not toggling

and so it draws only leakage current.

I_DSS, Leakage Current - Current through DMOS transistor

at the Maximum Rated Voltage.

Current Controlled PWM

IV_G, Operating Gate Driver Current - Gate Drivers supply

current with the IC enabled. The DMOS transistor drain is

loaded with a large resistor tied to 60V so that it is swinging

from 0V to 60V during each cycle.

g_m(V_C), Transconductance - The change in the DMOS tran-

sistor peak drain current divided by the change in voltage on

V_C. When analyzing DC/DC converters the DMOS transistor

and the inductor tied to the drain are sometimes modelled as

a voltage-controlled current source and this parameter is the

gain of the voltage-controlled current source.

V_DDC, V_DDClamp - V_DDvoltage at the maximum allowed

current through the V_DDClamp.

V_REF, Reference Voltage - The voltage on FB that sets the

current on V_Cto zero. This is the reference voltage for the

DC/DC converter.

V/I_REF, Current Control Threshold - The voltage on V_C

that causes the DMOS transistor to shut off at the minimum

controllable current. This voltage is greater than the Enable

Comparator Threshold (V_CEN) so that as V_Crises the IC

does not jump from the disabled state to the DMOS transis-

tor conducting a large current.

Ampliﬁers

|I_FB|, Input Current - Current through FB pin when it is at its

normal operating voltage. This current must be considered

when connecting the output of a DC/DC convertor to the FB

pin via a resistor divider.

t

_BT, Blanking Time - At the beginning of each cycle there is

a blanking time that the DMOS transistor turns-on and stays-

on no matter how high drain the current. This blanking time

permits ringing in the external parasitic capacitances and

inductances to dampen and for the charging of the reverse

bias on the rectiﬁer diode.

g_m(V_FB), Transconductance - The change in current

through the V_Cpin divided by the change in voltage on FB.

The g_mtimes the resistance between V_Cand ground gives

the voltage gain of the Error Ampliﬁer.

t

_ONMIN, Minimum DMOS Transistor “On” Time - The mini-

IV_CMAX, Maximum Source Current - The current on V_C

when FB is more than a few hundred millivolts less than

mum on-time for the DMOS transistor where small changes

in the V_Cvoltage make predictable changes in the DMOS

transistor peak current. Converters should be designed to

avoid requiring pulse widths less than the minimum on time.

V_REF

.

IV_CMAX, Maximum Sink Current - The current on V_Cwhen

FB is more than a few hundred millivolts more than V_REF

.

t

_OFFMIN, Minimum DMOS Transistor “Off” Time - The min-

imum off-time for the DMOS transistor that allows enough time

for the IC to get ready for the next cycle. Converters should be

designed to avoid requiring pulse widths so large that the mini-

mum off time is violated. (However, zero off time is allowed, that

is, the DMOS transistor can stay on from one cycle to the next.)

A_OL, Voltage Gain - Change in the voltage on V_Cdivided by

the change in voltage on FB. There is no resistive load on

V_C. This is the voltage gain of the error ampliﬁer when g_m

times load resistance is larger than this gain.

V_CMAX, V_CRising Threshold - The voltage on V_Cthat

causes the Voltage-to-Current Ampliﬁer to reach full-scale.

When V_Creaches this voltage, the V_CNMOS transistor (tran-

sistor with its drain connected to the V_Cpin in the Functional

Block Diagram of Figure 2) turns on and tries to lower the volt-

age on V_C.

MinCI, Minimum Controllable Current - When the voltage

on V_Cis below V/I_REF, the peak current for the DMOS tran-

sistor is too small for the Current Comparator to operate reli-

ably. Converters should be designed to avoid operating the

DMOS transistor at this low current.

7-56

HIP5061

MaxCI, Maximum Controllable Current - The peak current

V_CEN, Enable Comparator Threshold Voltage - The mini-

for the DMOS transistor when the Voltage-to-Current Con- mum voltage on V_Cneeded to enable the IC. The IC can be

verter is at its full scale output. The DMOS transistor current shutdown from an open-collector logic gate by pulling down

may exceed this value during the blanking time so proper the V_Cpin to GND.

precautions should be taken. This parameter is unchanged

for the ﬁrst 3/8 of the cycle and then decreases linearly with

time because of the Current Ramp becoming active.

R_VC, Power - Up Resistance - When V_DDis below V_DDMIN

,

the NMOS transistor connected to the V_Cpin is turned on to

make sure the V_Cnode is low. Thus the voltage on V_Ccan

gradually build up as will the trip current on the DMOS tran-

sistor. This is the only form of “soft start” included on the IC.

The resistance is measured between the V_Cand GND pins.

Current Compensation Ramp

∆I/∆t, Compensation Ramp Rate - At a given voltage on V_C

the DMOS transistor will turn off at some current that stays

constant for about the ﬁrst 1.5µs of the cycle. After 1.5µs, the Thermal Monitor

turnoff current starts to linearly decrease. This parameter

T_J, Rising Temperature Threshold - The IC temperature

that causes the IC to disable itself so as to prevent damage.

_RD, Compensation Ramp Delay - The time into each cycle Proper heat-sinking is required to avoid over-temperature

speciﬁes the change in the DMOS transistor turnoff current.

t

that the compensation ramp turns on. The Current Compen- conditions, especially during start-up when the DMOS tran-

sation Ramp, used for Slope Compensation, is developed by sistor may stay on for a long time if an external soft-start cir-

the Current Ramp block shown in the FUNCTIONAL BLOCK cuit is not added.

DIAGRAM of Figure 2.

T

_JHY, Temperature Hysteresis - The IC must cool down

Start-Up

this much after it is disabled by being too hot before it can

resume normal operation.

V_DDMIN, Rising V_DDThreshold Voltage - The minimum

voltage on V_DDneeded to enable the IC.

V_DDHYS, Power - On Hysteresis Voltage - The difference

between the voltage on V_DDthat enables the IC and the volt-

age that disables the IC.

V_DD

7

V_G

6

V_DD

CLAMP

RAMP RESET

RAMP ENABLE

BIAS

CIRCUITS

CURRENT

RAMP

BAND GAP

REFERENCE

REGULATOR

DRAIN

5

GND

1

V_DD

CONTROL

LOGIC

GATE

DRIVER

-

CLOCK

V_REF= 5.1V

10.3V

+

V_DDMONITOR

UNDER VOLTAGE

LOCK OUT

V_C

2

+

ENABLE

TAB

-

ERROR

AMP

DISABLE

100ns

CURRENT

MONITORING

THERMAL

MONITOR

BLANKING

1.5V

SOURCE

VOLTAGE TO

CURRENT

V_DD

FB

3

CURRENT SAMPLE

-

CONVERTER

-

ERROR

AMP

+

-

360Ω

CURRENT

COMPARE

INTERNAL LEAD

ERROR CURRENT

INDUCTANCE

2KΩ

AND RESISTANCE

+

LIGHT LOAD

COMPARATOR

SOURCE

4

5.1V

V_REF

+

SHORT

CIRCUIT

HIP5061

-

7.0V

FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF THE HIP5061

7-57

HIP5061

Pin Description

TERMINAL

NUMBER

DESIGNATION

DESCRIPTION

1

2

GND

This is the analog ground terminal of the IC.

V

The output of the transconductance ampliﬁer appears at this terminal. Input to the internal

voltage to current converter also appears at this node. Transconductance ampliﬁer gain

C

and loop response are set at this terminal. When the V terminal voltage is below the

DD

starting voltage, V

, this terminal is held low. When the voltage at this terminal

DDMIN

exceeds V

, 7V typical, implying an over-current condition, a typical 10mA current,

CMAX

I

pulls this terminal towards ground. This current remains “ON” until the voltage on

VCOVER

the V terminal falls by V

, typically 1.1V, below the upper threshold, V

. When the

C

CHYS

CMAX

voltage on this terminal falls below V

, typically 1.5V, the IC is disabled.

CEN

3

4

FB

Feedback from the regulator output is applied to this terminal. This terminal is the input to

the transconductance ampliﬁer. The ampliﬁer compares the internal 5.1V reference and

the feedback signal from the regulator output.

SOURCE

DRAIN

The terminal, labeled TAB, has a connection to this terminal, but because of the long lead

length and resulting high inductance of this terminal, it should not be used as a means of

bypassing. Therefore, this terminal is labeled “Do Not Use.”

5

6

Connection to the Drain of the internal power DMOS transistor is made at this terminal.

V

Gate drive supply voltage is provided at this terminal. A 10Ω to 150Ω resistor connected

G

between this terminal and the V terminal provides decoupling and the supply voltage

DD

for the gate drivers.

7

V

External supply input to the IC. A nominal 14V shunt regulator is connected between this

terminal and the TAB. A series resistor should be connected to this terminal from the

external voltage source to supply a minimum current of 33mA and a maximum current of

105mA under the worst cast supply voltage. The series resistor is not required if the

supply voltage is 12V, ±10%.

DD

TAB

SOURCE

This is the internal power DMOS transistor Source terminal. It should be used as the

ground return for the V bypass capacitor. In addition high frequency bypassing for both

DD

the regulator output load voltage and supply input voltage should be returned to this

terminal.

For more information refer to Application Notes AN9208, AN9212, AN9323.

Foot Print For Soldering

0.523

LIMIT OF SOLDER MASK

FOR HEADER

0.120

OPTIONAL Ø 0.151

0.050 TYP

0.212

0.424

0.050 TYP

0.080 TYP

0.480

0.575

0.675

TO-220 STAGGERED GULL WING SIP

7-58

HIP5061

Typical Performance Curves

26

24

20

18

16

14

12

10

8

V_FB= V_C= 0V, T_A= +25^oC

OPERATING CURRENT, V_DD= V_G= 13.2V, V_C= 8.5V, V_FB= 4V

22

20

18

16

14

QUIESCENT CURRENT, V_DD= V_G= 13.2V, V_C= 0V, V_FB= 4V

6

12

4

10

8

2

0

6

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

0

10

20

30

40

50

60

70

80

90

100

AMBIENT TEMPERATURE (^oC)

V_DD(V)

FIGURE 3. TYPICAL SUPPLY CURRENT vs TEMPERATURE

FIGURE 4. TYPICAL SUPPLY CURRENT vs SUPPLY VOLTAGE

26

1.2

1.1

1.0

0.9

24

V_DD= 12V, V_FB= 6V

22

20

18

16

14

12

10

T_A= 0^oC

T_A= +105^oC

0.8

V_DD= V_G= 12V, V_FB= 5.1V, V_C= 5V

0.7

0.6

0.5

0.4

0.3

0.2

8

6

4

0

10

20

30

40

50

60

70

80

90 100

0

1

2

3

4

5

6

7

8

9

10 11 12

AMBIENT TEMPERATURE (^oC)

VOLTAGE AT V_CPIN (V)

FIGURE 5. TYPICAL GATE DRIVER OPERATING

CURRENT vs TEMPERATURE

FIGURE 6. TYPICAL SUPPLY CURRENT vs VOLTAGE

o

AT PIN V FOR 0 C AND +105 C

C

15.0

14.8

14.6

5.20

5.18

5.16

5.14

5.12

5.10

5.08

5.06

5.04

5.02

5.00

I_DD= 100mA

14.4

V_DD= V_G= 12V, I_VC= 0µA, V_C= V_FB

14.2

14.0

13.8

13.6

13.4

13.2

13.0

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

AMBIENT TEMPERATURE (^oC)

FIGURE 7. TYPICAL CLAMP VOLTAGE vs TEMPERATURE

FIGURE 8. TYPICAL REFERENCE VOLTAGE vs

TEMPERATURE

7-59

HIP5061

Typical Performance Curves (Continued)

5.20

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

5.18

I_VC= 0mA, V_C= V_FB

5.16

V_DD= V_G= 12V, V_C= 5V, V_FB= V_REF

5.14

T_A= +105^oC

5.12

5.10

T_A= 0^oC

5.08

5.06

5.04

5.02

5.00

10.8

11.2

11.6

12.0

12.4

_DD(V)

12.8

13.2

13.6 14.0

0

10

20

30

40

50

60

70

80

90 100

AMBIENT TEMPERATURE (^oC)

V

FIGURE 9. TYPICAL REFERENCE VOLTAGE vs SUPPLY

FIGURE 10. TYPICAL INPUT CURRENT TO FB PIN vs

TEMPERATURE

o

VOLTAGE FOR 0 C AND +105 C

0.5

36

35

0.4

0.3

0.2

0.1

0

34

V_DD= V_G= 12V, IV_C= 500µA

33

32

31

30

29

28

27

26

25

24

23

22

V_DD= V_G= 12V, V_C= 4V, T_A= +25^oC

-0.1

-0.2

-0.3

-0.4

-0.5

-1

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

0

10

20

30

40

50

60

70

80

90 100

VOLTAGE ON FB PIN (V)

AMBIENT TEMPERATURE (^oC)

FIGURE 11. TYPICAL INPUT CURRENT TO FB PIN vs V

FIGURE 12. TYPICAL ERROR AMPLIFIER

FB

TRANSCONDUCTANCE vs TEMPERATURE

2.5

2.0

2.5

2.0

V_DD= V_G= 12V, V_C= 4V, T_A= +25^oC

1.5

SINKING CURRENT, V_FB= 5.6V

1.5

1.0

0.5

1.0

0.5

V_DD= V_G= 12V, V_C= 5V

0.0

-0.5

-1.0

-1.5

-2.0

-1.0

-1.5

-2.0

-2.5

SOURCING CURRENT, V_FB= 4.6V

-2.5

0

10

20

30

40

50

60

70

80

90 100

-175-150-125-100 -75 -50 -25

0

25 50 75 100 125 150 175

VOLTAGE ON FB PIN (mV) CENTERED AROUND 5.1V

AMBIENT TEMPERATURE (^oC)

FIGURE 14. TYPICAL ERROR AMPLIFIER SINKING AND

SOURCING CURRENT vs TEMPERATURE

FIGURE 13. TYPICAL V PIN CURRENT IV PIN vs

C

VOLTAGE ON FB PIN (SHOWS ERROR

AMPLIFIER TRANSCONDUCTANCE)

7-60

HIP5061

Typical Performance Curves (Continued)

2.5

12

V_DD= V_G= 12V, V_C= 4V, T_A= +25^oC

2.0

V_DD= 9V (UNDER VOLTAGE CONDITION)

T_A= 0^oC

T_A= +105^oC

10

8

1.5

1.0

0.5

0.0

-0.5

6

4

2

-1.0

-1.5

-2.0

-2.5

0

1

2

3

4

5

6

7

8

9

-1

0

1

2

3

4

5

6

7

8

9

10 11 12 13

VOLTAGE ON V_CPIN (V)

VOLTAGE ON FB PIN (V)

FIGURE 15. TYPICAL V PIN CURRENT vs

FIGURE 16. TYPICAL V PIN CURRENT vs VOLTAGE ON

C

o

VOLTAGE ON FB PIN

V PIN FOR 0 C AND +105 C

C

16

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_DD= 12V, T_A= +25^oC

V_CMAX

14

FB = 6V

FB = 4V

12

10

8

V_DD= VG = 12V

6

4

FB = 6V

2

V_CHYS

0

FB = 4V

-2

-4

0

10

20

30

40

50

60

70

80

90 100

0

1

2

3

4

5

6

7

8

9

10 11 12

AMBIENT TEMPERATURE (^oC)

VOLTAGE ON V_CPIN (V)

FIGURE 17. TYPICAL V PIN CURRENT vs VOLTAGE ON V PIN

FIGURE 18. TYPICAL SHORT CIRCUIT COMPARATOR

THRESHOLD VOLTAGE vs TEMPERATURE

C

FOR VOLTAGES ABOVE AND BELOW V

REF

11.0

10.5

10.0

9.5

3.0

2.5

V_DD= V_G= 10.8V, V_C= V_CMAX

V_DD= V_G= 12V, V_FB= 5.1V

2.0

1.5

1.0

9.0

0.5

0.0

8.5

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

8.0

7.5

7.0

6.5

6.0

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

AMBIENT TEMPERATURE (^oC)

FIGURE 19. TYPICAL OVER-VOLTAGE CURRENT vs

TEMPERATURE

FIGURE 20. TYPICAL CLOCK FREQUENCY PERCENT

CHANGE vs TEMPERATURE

7-61

HIP5061

Typical Performance Curves (Continued)

3.0

0.30

0.25

0.20

0.15

0.10

0.05

0.00

V_DD= V_G= 12V, V_FB= 5.1V

2.5

2.0

1.5

T_A= +100^oC

V_DD= V_G= 10.8V, I_DRAIN= 5A

1.0

T_A= 0^oC

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

10.8

11.2

11.6

12.0

12.4

12.8

13.2

13.6

14.0

0

10

20

30

40

50

60

70

80

90 100

AMBIENT TEMPERATURE (^oC)

V

_DD(V)

FIGURE21. TYPICALCLOCKFREQUENCYPERCENTCHANGE

FIGURE 22. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE

RESISTANCE vs TEMPERATURE

o

vs SUPPLY VOLTAGE V AT 0 C AND +100 C

DD

0.30

0.28

0.26

0.24

0.22

0.20

0.18

0.16

0.14

0.12

0.10

0.50

0.45

V_DD= V_G= 10.8V, V_FB= 5.1V

T_A= +100^oC

V_DD= 60V

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

T_A= 0^oC

0

10

20

30

40

50

60

70

80

90 100

0

1

2

3

4

5

6

7

AMBIENT TEMPERATURE (^oC)

DMOS TRANSISTOR DRAIN CURRENT (A)

FIGURE 23. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE

FIGURE 24. TYPICAL DMOS TRANSISTOR DRAIN TO SOURCE

LEAKAGE CURRENT vs TEMPERATURE

RESISTANCE vs DRAIN CURRENT I

AT

DRAIN

o

0 C AND +100 C

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

2.90

V_DD= V_G= 12V

V_DD= V_G= 12V, I_DRAIN= 0.25A

2.88

2.86

2.84

2.82

2.80

2.78

2.76

2.74

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

AMBIENT TEMPERATURE (^oC)

FIGURE 25. TYPICAL TRANSCONDUCTANCE FROM V PIN TO

FIGURE 26. TYPICAL VOLTAGE TO CURRENT CONVERTER

REFERENCE VOLTAGE vs TEMPERATURE

C

DMOS TRANSISTOR DRAIN (PEAK CURRENT)

vs TEMPERATURE

7-62

HIP5061

Typical Performance Curves (Continued)

180

150

V_DD= V_G= 12V

175

145

140

135

130

125

120

115

170

165

160

155

150

145

140

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

AMBIENT TEMPERATURE (^oC)

FIGURE 27. TYPICAL MINIMUM DMOS TRANSISTOR “ON”

TIME vs TEMPERATURE

FIGURE 28. TYPICAL MINIMUM DMOS TRANSISTOR “OFF”

TIME vs TEMPERATURE

-0.50

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

-0.55

V_DD= V_G= 12V

-0.60

-0.65

-0.70

-0.75

-0.80

-0.85

-0.90

-0.95

-1.00

V_DD= V_G= 12V, DUTY CYCLE = 96%

4.5

4.0

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

AMBIENT TEMPERATURE (^oC)

FIGURE 29. TYPICAL MAXIMUM CONTROLLABLE PEAK

DMOS DRAIN CURRENT vs TEMPERATURE

FIGURE 30. TYPICAL COMPENSATING RAMP RATE

vs TEMPERATURE

1.80

11

1.75

V_DD= V_G= 12V

10

V_DDMIN

1.70

1.65

1.60

1.55

1.50

1.45

1.40

1.35

1.30

1.25

1.20

9

8

7

6

V_FB= 4V

5

4

3

2

V_DDHYS

1

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

AMBIENT TEMPERATURE (^oC)

FIGURE 31. TYPICAL COMPENSATION RAMP DELAY

TIME vs TEMPERATURE

FIGURE 32. TYPICAL RISING V COMPARATOR THRESHOLD

DD

VOLTAGE vs TEMPERATURE

7-63

HIP5061

Typical Application Circuit

Figure 33 shows a Simpliﬁed Block Diagram of the HIP5061 in a

typical Boost converter. A resistor connected from the V_INsupply

to the V_DDterminal of the IC powers the internal 14V shunt

regulator. The Gate Driver supply is decoupled from the main

supply by a small external resistor connected between V_DDand

the V_Gterminal. A bypass capacitor is connected between the

A 2MHz internal clock provides all the timing signals for the

converter operating at 250kHz. A slope compensation circuit

is also incorporated within the converter IC to eliminate sub-

harmonic oscillation that occurs in continuous-current mode

converters operating with duty cycles greater than 50%.

V

_DDterminal and ground to reduce coupling between analog and

HIP5061 Description of Operation

digital circuitry. A Schottky diode insures efﬁcient energy transfer

from the DMOS drain circuit inductor to the load. To set the

output voltage, two resistors are used to scale the output supply

voltage down to the 5.1V internal reference.

Figure 2 shows a more detailed Functional Block Diagram of

the HIP5061. An internal 14V shunt regulator in conjunction

with an external series resistor provides internal operating

voltage to the IC in applications where no 12V auxiliary sup-

ply is available. Note that In applications where the input

voltage at V_DDis 12V, +/-10%, the regulator is not used. This

regulator is shown as a zener diode on the diagrams of Fig-

ure 2 and Figure 33.

The heart of the IC is the high current DMOS power

transistor with its associated gate driver and high-speed

peak current control loop. A portion of the converters DC

output is applied to a transconductance error ampliﬁer that

compares the fed back signal with the internal 5.1V

reference. The output of this ampliﬁer is brought out at

the V_Cterminal to provide for soft start and frequency

compensation of the control loop. This same signal is also

applied internally to program the peak DMOS transistor

drain current. To assure precise current control, the

response time of this peak current control loop is less

than 50ns.

The 2MHz clock is processed in the Control Logic block to

provide various timing signals. A cycle of operation begins

when a 100ns pulse (which occurs at a 4µs interval) triggers

the latch that initiates the DMOS transistor on-time. This

pulse also provides a blanking interval in the Current Moni-

toring block to eliminate false turn-offs caused by high tran-

sient pulse currents that occur during turn-on. The output of

V_IN

V_OUT

V_DD

V_DDCLAMP

V_G

DRAIN

HIP5061

GATE

DRIVER

TAB

(SOURCE)

CONTROL

LOGIC

2MHz

CLOCK

V_C

OVER

TEMP

AMP

FB

V/I

2.6V

UNDER

VOLTAGE

SLOPE

COMPENSATION

5.1V

REFERENCE

GND

FIGURE 33. SIMPLIFIED BLOCK DIAGRAM OF THE HIP5061 IN A TYPICAL "BOOST" CONFIGURATION

7-64

HIP5061

the Current Ramp block is summed with the sensed DMOS impedance, ideally inﬁnity. The ampliﬁer gain is typically

transistor current (to provide slope compensation) before 50dB and is not signiﬁcantly altered when operating into the

being compared with the Error Current signal. The current stages that follow within the IC. To minimize the output stage

ramp, -0.45A/µs, is inhibited for the ﬁrst 1.5µs (37.5%) of the idling current, while providing high peak currents to insure

duty cycle by the Ramp Enable signal, since ramp is not rapid response to load and input transients, a class B type of

needed for slope compensation during this interval. Inhibit- output stage was used in the ampliﬁer. Placing a 100k

ing of the compensating ramp has the effect of reducing the resistor from the ampliﬁer output terminal, V_C, to ground will

peak short-circuit current.

bias the output stage to an active state and still minimize

power consumption. In all cases, the resistor shunting the

transconductance ampliﬁer output must be greater than

10kΩ to insure that the output will rise sufﬁciently high to

obtain the maximum DMOS transistor drain current.

The output of the power supply is divided down and

monitored at the FB terminal. A transconductance error

ampliﬁer compares the DC level of the fed back voltage with

an internal bandgap reference, while providing voltage loop

compensation by means of external resistors and Start-Up Sequence

capacitors. The Error Ampliﬁer output (the error voltage) is

Upon initial power up of the HIP5061 in a typical application

then converted into a current (the Error Current) that is used

to program the required peak DMOS transistor current that

produces the desired output voltage. When the sum of the

sensed DMOS transistor current and the compensating

ramp exceed the Error Current signal, the latch is reset and

the DMOS transistor is turned off. Current comparison

around this loop takes place in less than 50ns, allowing for

excellent 250kHz converter operation. The latch can also be

reset by an under-voltage (V_DD< 10.3V typical), over

temperature (T_J> +125^oC typical) or a shutdown signal

externally applied at the V_Cterminal. See Figure 36.

circuit, the voltage at V_Cwill be zero, and the DMOS transis-

tor will be off. When the voltage at V_DDrises above the

10.3V typical threshold, the error ampliﬁer output is enabled

and the V_Cvoltage begins to rise in response to the low volt-

age at the FB terminal. When the V_Cvoltage rises above

1.5V the DMOS transistor begins to switch at the minimum

duty cycle, and when it rises above 2.55V the duty cycle

begins to increase. The V_Cvoltage (and peak DMOS tran-

sistor current) will then continue to rise until the voltage loop

gains control and establishes regulation. Note that the rate

of rise in the V_Cvoltage can be controlled by an external soft

Note that if the error voltage (at the V_Cpin) is less that start circuit (See Soft Start Implementation).

2.55V, then the output of the Voltage-to-Current Converter

If the V_Cvoltage is unrestricted in its rate of rise, then it will

will be held at zero. This condition will produce the minimum

typically rise quickly to its maximum (peak current) value,

possible pulse width, typically 150ns (100ns blanking pulse

causing the DMOS transistor to turn-on and stay on until it

plus 50ns delay). Error voltages lower than this 2.55V level

reaches the peak current value. At this point, the DMOS

will not produce shorter pulse widths. Under very light loads

transistor begins switching, and the V_Cvoltage (and peak

(when V_Cgoes below 1.5V), the Enable Comparator will

DMOS transistor current) will drop down to the level com-

manded by the voltage loop.

temporarily hold-off the PWM latch (and the DMOS transis-

tor) until the V_Cvoltages rises above 1.5V. This low V_C

inhibit circuit results in a burst-mode of operation that main-

tains regulation under light or no loads.

Using the Shunt Regulator

The internal 14V shunt regulator in conjunction with an

During an over-current condition, the output of the Error

external series resistor allows the IC to operate from quite

Ampliﬁer will attempt to exceed the 7.0V threshold. At this

high input voltages, limited only by power dissipation in the

point, the Short-Circuit Comparator will pull down on this sig-

external resistor. When only higher voltages are available, a

nal and induce a low-level oscillation about the threshold,

bootstrap or other 12V auxiliary supply can be used to elimi-

serving to clamp the peak error voltage. This clamping

nate this dissipation. The series resistor should be chosen to

action, in turn, will limit the peak current in the DMOS tran-

be as large as possible to reduce power dissipation at high

sistor, reducing the duty ratio of the switch as the demand for

line, while ensuring adequate V_DDvoltage at low line. The

current continues to increase. This action, in conjunction

maximum value for this resistor, R, is given by:

with the Thermal Monitor, serves to protect the IC from over-

current (short-circuit) conditions.

V

– 10.5

I^,MIN

R

(Ω) =

----------------------------------------

Using the Transconductance Error Ampliﬁer

MAX

0.033

A transconductance ampliﬁer with a typical g_mof 30mS is

used as the input gain stage where the power supply output

voltage is compared with the internally generated 5.1V

reference voltage. A PNP transistor input structure allows

this ampliﬁer to accommodate large negative going transient

voltages without causing ampliﬁer phase reversal, often

associated with PNP input structures. Negative transients up

to 5V applied to the input though at least 5.1k will not result

in phase reversal. The ampliﬁer output stage has the

customary drain to drain output to help improve the output

Where V_Iis the input voltage to the power supply. The value

chosen for this resistor must also result in a current, I, into

the V_DDclamp that is less than 105mA when the input volt-

age is at its maximum:

V

– 13.3

I^,MAX

R

I

(A) =

-------------------------------------------------

MAX

7-65

HIP5061

TABLE 2. MINIMUM INDUCTANCE FOR STABLE CCM

OPERATION ABOVE 50% DUTY CYCLE

Inductor Selection

The selection of the energy storage inductor(s) L_STORfor a DC to

DC converter has tremendous inﬂuence on the behavior of the

converter. It is particularly important in light of the high level of

integration (and necessarily few degrees of freedom) achieved in

the HIP5061. There are several factors inﬂuencing the selection

of this inductor. First, the inductance of L_STORwill determine the

basic mode of operation for the converter: continuous or

discontinuous current. In order to maximize the output power

for the given maximum controllable DMOS transistor current, a

converter may be designed to operate in continuous current

mode (CCM). However, this tends to require a larger inductor,

and for many converter topologies results in a feedback loop

tha is difﬁcult to stabilize. For these and other reasons, the

inductor L_STORmay be chosen so as to operate the converter in

discontinuous current mode (DCM). The relative merits of

CCM and DCM operation for various topologies and the

corresponding selection of L_STORis well documented and will not

be covered here.

CONVERTER TYPE MINIMUM INDUCTANCE

V_O+ V_D– V_{I, MIN}

-------------------------------------------

2M_{R, MIN}

Boost

L =

L₁L₂

V

_O+ V_D

----------------- ----------------------

L₁+ L₂2M_{R, MIN}

SEPIC (Note 1)

Cuk (Note 2)

Flyback

>

L₁L₂

V_O– V_D

----------------- > ----------------------

L₁+ L₂2M_{R, MIN}

N_P(V_O+ V_D)

L_P

>

------ ---------------------------

N_S2M_{R, MIN}

N_S(V_O+ V_D)

Forward

L >

------ ---------------------------

N_P2M_{R, MIN}

A second factor inﬂuencing the selection of L_STORis the

stability requirement for current-mode control. This constraint is

only applicable for converters operating in CCM, since open-

loop instabilities of this type are not observed in converters

operating in DCM. For marginal stability, the compensating

ramp (internal to the HIP5061) must have a slope that is

greater than one-half the difference between the inductor

current’s down slope and up slope. (To ensure stability for duty

ratios D > 0.8, the slope of the compensating ramp should be

equal to the inductor current downslope.) A generally accepted

goal is to set the slope of the compensating ramp to be at least

one-half of the inductor current down slope. Since there is no

external control over the internal compensating ramp, one must

be sure that the inductor is large enough so that the down slope

of the inductor current is not too large. Table 2 summarizes this

requirement for minimum inductance for several common

topologies.

NOTES:

1. Assumes that L and L are both CCM.

1

2

2. L = Inductance in Henrys, V = Output Voltage,

O

V

= Diode Voltage Drop, V = Input Voltage,

D

I

M

= (∆I/∆t)

= 0.45A/µs, L = Drain Inductor,

MIN 1

R,MIN

L = Secondary Inductor, N = Primary Turns,

2

P

N

= Secondary Turns

S

DMOS Transistor Turn-Off Snubber

In order to reduce dissipation in the DMOS transistor due to

turn-off losses, the turn-off time has been minimized.

However, the rapid reduction of current that occurs in the

drain of the DMOS transistor can result in large transient

voltages being induced across any parasitic inductance in

A third constraint on the size of the inductor is one that is the drain path. For this reason, it is important that such

common among current-mode controlled PWM converters, parasitic inductance be reduced by good, high frequency

and applies to both DCM and CCM operation. The stable layout practices. Nevertheless, there are many instances

generation of the desired DMOS transistor pulse width (e.g., transformer isolated topologies) in which voltages in

depends on the accurate comparison of the error signal and excess of 60V may be developed at the DMOS transistor

the peak L_STOR(DMOS) transistor drain current. Thus, as drain. In some cases, a simple R-C snubber may be added

the peak L_STORripple current becomes smaller, immunity to reduce the overshoot of the drain voltage to a safe level.

from noise on the error signal is eventually reduced until the

It is also possible that the large amount of ringing that can

pulse width can no longer be adequately controlled. For the

occur at the DMOS transistor drain at turn-off will induce

HIP5061, the inductor current ripple must be at least 200mA

noise in the IC. This noise may result in false triggering of

peak to peak to ensure proper control of the DMOS

the PWM latch, particularly at high peak DMOS transistor

transistor current. This effectively establishes a maximum

drain currents. Noise related instability can also be elimi-

value for the inductor L_STOR, so as to maintain at least

nated by the addition of a snubber, which will rapidly damp

200mA of ripple. Note that under extremely light or no load

out such turn-off ringing. Good layout practices will reduce

conditions, all converters will eventually operate in DCM,

the need for such protective measures, and ensure that the

and the 200mA requirement will eventually be violated.

DMOS transistor is not overstressed.

Under these conditions, the HIP5061 will continue to

regulate, although the switching of the DMOS transistor will

Under-Voltage Lockout

be in

a burst-mode, controlled by the Light Load

The V_DDinput voltage is monitored by a comparator that

holds off the DMOS transistor gate drive signal when the

Comparator. (See Figure 2.)

V_DDvoltage is less that about 10.3V. The typical 0.5V hyster-

7-66

HIP5061

esis of this comparator is intended to reduce oscillation DMOS Transistor Turn-On Noise

when the voltage at V_DDis in the vicinity of 10V. Note, how-

Although the large DMOS transistor turn-on current spikes are

ever, that when an external series resistor is used to feed the

shunt regulator, the voltage drop across this resistor (which

sharply decreases when the IC shuts down), effectively

reduces the hysteresis. To reduce the tendency for oscilla-

tion in the vicinity of the 10V threshold, the impedance of the

source that feeds the DC to DC converter input should be

minimized. The addition of a capacitor (1µF-47µF) at the

“blanked over” by the control circuit, it is important to minimize

these current spikes, since they often result in voltage spikes

considerably below the device substrate that can activate par-

asitic devices within the IC. Such activation of parasitic

devices will often result in improper operation of the IC. An

external terminal labeled V_Gbrings out the power supply to

the gate drive circuitry. This allows for the control of the peak

current delivered to the gate of the DMOS transistor, which in

turn establishes the turn-on speed. The V_Gpin may be exter-

nally bypassed for the fastest possible turn-on, or series resis-

tance may be added with no bypassing capacitor to slow

down the turn-on of the DMOS transistor. Depending upon the

actual layout of the supply, it is generally recommended that a

series resistor be added (10Ω-150Ω) so that the DMOS tran-

sistor turn-on speed is reduced. By properly adjusting the

turn-on speed, undershoot can be avoided while turn-on

switching losses are kept to a minimum.

V_DDterminal can also help to provide smooth turn-on or turn-

off of the converter if the input supply rises or falls gradually

through the V_DDComparator threshold.

Peak Controllable DMOS Transistor Current

Figure 34 shows the guaranteed minimum, peak controllable

DMOS transistor current versus duty cycle. This peak cur-

rent value is established by the current limit circuitry, which

effectively clamps the voltage at V_C(the error voltage) to

perform current limiting. Since the sensed DMOS transistor

current is summed with a compensating current ramp that

begins its rise 1.5µs after the initiation of a cycle, current lim-

iting will begin to occur at a peak DMOS transistor current

that varies with the operating duty cycle. The highest current

limit threshold occurs for D<0.375, where no ramp is added

to the sensed DMOS transistor current. At higher operating

duty ratios, the onset of current limit will occur at increasingly

lower currents, due to the effect of adding the compensating

ramp to the sensed current. Note that this curve represents

guaranteed minimum values. The guaranteed maximum val-

ues are considerable higher, although they are still limited to

levels that protect the IC.

Soft Start Implementation

It is often desirable to allow the regulator to start up slowly,

Figure 35 shows one means of implementing this action. The

normally high output current from the HIP5061 transconduc-

tance ampliﬁer (when V_FB= 0 and V_REF= 5.1V) is directed to

an external capacitor through a diode. This slows down the

rate of rise of the voltage at the V_Cterminal. After the regula-

tor starts, the external capacitor is charged to V_DDand is

effectively removed from the frequency compensation net-

work by a reverse biased diode. To ensure rapid recycling of

the capacitor voltage with removal of power, a diode is placed

across the 100kΩ resistor. Logic Shutdown Input (V_CPin).

7

5

3

1

100kΩ

V_DD

V_C

V_G

DRAIN

2mA, TYP

GATE DRIVER

AND CONTROL

CIRCUITRY

20µF

FB

SOFT START

NETWORK

HIP5061

GND

SOURCE

100kΩ

0.1µF

1.0

0.375

0.06

DUTY CYCLE

TYPICAL FREQUENCY

COMPENSATION NETWORK

FIGURE 34. PEAK DMOS TRANSISTOR DRAIN CURRENT vs

DUTY CYCLE

FIGURE 35. SOFT START CIRCUIT FOR THE HIP5061

When the DMOS transistor ﬁrst turns ON there may be sub-

stantial current spikes exceeding the normal maximum peak

current established by the current control stages within the

IC. To prevent these spurious spikes from conveying errone-

ous information to the Current Comparator, a 100ns blanking

signal is applied to the current monitoring circuitry. Thus,

there is no peak current protection during the ﬁrst 6% of the

duty cycle (see Figure 36).

The DC to DC converter may be shut down by returning the

V_Coutput terminal to ground. A sinking current greater than

4mA will insure that this output is pulled to ground. It must be

remembered that once switching operation ceases, the drain

of the DMOS transistor is open. When the supply is in the

Boost conﬁguration, the output voltage is not zero but the input

voltage less diode and inductor voltage drops. If the SEPIC

7-67

HIP5061

topology is used, this is not the case. Shutting down the regu- All the capacitors shown with values of 1µF or less are of the

lator via the V_Cterminal will cut off the output. Figure 36 shows multilayer ceramic type with the X7R dielectric material. This

two methods of shutting down the IC. In each case the current material has a fairly ﬂat voltage and temperature coefﬁcient

sinking circuit must be able to sink at least 4mA, the maximum that assures that the capacitance remains comparatively con-

current from the HIP5061 V_Cterminal.

stant at extreme operating temperatures and voltages. The

multilayer construction allows for comparatively large values

with good volumetric efﬁciency and low inductance. Capaci-

tors around the power input and output circuits should be

returned to the device TAB via a low inductance ground plane.

This TAB is internally connected to the DMOS transistor

source. The schematic diagram of Figure 38 was drawn with

the diagonal leads to show the critical paths for the various

high frequency elements. These short interconnects assure

the lowest inductance around the output power circuit.

V_DD

V_G

DRAIN

FROM CD4049UB

4mA

V_C

GATE DRIVER

AND CONTROL

CIRCUITRY

OFF

FB

Design of a 28V, 1.8A Boost Converter

GND

SOURCE

HIP5061

Figure 38 shows the schematic diagram and a parts list of a

50W supply designed with the HIP5061. Table 3 tabulates

the performance of the power supply.

NOTE: FREQUENCY

COMPENSATION NETWORK

NOT SHOWN

ALTERNATE METHOD

TABLE 3. TYPICAL LABORATORY PERFORMANCE OF

50W, 28V/1.8A REGULATOR

FIGURE 36. TWO METHODS OF SHUTTING DOWN THE HIP5061

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V to 16V

Line Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mV/V

Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.0V

Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 64mV/A

Mounting, Layout and Component

Selection

The TO-220 package with its gullwing leads was designed to

be surface mounted. To aid in the external reduction of lead

length and hence inductance and resistance, the IC leads

were staggered. To keep the inductance and resistance of

the critical drain terminal as low as possible, it is suggested

that the PC trace to the DMOS transistor drain terminal be

made as wide as possible. The adjacent source terminal is

not recommended to be used and therefore allows the metal

to the drain terminal to be widened beyond the normal

widths for these terminals. Figure 37 illustrates these points.

Output Ripple, FL . . . . . . . . . . . . . . . . . . . . . . . . . . 600mV P-P

(20MHz BW)

Output Ripple, after Filter, FL . . . . . . . . . . . . . . . . . 80mV P-P

(20MHz BW)

Efficiency: V = 11V, I = 0.18A. . . . . . . . . . . . . . . 90%

I

L

V = 11V, I = 1.8A. . . . . . . . . . . . . . . . 89%

I

L

V = 16V, I = 0.18A. . . . . . . . . . . . . . . 73%

I

L

V = 16V, I = 1.8A. . . . . . . . . . . . . . . . 93%

I

L

One of the most important aspects to the proper application

of this device is high frequency bypassing. In a Boost con-

verter, for example, there should be a low-inductance inter-

connect from the DMOS transistor drain, through the output

diode and capacitors, and returning to the TAB (source) of

the HIP5061. Inductance in this line results in large transient

voltages on the DMOS transistor drain terminal which can

result in voltages above the maximum DMOS transistor

drain voltage rating.

Inductor Selection

In order to maximize the output power for the given maxi-

mum controllable DMOS transistor current, this converter

has been designed to operate in continuous current mode

(CCM). In this mode, the inductor value will generally be

large, resulting in a lower inductor ripple current and a lower

peak DMOS current. To ensure that the converter operates

in CCM over the usable range of input voltage and output

current, the value of L2 must be greater than the “critical

inductance,” given by

IC SOLDERED TO PC BOARD

V_GPC METAL

V_DDPC METAL

WIDER

DRAIN

2

V

+ V – V

T

PC METAL

FOR LOWER

INDUCTANCE

O I^,MAX

O

D

I^,MAX

S

L

=

----------------------------------------------------------------------------------------------------------

CRIT

2

2P

2

V

+ V

O^,MIN

O

D

HIP5061

NORMAL

PC METAL

FOR FB

(28) (16) (28 + 0.5 – 16) 4×10^–6

-------------------------------------------------------------------------------------------------

2

=

AND V_C

2 (5.6) (28 + 0.5)

GROUND PC METAL

= 39µH

FIGURE 37. SHOWING WIDER PC BOARD METAL FOR

CRITICAL

7-68

HIP5061

where P_O,MINhas been arbitrarily chosen as 5.6W, corre-

D.C. Gain: 20dB-40dB

sponding to an output current of 0.2A, and V_Dis the forward

voltage of CR1. Thus, for L2 > 39µH, the converter will be in

CCM for V_I= 11V to 16V and I_L= 0.2A to 1.8A.

Pole at 88Hz-880Hz

LHP Zero at 1MHz

RHP Zero at 11.0kHz-110kHz

Double Pole at 80kHz (from ﬁlter)

A second factor inﬂuencing the selection of L2 is the stability

requirement for current-mode control. Using the above

equation for L_MINfor the Boost converter:

To stabilize the voltage loop, it is necessary to establish the

unity gain crossover frequency well below the RHP zero, since

this zero introduces positive gain and negative phase. A cross-

over of 4kHz is fairly conservative, and is achieved by adding a

1µF capacitor at the VC pin, which provides near inﬁnite DC

gain, and about -5dB of gain at 4kHz. This results in a phase

margin of about 15^oat full load. Note that R4 is required for

proper operation of the transconductance ampliﬁer, since it is

providing bias current for the output stage as discussed under

Using the Transconductance Error Ampliﬁer section.

V

+ V – V

O

D

I^,MIN

28 + 0.5 – 11

L >

=

= 19µH

-----------------------------------------------------

--------------------------------------------------------

2 × M

6

RAMP^,MIN

2 × 0.45×10 A ⁄ S

Thus, L2 must be at least 19µH to ensure good stability of

the current loop, and a choice of L2 = 40µH satisﬁes this

requirement, while maintaining CCM operation over an

extremely wide load range.

Output Filter Design

Inductor L3 was chosen with C11 to provide at least 15dB of

ripple attenuation at the switching frequency. The corner fre-

quency (80kHz) of this ﬁlter is well above the crossover fre-

quency of the voltage loop (4kHz), and has no effect on

stability. This secondary LC ﬁlter was used to reduce output

ripple instead of a lower-cost, high-value, low ESR alumi-

num electrolytic capacitor to demonstrate the reduction in

volume possible at this switching frequency. A lower cost

solution could achieve the same output ripple by replacing

C9,10,12 and L3 with one or two large capacitors (e.g.,

The chosen core material for L2 is Kool Mu ferrous alloy pow-

der from Magnetics, Inc. This material was chosen because of

its relatively low cost, while its losses due to AC ﬂux are ﬁve to

ten times less than conventional powdered iron.

Loop Compensation

The control to output transfer function for this current-mode

boost converter has the following characteristics over the

speciﬁed load and line conditions:

L3, 4µH

1µF,

50V

L2, 40µH

CR1

C4

RA

20Ω, 1W

INPUT

11VDC - 16VDC

C12

47µF,

C3

1µF,

50V

C11

1µF,

50V

R11

50V

C5

R5

10Ω, 1/4W

OUTPUT

28VDC

0A - 1.8A

7.5Ω, 1/2W

C9

6.8µF,

50V

7

6

5

R1

10K,

1%

47µF,

50V

C13

1nF,

100V

V_DD

V_G

OPTIONAL

FILTER

DRAIN

GATE DRIVERS,

CONTROL CIRCUITRY

AND LOGIC

C10

6.8µF,

50V

TAB

3

1

(SOURCE)

FB

GND

1µF,

50V

R2

2.21K, 1%

C1

2

R4

100K

HIP5061

V_C

PARTS LIST

C1, C3, C4 and C11 1µF, 50V, Ceramic - Murata Erie RPE113X7R105050V

C5 and C12 47µF, 50V, Alum - United Chemicon 515D476M050

C9 and C10 6.8µF, 50V, Ceramin - Mallory M60u6r8M50

C13 1nF, 100V, Ceramin - Kemet C322C102K1G5CA

CR1 Schottky Diode - Motorola MBRD360

RA 20Ω, 1W, Wirebound - Dale RWR81S20R0FR or Equivalent

R1 10K, 1%

R2 2.2K, 1%

R4 100K, 1/4W

R5 10Ω, 1/4W

L2 40µH at 5A, Pulse Engineering PE - 53571

R11 7.5Ω, 1/2W, Carbon - Allen Bradley EB75G5

L3 4µH at 5.5A, Pulse Engineering PE - 53570

FIGURE 38. HIP5061 50W, 28V BOOST REGULATOR SCHEMATIC AND PARTS LIST

7-69

HIP5061

390µF, 50V, type 673D from United Chemicon). This change Snubber Network

would also greatly improve load transient response, pro-

A snubber network has been added to reduce the ringing at

vided that the loop compensation is appropriately adjusted.

Note that in the circuit of Figure 38, capacitor C12 does not

signiﬁcantly affect output ripple, but is necessary to absorb

the energy stored in L2 during severe load transients. In the

event of a step change in load from 1.8A to 0A, C12 will limit

the output voltage overshoot to about 10V and protect the

drain of the DMOS transistor from overvoltage breakdown.

the drain due to parasitic layout inductances. In particular,

under severe load transient conditions, this snubber is nec-

essary to protect the drain from voltage breakdown. A sec-

ond beneﬁt of reducing the noise and ringing at the drain is

that it reduces the tendency of the HIP5061 to exhibit noise-

related instabilities at high peak DMOS transistor currents

(4A-6A). A value of 1000pF was chosen for C13, since this

is adequate to dampen the ringing associated with the

200pF drain capacitance of the DMOS transistor. R11 was

chosen as 7.5Ω to provide the best possible dampening

given the parasitic inductances that exist in the layout. Note

that this snubber may not be necessary if the layout of the

circuit were improved, or if the application did not push the

envelope of DMOS transistor current.

Input and V_DDFilters

Since the boost converter is current fed, input ﬁltering is eas-

ily achieved by the addition of a small capacitor C4. This

capacitor provides nearly 40dB of ripple current attenuation

for the input, reducing the AC ripple current ﬂowing into the

converter to less than 200mA.

R5 and C3 have been chosen to provide good ﬁltering of

high frequency pulse currents. R5 provides isolation

Other Power Supply Topologies

between the analog V_DDpin and the high pulse current V_GFigure 39 shows three other topologies besides the Boost that

pin, and also provides a means to control the turn-on speed may be implemented with the grounded source DMOS power

of the DMOS transistor by limiting the peak current available transistor used in the HIP5061. Other, more complex power

to the internal gate drive circuitry. Thus the output transition supply topologies such as the Quadratic are also possible to

time may be increased to prevent drain voltage undershoot. implement with the HIP5061. One noteworthy feature of the

Undershoot may result in activation of device parasitics and Quadratic topology as shown in Figure 41 is the wide input to

improper circuit operation. For the two-layer board used for output voltage transfer ratio possible with reasonable duty

this design, C3 could be reduced to 0.22µF without affecting cycles. Duty cycles that are not near the Minimum DMOS tran-

circuit operation. C5 was added to provide low-frequency ﬁl- sistor “ON” Time speciﬁcation shown in the Data Sheet. This

tering at the V_DDpin. This reduces the tendency of the circuit permits easier control at the extremes of the transfer ratios.

to oscillate off and on when the voltage at the V_DDpin s in Compensating the control loop can pose challenges because

the vicinity of the under voltage lockout threshold, typically of the wider changes in the transfer ratio and hence loop gain.

10V, and the output power is high (30W - 50W).

The SEPIC topology^[11,13]does not have quite as wide input-

Shunt Regulator Resistor

output voltage range with reasonably controlled duty cycles

as the Quadratic converter mentioned above, but it does

allow both voltage increase and decrease with the same cir-

cuit. This is particularly advantageous when a power supply

is being used in the stabilizing mode and isolation is not

required. For example, in an application where a regulated

24V output is required and the input voltage varies ±20%

from a nominal 24V. The SEPIC supply can provide both the

Boost and Buck functions.

Resistor RA has been chosen to be as large as possible to

reduce power dissipation at high line, while ensuring ade-

quate V_DDvoltage at low line. Note that the guaranteed

range of input voltage for proper operation of this circuit is

11.2V to 15.3VDC, based upon data sheet limits. However,

the circuit was found to perform well at room temperature for

V_I= 10.7VDC to 17VDC. The maximum value for RA is

V

– 10.5

Another outstanding advantage of the SEPIC topology is its

fault isolation of the input and output voltage. All energy is

transferred via the coupling capacitor. Moreover if the clock

stops, voltage transfer stops. If the switching transistor shorts

there is no output. The Buck circuit will apply full input voltage

to the load with a shorted transistor. This is reason that the

SEPIC topology is referred to as the fail-safe Buck.

I^,MIN

R

=

= 21Ω

----------------------------------------

MAX

0.033

RA has been chosen as 20Ω, which results in a current into

the V_DDclamp that is less than 105mA when the input volt-

age is at its maximum:

V

– 13.3

I^,MAX

I

=

= 100mA < 105mA

-------------------------------------------------

MAX

20.0

7-70

HIP5061

+

V_OUT

-

V_DD

V_G

DRAIN

GATE DRIVER

AND CONTROL

CIRCUITRY

V_IN

V_OUT

V_C

FB

V_DD

V_G

DRAIN

HIP5061

V_IN

GATE DRIVER

AND CONTROL

CIRCUITRY

GND

SOURCE

-

V_C

COUPLING

MEANS

FB

ISOLATED

OR DIRECT

HIP5061

GND

SOURCE

-

FIGURE 39A. SEPIC (FAIL-SAFE BUCK) CONVERTER

+

-

FIGURE 40. FLYBACK CONVERTER

V_DD

V_G

DRAIN

It should be noted that when the Cuk topology is imple-

mented, a transistor current source is used to convert the

negative output voltage of the Cuk converter to a current that

is level shifted to the FB terminal on the HIP5061.

GATE DRIVER

V_IN

AND CONTROL

CIRCUITRY

V_C

FB

V_OUT

HIP5061

GND

Two other useful topologies that may be used are the For-

ward and the Flyback as shown in Figure 40 and Figure 41.

As shown, they may either be operated as an isolated or

non-isolated converter.

SOURCE

FIGURE 39B. CUK CONVERTER

+

V_OUT

+

-

V_DD

V_G

DRAIN

V_DD

V_G

DRAIN

GATE DRIVER

AND CONTROL

CIRCUITRY

V_OUT

V_IN

GATE DRIVER

AND CONTROL

CIRCUITRY

V_C

FB

V_C

COUPLING

MEANS

FB

HIP5061

ISOLATED

OR DIRECT

GND

SOURCE

HIP5061

-

GND

SOURCE

-

FIGURE 39C. QUADRATIC CONVERTER

FIGURE 39. THREE OTHER TOPOLOGIES

FIGURE 41. FORWARD CONVERTER

7-71

HIP5061

Both the SEPIC and the Boost topologies may be operated

References

at high voltages with the addition of a high voltage cascode .

Figure 42 shows the Cascode SEPIC converter that is

essentially limited by the selection of the external power

transistor. The burden of voltage, and power is placed upon

the external transistor. The HIP5061 still performs the drain

current sampling and the control function is the same as the

non cascode conﬁguration.

[1] Cassani, John C.; Hurd, Jonathan J. and Thomas, David

R., Wittlinger, H.A.; Hodgins, Robert G.; Sophisticated

Control IC Enhances 1MHz Current Controlled Regulator

Performance, High Frequency Power Conversion (HFPC)

conference proceedings, May 1992, pp. 167-173

[2] Smith, Craig D. and Cassani, Distributed Power Systems Via

ASICs Using SMT, Surface Mount Technology, October 1990

[3] Maksimovic and Cuk, Switching Converters With Wide DC

Conversion Range, High Frequency Power Conversion

(HFPC) conference record, May 1989

+

[5] Maksimovic and Cuk, General Properties and Synthesis of

PWM DC-to-DC Converters, IEEE Power Electronics

Specialists Conference (PESC) record, June 1989

V_OUT

160V

V_IN

V_DD

V_G

DRAIN

[6] Sokal and Sokal, Class E - A New Class of High Efﬁciency

Tuned Single-Ended Switching Power Ampliﬁers, IEEE

Journal of Solid-State Circuits, June 1975, pp. 168-176

GATE DRIVER

AND CONTROL

CIRCUITRY

V_C

FB

[7] Mansmann, Jeff; Shafer, Peter and Wildi, Eric, Maximizing

the Impact of Power ICs Via a Time-to-Market CAD Driven

Power ASIC Strategy, Applied Power and Electronics

Conference and Exposition (APEC) proceedings, Febru-

ary 1992, pp. 23-27

HIP5061

GND

SOURCE

-

[8] Severns and Bloom, Modern DC-to-DC Switchmode

Power Converter Circuits, Van Nostrand Reinhold, 1985

FIGURE 42. OFF LINE CASCODE SEPIC

[9] Sum, K., Switch Mode Power Conversion - Basic Theory

and Design, Marcel Dekker, In., 1984

Figure 43 shows the voltage transfer as a function of duty

cycle for the power supply topologies discussed.

[10] Pressman, A., Switching and Linear Power Supply,

Power Converter Design, Hayden Book Co., 1977

100

[11] Massey, R.P. and Snyder, E.C., High Voltage Single-

Ended DC-DC Converter, IEEE Power Electronics Spe-

cialists Conference (PESC) record, 1977, pp. 156-159

BUCK-BOOST, CUK AND SEPIC

M = D/(1-D)

10

[12] Clarke, P., A New Switched-Mode Power Conversion

Topology Provides Inherently Stable Response, POWER-

CON 10 proceedings, March 1983, pp. E2-1 through E2-7

M = 1/(1 - D) BOOST

1

[13] Intersil Application Notes AN9208 and AN9212.1

0.1

BUCK

M = D

QUADRATIC

M = D²/(1 - D)²

0.01

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

DUTY CYCLE (D)

FIGURE 43. VOLTAGE TRANSFER AS A FUNCTION OF DUTY

CYCLE FOR VARIOUS TOPOLOGIES

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

7-72


型号：	HIP5061DS
厂家：	Intersil
描述：	7A, High Efficiency Current Mode Controlled PWM Regulator 7A ，高效电流模式控制PWM稳压器稳压器开关局域网
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