HM1-65642883 [INTERSIL]
8K x 8 Asynchronous CMOS Static RAM; 8K ×8的异步CMOS静态RAM
| 型号： | HM1-65642883 |
| 厂家： | 
Intersil |
| 描述： | 8K x 8 Asynchronous CMOS Static RAM |
| 文件： | 总9页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM-65642/883
8K x 8 Asynchronous
CMOS Static RAM
March 1997
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HM-65642/883 is a CMOS 8192 x 8-bit Static Random
Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide
standard, which allows easy memory board layouts which
accommodate a variety of industry standard ROM, PROM,
EPROM, EEPROM and RAMs. The HM-65642/883 is ideally
suited for use in microprocessor based systems. In particu-
lar, interfacing with the Intersil 80C86 and 80C88 micropro-
cessors is simplified by the convenient output enable (G)
input.
• Full CMOS Design
• Six Transistor Memory Cell
• Low Standby Supply Current . . . . . . . . . . . . . . . .100µA
• Low Operating Supply Current. . . . . . . . . . . . . . . 20mA
• Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns
• Low Data Retention Supply Voltage. . . . . . . . . . . . 2.0V
• CMOS/TTL Compatible Inputs/Outputs
• JEDEC Approved Pinout
The HM-65642/883 is a full CMOS RAM which utilizes an
array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full mili-
tary temperature range. In addition to this, the high stability
of the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of four
transistor or MIX-MOS (4T) devices
• Equal Cycle and Access Times
• No Clocks or Strobes Required
• Gated Inputs
- No Pull-Up or Pull-Down Resistors Required
o
o
• Temperature Range -55 C to +125 C
• Easy Microprocessor Interfacing
• Dual Chip Enable Control
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
150ns/75µA
HM1-65642B/883
HM4-65642B/883
150ns/150µA
HM1-65642/883
HM4-65642/883
200ns/250µA
PKG. NO.
F28.6
o
o
-55 C to +125 C
HM1-65642C/883
-
o
o
CLCC
-55 C to +125 C
J32.A
Pinouts
HM-65642/883 (CERDIP)
TOP VIEW
HM4-65642/883 (CLCC)
TOP VIEW
1
2
28
27
26
25
24
23
22
21
20
19
18
NC
A12
A7
VCC
W
PIN
A
DESCRIPTION
Address Input
Data Input/Output
Chip Enable
Chip Enable
Write Enable
Output Enable
No Connections
Ground
1
4
3
2
32 31 30
29
28
27
26
25
5
6
A8
A9
A6
A5
3
E2
DQ
4
A6
A8
7
8
9
A11
A4
A3
A2
5
A5
A9
E1
E2
NC
G
6
A4
A11
G
7
A3
W
24 A10
23 E1
A1 10
A0 11
8
A2
A10
E1
G
9
A1
NC
GND
VCC
12
22
10
11
12
13
14
NC
DQ7
A0
DQ7
DQ6
13
21
DQ0
DQ1
DQ2
GND
DQ6
DQ0
14
15 16 17 18 19 20
17 DQ5
16 DQ4
15 DQ3
Power
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3004.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19969-220
HM-65642/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance (Typical)
θ
θ
JC
JA
o
o
Input or Output Voltage Applied for all Grades . . . . . . .GND -0.3V to
VCC +0.3V
CERDIP Package . . . . . . . . . . . . . . . . 45 C/W
CLCC Package . . . . . . . . . . . . . . . . . . 55 C/W
8 C/W
o
o
10 C/W
o
o
Typical Derating Factor. . . . . . . . . . . . 5mA/MHz Increase in ICCOP
Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175 C
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300 C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101,000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . +2.2V to VCC +0.3V
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V
Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max.
TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
LIMITS
(NOTE 1)
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
o
o
High Level Output
Voltage
VOH 1
VCC = 4.5V, IO = -1.0mA
1, 2, 3
-55 C ≤ T ≤ +125 C
2.4
-
V
A
o
o
Low Level Output
Voltage
VOL
IIOZ
VCC = 4.5V, IO = 4.0mA
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
-
0.4
V
A
o
o
High Impedance
Output Leakage
Current
HM-65642B/883, HM-65642/883
VCC = 5.5V, G = 2.2V,
VI/O = GND or VCC
-55 C ≤ T ≤ +125 C
-1.0
+1.0
µA
A
o
o
HM-65642C/883
1, 2, 3
-55 C ≤ T ≤ +125 C
-2.0
+2.0
µA
A
VCC = 5.5V, G = 2.2V,
VI/O = GND or VCC
o
o
Input Leakage
Current
II
HM-65642B/883, HM-65642/883
VCC = 5.5V, VI = GND or VCC
1, 2, 3
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
-1.0
-2.0
-
+1.0
+2.0
100
µA
µA
µA
A
o
o
HM-65642C/883
VCC = 5.5V, VI = GND or VCC
-55 C ≤ T ≤ +125 C
A
o
o
Standby Supply
Current
ICCSB1
HM-65642B/883
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V
-55 C ≤ T ≤ +125 C
A
o
o
HM-65642/883
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
-
-
250
400
µA
µA
A
o
o
HM-65642C/883
-55 C ≤ T ≤ +125 C
A
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V
o
o
Standby Supply
Current
ICCSB
ICCEN
ICCOP
VCC = 5.5V, IO = 0mA, E1 = 2.2V or
E2 = 0.8V
1, 2, 3
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
-
-
-
5
5
mA
mA
mA
A
o
o
Enable Supply
Current
VCC = 5.5V, IO = 0mA, E1 =0.8V,
E2 = 2.2V
-55 C ≤ T ≤ +125 C
A
o
o
Operating Supply
Current
VCC = 5.5V, G = 5.5V, (Note 2),
f = 1MHz, E1 = 0.8V, E2 = 2.2V
-55 C ≤ T ≤ +125 C
20
A
6-221
HM-65642/883
TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
LIMITS
(NOTE 1)
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
o
o
Data Retention
Supply Current
ICCDR
HM-65642B/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
-55 C ≤ T ≤ +125 C
-
-
-
-
75
µA
A
o
o
HM-65642/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
-55 C ≤ T ≤ +125 C
150
250
-
µA
µA
-
A
o
o
HM-65642C/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
-55 C ≤ T ≤ +125 C
A
o
o
Functional Test
NOTES:
FT
VCC = 4.5V (Note 3)
7, 8A, 8B
-55 C ≤ T ≤ +125 C
A
1. All voltages referenced to device GND.
2. Typical derating 5mA/MHz increase in ICCOP.
3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH ≥ 1.5V, and VOL ≤ 1.5V.
TABLE 2. HM-65642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
HM-
65642B/883
HM-
65642/883
HM-
65642C/883
GROUP A
SUB-
(NOTES 1, 2)
PARAMETERS
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
MIN
MAX
MIN
MAX UNITS
o
o
Read/Write/
Cycle Time
TAVAX
VCC = 4.5V and
5.5V
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C 150
-
150
-
200
-
ns
A
o
o
Address Access
Time
TAVQV
TGLQV
VCC = 4.5V and
5.5V
-55 C ≤ T ≤ +125 C
-
-
150
70
150
-
-
-
150
70
150
-
-
-
200
70
200
-
-
A
o
o
Output Enable
Access Time
VCC = 4.5V and
5.5V
-55 C ≤ T ≤ +125 C
ns
ns
ns
A
o
o
Chip Enable
Access Time
TE1LQV
TE2HQV
VCC = 4.5V and
5.5V
-55 C ≤ T ≤ +125 C
-
-
-
A
o
o
Write Recovery
Time
TWHAX
TE1HAX
TE2LAX
VCC = 4.5V and
5.5V
-55 C ≤ T ≤ +125 C
10
10
10
A
o
o
Chip Enable to
End-of-Write
TE1LE1H VCC = 4.5V and
TE2HE2L 5.5V
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
90
0
-
-
90
0
-
-
120
0
-
-
ns
ns
A
o
o
Address Setup
Time
TAVWL
TAVE1L
TAVE2H
VCC = 4.5V and
5.5V
-55 C ≤ T ≤ +125 C
A
o
o
Write Enable
Pulse Width
TWLWH
VCC = 4.5V and
5.5V
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
90
60
-
-
90
60
-
-
120
80
-
-
ns
ns
A
o
o
Data Setup Time
TDVWH
TDVE1H
TDVE2L
VCC = 4.5V and
5.5V
-55 C ≤ T ≤ +125 C
A
6-222
HM-65642/883
TABLE 2. HM-65642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
LIMITS
HM-
65642B/883
HM-
65642/883
HM-
65642C/883
GROUP A
SUB-
(NOTES 1, 2)
PARAMETERS
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
MIN
MAX
MIN
MAX UNITS
o
o
Data Hold Time
TWHDX
VCC = 4.5V and
5.5V
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
5
-
5
-
5
-
-
-
ns
ns
ns
A
o
o
TE1HDX
TE2LDX
VCC = 4.5V and
5.5V
-55 C ≤ T ≤ +125 C
10
10
-
-
10
10
-
-
10
10
A
o
o
VCC = 4.5V and
5.5V
-55 C ≤ T ≤ +125 C
A
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume transition time ≤ 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equivalent
load and CL ≥ 50pF, for CL > 50pF, access times are derated 0.15ns/pF.
TABLE 3. HM-65642/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
PARAMETER
Output High Voltage
Input Capacitance
SYMBOL
VOH2
CIN
CONDITIONS
NOTES
1
TEMPERATURE
MIN
MAX
-
UNITS
V
o
o
VCC = 4.5V, IO = -100µA
-55 C ≤ T ≤ +125 C VCC -0.4
A
o
VCC = Open, f = 1MHz, All
Measurements Refer-
enced to Device Ground
1, 2
T
= +25 C
-
-
-
-
12
pF
A
o
VCC = Open, f = 1MHz, All
Measurements Refer-
enced to Device Ground
1, 3
1, 2
1, 3
T
= +25 C
10
14
12
pF
pF
pF
A
o
I/O Capacitance
CI/O
VCC = Open, f = 1MHz, All
Measurements Refer-
enced to Device Ground
T
= +25 C
A
o
VCC = 4.5V, VI/O = GND
or VCC, All Measurements
Referenced to Device
Ground
T
= +25 C
A
o
o
Write Enable to Output in High Z
Write Enable High to Output ON
Chip Enable to Output ON
TWLQZ
TWHQX
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
1
1
1
-55 C ≤ T ≤ +125 C
-
50
-
ns
ns
ns
A
o
o
-55 C ≤ T ≤ +125 C
5
A
o
o
TE1LQX
TE2HQX
-55 C ≤ T ≤ +125 C
10
-
A
o
o
Output Enable to Output ON
TGLQX
TE1HQZ
TE2LQZ
TGHQZ
TAXQX
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
1
1
1
1
1
-55 C ≤ T ≤ +125 C
5
-
-
ns
ns
ns
ns
ns
A
o
o
Chip Enable to Output in High Z
-55 C ≤ T ≤ +125 C
50
60
50
-
A
o
o
-55 C ≤ T ≤ +125 C
-
A
o
o
Output Disable to Output in High Z
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
-55 C ≤ T ≤ +125 C
-
A
o
o
-55 C ≤ T ≤ +125 C
10
Output Hold from Address
Change
A
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design release and upon design changes which would affect these characteristics.
2. Applies to DIP device types only. For design purposes CIN = 6pF typical and CI/O = 7pF typical.
3. Applies to LCC device types only. For design purposes CIN = 4pF typical and CI/O = 5pF typical.
6-223
HM-65642/883
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
GROUPS METHOD
100%/5004
SUBGROUPS
Interim Test 1
Interim Test
PDA
-
100%/5004
1, 7, 9
100%/5004
1
Final Test 1
Group A
100%/5004
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
Samples/5005
Samples/5005
Groups C and D
6-224
HM-65642/883
1. The RAM must be kept disabled during data retention. This is ac-
Low Voltage Data Retention
complished by holding the E2 pin between -0.3V and GND.
Intersil CMOS RAMs are designed with battery backup in
mind. Data Retention voltage and supply current are guaran-
teed over the operating temperature range. The following
rules ensure data retention:
2. During power-up and power-down transitions, E2 must be held
between -0.3V and 10% of VCC.
3. The RAM can begin operating one TAVAX after VCC reaches the
minimum operating voltage of 4.5V.
DATA RETENTION MODE
VCC
4.5V
VIH
TAVAX
E2
VCCOR
GND
FIGURE 1. DATA RETENTION
Read Cycles
TAVAX
ADDRESS 1
A
Q
ADDRESS 2
TAVQV
TAXQX
DATA 1
DATA 2
FIGURE 2. READ CYCLE I: W, E2 HIGH; G, E1 LOW
TAVAX
A
TAVQV
E1
TE1LQV
TE1LQX
TE1HQZ
TE2LQZ
TGHQZ
E2
G
TE2HQV
TE2HQX
TGLQV
TGLQX
Q
FIGURE 3. READ CYCLE II: W HIGH
6-225
HM-65642/883
Write Cycles
TAVAX
A
TAVWL
TWLWH
TWHAX
W
E1
E2
TWHQX
TWHDX
TDVWH
D
Q
TWLQZ
FIGURE 4. WRITE CYCLE I: LATE WRITE
TAVAX
A
TAVE1L
TE1LE1H
TE1HAX
W
E1
E2
D
TDVE1H
TE1HDX
FIGURE 5. WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1
TAVAX
A
TAVE2H
TE2HE2L
TE2LAX
W
E1
E2
D
TDVE2L
TE2LDX
FIGURE 6. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2
6-226
HM-65642/883
Test Circuit
DUT
(NOTE 1) C
L
+
IOH
1.5V
IOL
-
EQUIVALENT CIRCUIT
NOTE:
1. Test head capacitance.
Burn-In Circuits
HM-65642/883
CERDIP
HM-65642/883
CLCC
TOP VIEW
TOP VIEW
VCC
C
C
GND
NC
A12
A7
VCC
W
1
2
28
F15
F10
F9
F8
F7
F6
F5
F4
F3
F2
F2
F2
27
26
25
24
23
22
21
20
19
18
17
16
15
F1
E2
1
4
3
2
32 31 30
3
F16
F11
F12
F14
F0
A8
A6
29
28
27
26
25
24
23
22
21
5
6
F11
F12
F9
F8
F7
F6
F5
F4
F3
A6
A8
4
A9
A5
A4
A3
A2
A1
A0
A5
A9
A11
5
7
F14
A4
A11
G
6
NC
G
8
A3
7
9
F0
F13
F0
F2
F2
A2
A10
E1
A10
E1
8
10
11
F13
F0
A1
9
DQ7
DQ6
A0
DQ7
DQ6
DQ5
DQ4
DQ3
NC 12
DQ0
10
11
12
13
14
F2
DQ0
DQ1
DQ2
GND
13
F2
F2
14 15 16 17 18 19 20
F2
F2
F2
NOTES:
NOTES:
F0 = 100kHz ±10%.
C = 0.01µF Min.
F0 = 100kHz ±10%.
All resistors 47kΩ ±5%.
C = 0.01µF Min.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
6-227
HM-65642/883
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
Type: SiO
274.0 x 302.8 x 19 ±1mils
2
Thickness: 8kÅ ±1kÅ
METALLIZATION:
Type: Si - Al
WORST CASE CURRENT DENSITY:
5
2
Thickness: 11kÅ ±2kÅ
0.9 x 10 A/cm
Metallization Mask Layout
HM-65642/883
A8
A7 A12
VCC
W
E2
A8
A9
A11
G
A5
A4
A3
A2
A1
A0
A10
E1
DQ7
DQ0 DQ1 DQ2 GND DQ3
DQ4 DQ5 DQ6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
6-228
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