HS-201HSRH_06 [INTERSIL]
Radiation Hardened High Speed, Quad SPST, CMOS Analog Switch; 抗辐射高速，四路SPST ， CMOS模拟开关
| 型号： | HS-201HSRH_06 |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened High Speed, Quad SPST, CMOS Analog Switch |
| 文件： | 总4页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-201HSRH
®
Data Sheet
March 24, 2006
FN4874.1
Radiation Hardened High Speed, Quad
SPST, CMOS Analog Switch
Features
• Electrically Screened to DSCC SMD 5962-99618
The HS-201HSRH is a monolithic CMOS analog switch
featuring power-off high input impedance, very fast switching
speeds and low ON resistance. Fabrication on our DI RSG
process assures SEL immunity and only very slight
sensitivity to low dose rate (ELDRS). These Class V/Q
devices are tested and guaranteed for 300krad (Si) total
dose performance.
• QML Qualified per MIL-PRF-38535
• Radiation Performance
- Guaranteed Total Dose Performance. . . . . 300krad (Si)
- SEL Immune. . . . . . . . . . . . . . . . . . . . .DI RSG Process
• Overvoltage Protection (Power On, Switch Off) . . . . . . ±30V
• Power Off High Impedance . . . . . . . . . . . . . . . . . . . ±17V
• Fast Switching Times
Power-off high input impedance enables the use of this
device in redundant circuits without causing data bus signal
degradation. ESD protection, overvoltage protection, fast
switching times, low ON resistance, and guaranteed
radiation hardness, make the HS-201HSRH ideal for any
space application where improved switching performance is
required.
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110ns (Max)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80ns (Max)
ON
OFF
• Low “ON” Resistance . . . . . . . . . . . . . . . . . . . 50Ω (Max)
• Pin Compatible with Industry Standard 201 Types
• Operating Supply Range . . . . . . . . . . . . . . . . . ±10V to ±15V
• Wide Analog Voltage Range (±15V Supplies) . . . . . . . ±15V
• TTL Compatible
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center (DSCC). The SMD numbers
listed here must be used when ordering flight units.
Detailed electrical specifications for this device are
contained in SMD 5962-99618. A ”hot-link” is provided
on our homepage for downloading.
Applications
• High Speed Multiplexing
• Sample and Hold Circuits
• Digital Filters
www.intersil.com/spacedefense/space.asp
Pinout
HS1-201HSRH, SBDIP (CDIP2-T16)
HS9-201HSRH, FLATPACK (CDFP4-F16)
TOP VIEW
• Operational Amplifier Gain Switching Networks
• Integrator Reset Circuits
A1
OUT1
IN1
1
2
3
4
5
6
7
8
16 A2
15 OUT2
14 IN2
13 V+
V-
GND
IN4
12 NC
11 IN3
10 OUT3
OUT4
A4
9
A3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HS-201HSRH
Ordering Information
INTERNAL
TEMP. RANGE
(°C)
ORDERING NUMBER
MKT. NUMBER
PART MARKING
Q 5962F9961801VEC
Q 5962F9961801QEC
Q 5962F9961801VXC
Q 5962F9961801QXC
-
PACKAGE
16 Ld SBDIP
16 Ld SBDIP
16 Ld Flatpack
16 Ld Flatpack
-
PKG. DWG. #
D16.3
D16.3
K16.A
K16.A
-
5962F9961801VEC
5962F9961801QEC
5962F9961801VXC
5962F9961801QXC
5962F9961801V9A
HS1-201HSRH/PROTO
HS9-201HSRH/PROTO
HS1-201HSRH-Q
HS1-201HSRH-8
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
HS9-201HSRH-Q
HS9-201HSRH-8
HS0-201HSRH-Q
HS1-201HSRH/PROTO
HS9-201HSRH/PROTO
HS1-201HSRH/PROTO
HS9-201HSRH/PROTO
16 Ld SBDIP
16 Ld Flatpack
D16.3
K16.A
Die Characteristics
DIE DIMENSIONS
Backside Finish
Silicon
2790µm x 4950µm (110 mils x 195 mils)
Thickness: 483µm ±25.4µm (19 mils ±1 mil)
ASSEMBLY RELATED INFORMATION
INTERFACE MATERIALS
Glassivation
Substrate Potential
Unbiased (DI)
Type: Phosphorus Silicon Glass (PSG)
Thickness: 8.0kÅ +/-1.0kÅ
ADDITIONAL INFORMATION
Worst Case Current Density
Metallization
Type: Ti/AlCu
Thickness: 16.0kÅ +/- 2kÅ
5
2
<2.0 x 10 A/cm
Transistor Count
328
Substrate
Rad Hard Silicon Gate, Dielectric Isolation
Metallization Mask Layout
HS-201HSRH
OUT4
IN4
GND
V-
IN1
OUT1
A1
A2
A4
A3
OUT3
IN3
V+
IN2
OUT2
FN4874.1
March 24, 2006
2
HS-201HSRH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K16.A MIL-STD-1835 CDFP4-F16 (F-5A, CONFIGURATION B)
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
A
e
INCHES MILLIMETERS
MIN
PIN NO. 1
ID AREA
SYMBOL
MAX
0.115
0.022
0.019
0.009
0.006
0.440
0.285
0.315
-
MIN
1.14
0.38
0.38
0.10
0.10
-
MAX
2.92
0.56
0.48
0.23
0.15
11.18
7.24
8.00
-
NOTES
D
A
b
0.045
0.015
0.015
0.004
0.004
-
-
-
-A-
-B-
S1
b1
c
-
-
b
c1
D
-
E1
3
-
0.004
Q
H
A - B
D
0.036
H
A - B
D
S
M
S
S
M
S
C
E
0.245
6.22
E
E1
E2
E3
e
-
-
3
-
-D-
A
0.130
0.030
3.30
0.76
-H-
-C-
-
-
7
-
L
E2
L
E3
E3
0.050 BSC
1.27 BSC
SEATING AND
BASE PLANE
c1
LEAD FINISH
k
0.008
0.250
0.026
0.005
-
0.015
0.370
0.045
-
0.20
6.35
0.66
0.13
-
0.38
9.40
1.14
-
2
-
L
BASE
METAL
Q
S1
M
N
8
6
-
(c)
b1
0.0015
0.04
M
M
(b)
16
16
-
SECTION A-A
Rev. 1 2-20-95
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
FN4874.1
3
March 24, 2006
HS-201HSRH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 LEAD FINISH
D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-A-
-D-
E
INCHES MILLIMETERS
MIN
-
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.840
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
21.34
7.87
NOTES
b1
M
(b)
A
b
-
M
A
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
S
S
S
D
bbb
C
A - B
-
D
4
BASE
S2
Q
PLANE
2
-C-
SEATING
PLANE
c1
D
3
L
-
S1
b2
eA
A A
E
0.220
5.59
-
e
eA/2
aaa M C A - B S D S
b
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
M
C A - B S D S
-
NOTES:
0.125
0.200
3.18
5.08
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
Q
0.015
0.005
0.005
0.060
0.38
0.13
0.13
1.52
5
S1
S2
α
-
-
-
-
6
7
o
o
o
o
90
105
90
105
-
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
-
M applies to lead plating and finish thickness.
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
2
8
N
16
16
5. Dimension Q shall be measured from the seating plane to the
Rev. 0 4/94
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4874.1
4
March 24, 2006
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