HS-81C55RH_00 [INTERSIL]
Radiation Hardened 256 x 8 CMOS RAM; 抗辐射256 ×8 CMOS RAM
| 型号： | HS-81C55RH_00 |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened 256 x 8 CMOS RAM |
| 文件： | 总11页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-81C55RH, HS-81C56RH
TM
Data Sheet
August 2000
File Number 3039.2
Radiation Hardened 256 x 8 CMOS RAM
Features
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
• Electrically Screened to SMD # 5962-96766
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened EPI-CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
8
- Transient Upset. . . . . . . . . . . . . . . . . .>1 x 10 rad(Si)/s
12
- Latch-Up Free. . . . . . . . . . . . . . . . . .>1 x 10 rad(Si)/s
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system.
The RAM portion is designed as 2048 static cells organized
as 256 x 8. A maximum post irradiation access time of
500ns allows the HS-81C55/56RH to be used with the
HS-80C85RH CPU without any wait states. The
HS-81C55RH requires an active low chip enable while the
HS-81C56RH requires an active high chip enable. These
chips are designed for operation utilizing a single 5V power
supply.
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
• Low Standby Current . . . . . . . . . . . . . . . . . . . .200µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . . . . 2mA/MHz
• Completely Static Design
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
• Internal Address Latches
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96766. A “hot-link” is provided
on our homepage for downloading.
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
http://www.intersil.com/spacedefense/space.asp
Ordering Information
o
o
• Military Temperature Range . . . . . . . . . . . -55 C to 125 C
INTERNAL
MKT. NUMBER
TEMP. RANGE
o
Functional Diagram
ORDERING NUMBER
5962R9676601QXC
5962R9676601QYC
5962R9676601VXC
5962R9676601VYC
5962R9676602QXC
5962R9676602QYC
5962R9676602VXC
5962R9676602VYC
( C)
HS1-81C55RH-8
HS9-81C55RH-8
HS1-81C55RH-Q
HS9-81C55RH-Q
HS1-81C56RH-8
HS9-81C56RH-8
HS1-81C56RH-Q
HS9-81C56RH-Q
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PORT A
IO/M
256 x 8
STATIC
RAM
8
PA0 - PA7
PB0 - PB7
PC0 - PC5
A
B
C
AD0 - AD7
CE OR CE†
ALE
PORT B
8
RD
PORT C
8
WR
RESET
TIMER
VDD (10V)
GND
TIMER CLK
TIMER OUT
† 81C55RH = CE
81C56RH = CE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1
HS-81C55RH, HS-81C56RH
Pinouts
40 LEAD DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INTERSIL OUTLINE K42.A
MIL-STD-1835 CDIP2-T40
TOP VIEW
TOP VIEW
1
2
3
4
40
39
38
37
36
35
PC3
PC4
VDD
PC2
PC1
PC0
PB7
PB6
PC3
PC4
1
2
3
4
42
41
40
39
VDD
PC2
PC1
PC0
PB7
TIMER IN
RESET
TIMER IN
RESET
PC5
TIMER OUT
IO / M
5
6
7
8
9
PC5
5
6
38
37
TIMER OUT
PB6
PB5
PB4
PB3
PB2
PB1
34 PB5
IO/M
7
8
36
35
CE OR CE
CE or CE†
RD
33
PB4
RD
WR
9
34
33
32
31
30
29
28
27
32
PB3
10
11
12
13
14
15
16
WR 10
ALE
31
30
29
28
27
26
25
24
PB2
PB1
ALE
AD0
AD1
AD2
AD3
NC
11
AD0 12
PB0
PA7
PA6
PB0
PA7
PA6
PA5
PA4
PA3
13
14
15
16
17
AD1
AD2
PA5
NC
AD3
AD4
AD5
PA4
AD4
AD5
AD6
17
18
19
26
25
24
PA3
PA2
PA1
PA0
AD6 18
AD7 19
GND 20
23 PA2
22 PA1
21 PA0
AD7
20
21
23
22
GND
† 81C55RH = CE
81C56RH = CE
2
HS-81C55RH, HS-81C56RH
Pin Descriptions
SYMBOL
TYPE
NAME AND FUNCTION
RESET
I
Reset: Pulse provided by the HS-80C85RH to initialize the system (connect to HS-80C85RH RESET OUT).
Input high on this line resets the chip and initializes the three I/O ports to input mode. The width of RESET
pulse should typically be two HS-80C85RH clock cycle times.
AD0 - AD7
I/O
Address/Data: Three-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. The
8-bit address is latched into the address latch inside the HS-81C55 and HS-81C56RH on the falling edge of
ALE. The address can be either for the memory section or the I/O section depending on the IO/M input. The
8-bit data is either written into the chip or read from the chip, depending on the WR or RD input signal.
CE or CE
RD
I
I
Chip Enable: On the HS-81C55RH, this pin is CE and is ACTIVE LOW. On the HS-81C56RH, this pin is CE
and is ACTIVE HIGH.
Read Control: Input low on this line with the Chip Enable active enables and AD0 - AD7 buffers. If IO/M pin
is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O port or
command/status registers will be read to the AD bus.
WR
I
I
Write Control: Input low on this line with the Chip Enable active causes the data on the Address/Data bus to
be written to the RAM or I/O ports and command/status register, depending on IO/M.
ALE
Address Latch Enable: This control signal latches both the address on the AD0 - AD7 lines and the state of
the Chip Enable and IO/M into the chip at the falling edge of ALE.
IO/M
I
I/O Memory: Selects memory if low and I/O and command/status registers if high.
PA0 - PA7 (8)
I/O
Port A: These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the
command register.
PB0 - PB7 (8)
PC0 - PC7 (8)
I/O
I/O
Port B: These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the
command register.
Port C: These 6 pins can function as either input port, output port, or as control signals for PA and PB.
Programming is done through the command register. When PC0 - PC5 are used as control signals, they will
provide the following:
PC0 - A INTR (Port A Interrupt)
PC1 - ABF (Port A Buffer Full)
PC2 - A STB (Port A Strobe)
PC3 - B INTR (Port B Interrupt)
PC4 - B BF (Port B Buffer Full)
PC5 - B STB (Port B Strobe)
TIMER IN
TIMER OUT
VDD
I
O
I
Timer Input: Input to the counter-timer.
Timer Output: This output can be either a square wave or a pulse, depending on the timer mode.
Voltage: +5V.
GND
I
Ground: Ground reference.
3
HS-81C55RH, HS-81C56RH
Waveforms
READ
CE (81C55RH)
OR
CE (81C56RH)
IO/M
tAD
AD
0-7
ADDRESS
DATA VALID
tAL
tLA
ALE
RD
tLL
tRIDE
tRDF
tRD
tCL
tRV
tLC
tCC
WRITE
CE (81C55RH)
OR
CE (81C56RH)
IO/M
AD
0-7
ADDRESS
DATA VALID
tAL
tLA
tDW
tCL
ALE
WR
tLL
tLC
tWD
tCL
tCC
tRV
4
HS-81C55RH, HS-81C56RH
Waveforms (Continued)
STROBED INPUT
BF
tSBF
STROBED
INTR
tRBE
tSS
tSI
tRDI
RD
tPSS
tPHS
INPUT DATA
FROM PORT
STROBED OUTPUT
BF
tSBE
STROBE
INTR
tSI
tWBF
tWI
WR
tWP
OUTPUT DATA
TO PORT
5
HS-81C55RH, HS-81C56RH
Waveforms (Continued)
BASIC INPUT
RD
BASIC INPUT
RD
tRP
tWP
tPR
INPUT
INPUT
DATA BUS
DATA BUS
TIMER OUTPUT COUNTDOWN FROM 5 TO 1
LOAD COUNTER CLR
RELOAD COUNTER CLR
2
1
5
4
3
2
1
5
tF
t2
TIMER IN
t1
tR
tCYC
TIMER OUT
(PULSE)
(NOTE 1)
tTL
tTH
TIMER OUT
(SQUARE WAVE)
(NOTE 1)
tTL
tTH
NOTE: THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC
RELOAD MODE (M, MODE BIT = 1)
The 8-bit address on the Address/Data lines, Chip Enable
input CE or CE and IO/M are all latched on-chip at the falling
edge of ALE.
Functional Description
The HS-81C55RH and 81C56RH contains the following:
• 2K Bit Static RAM Organized as 256 x 8
• Two 8-Bit I/O Ports (PA and PB) and One 6-Bit I/O Port
(PC)
8-BIT INTERNAL DATA BUS
• 14-Bit Timer-Counter
The IO/M (IO/Memory Select) pin selects either the five
register (Command, Status, PA0 - PA7, PB0 - PB7, PC0 -
PC5) or the memory (RAM) portion.
PC
PB
PA
COMMAND
STATUS
TIMER
MSB
TIMER
LSB
6
8
8
TIMER MODE
FIGURE 1. INTERNAL REGISTERS
6
HS-81C55RH, HS-81C56RH
Reading the Status Register
The status register consists of seven latches, one for each
bit six (0-5) for the status of the ports and one (6) for the
status of the timer.
CE (81C55RH)
OR
CE (81C56RH)
The status of the timer and the I/O section can be polled by
reading the Status Register (Address XXXXX000). Status
word format is shown in Figure 4. Note that you may never
write to the status register since the command register
shares the same I/O address and the command register is
selected when a write to that address is issued.
IO/M
AD0 - AD7
ALE
ADDRESS
DATA
VALID
RD OR WR
AD7 AD6
TIMER
AD5 AD4 AD3 AD2 AD1 AD0
INTE
B
B
BF
INTR INTE
A
BF
INTR
A
B
A
FIGURE 2. ON-BOARD MEMORY READ/WRITE CYCLE
PORT A
INTERRUPT
REQUEST
Programming of the Command Register
PORT A BUFFER
FULL/EMPTY
The command register consists of eight latches. Four bits (0-
3) define the mode of the ports, two bit (4-5) enable or disable
the interrupt from port C when it acts as control port, and the
last two bits (6-7) are for the timer.
(INPUT/OUTPUT)
PORT A INTERRUPT ENABLE
PORT B INTERRUPT REQUEST
PORT B BUFFER FULL/EMPTY
(INPUT/OUTPUT)
The command register contents can be altered at anytime by
using the I/O address XXXXX000 during a WRITE operation
with the Chip Enable active and IO/M = 1. The meaning of
each bit of the command byte is defined in Figure 3. The
contents of the command register may never be read.
PORT B INTERRUPT ENABLE
TIMER INTERRUPT (THIS BIT IS LATCHED HIGH WHEN
TERMINAL COUNT IS REACHED, AND IS RESET TO LOW
READING OF THE C/S REGISTER & BY HARDWARE RESET).
FIGURE 4. STATUS REGISTER BIT ASSIGNMENT
7
6
5
4
3
2
1
0
Input/Output Section
TM2 TM1 IEB IEA PC2 PC1 PB PA
The I/O section of the HS-81C55RH and HS-81C56RH
consists of five registers: (See Figure 5)
DEFINES
PA0 - PA7
• Command/Status Register (C/S) - Both register are
assigned the address XXXXX000. The C/S address
serves the dual purpose.
0 = INPUT
1 = OUTPUT
DEFINES
PB0 - PB7
00 = ALT1
11 = ALT2
01 = ALT3
10 = ALT4
When the C/S registers are selected during WRITE
operation, a command is written into the command
register. The contents of this register are not accessible
through the pins.
DEFINES
PC0 - PC5
ENABLE PORT
A INTERRUPT
0 = INPUT
1 = OUTPUT
ENABLE PORT
B INTERRUPT
When the C/S (XXXXX000) is selected during a READ
operation, the status information of the I/O ports and
the timer becomes available on the AD0 - AD7 lines.
00 = NOP - DO NOT AFFECT COUNTER
OPERATION
01 = STOP - NOP IF TIMER HAS NOT
STARTED; STOP COUNTING IF
THE TIMER IS RUNNING
• PA Register - This register can be programmed to be
either input or output ports depending on the status of
the contents of the C/S Register. also depending on the
command, this port can operate in either the basic
mode or the strobed mode (See timing diagram). the
I/O pins assigned in relation to this register are PA0 -
PA7. The address of this register is XXXXX001.
10 = STOP AFTER TC - STOP IMME-
DIATELY AFTER PRESENT TC
IS REACHED (NOP IF TIMER
HAS NOT STARTED)
TIMER
COMMAND
11 = START - LOAD MODE AND CNT
LENGTH AND START IMMEDIATE-
LY AFTER LOADING (IF TIMER IS
NOT PRESENTLY RUNNING). IF
TIMER IS RUNNING, START THE
NEW MODE AND CNT LENGTH
IMMEDIATELY AFTER PRESENT
TC IS REACHED.
• PB Register - This register functions the same as PA
Register. the I/O pins assigned are PB0 - PB7. The
address of this register is XXXXX010
• PC Register - This register has the address
XXXXX011 and contains only 6 bits. The 6 bits can be
programmed to be either input ports, output ports or as
FIGURE 3. COMMAND REGISTER BIT ASSIGNMENT
7
HS-81C55RH, HS-81C56RH
control signals for PA and PB by properly programming
the AD2 and AD3 bits of the C/S register.
When in the ALT1 or ALT2 modes, the bits of Port C are
structured like the diagram above in the simple input or
output mode, respectively.
When PC0 - PC5 is used as a control port, 3 bits are
assigned for Port A and 3 for Port B. The first bit is an
Interrupt that the HS-81C55RH and HS-81C56RH sends
out. The second is an output signal indicating whether the
buffer is full or empty, and the third is an input pin to
accept a strobe for the strobed input mode. (See Table 1).
Reading from an input port with nothing connected to the
pins will provide unpredictable results.
When the ‘C’ port is programmed to either ALT3 or ALT4, the
control signals for PA and PB are initialized as follows:
CONTROL
BF
INPUT MODE
Low
OUTPUT MODE
Low
INTR
Low
High
STB
Input Control
Input Control
I/O ADDRESS†
A7 A6 A5 A4 A3 A2 A1 A0
SELECTION
X
X
X
X
X
0
0
0
Interval Command/
Status Register
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
0
1
General Purpose I/O Port A
General Purpose I/O Port B
General Purpose I/O or
Control Port C
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
1
Low-Order 8 Bits of
Timer Count
High 6 Bits of Timer Count
and 2 Bits of Timer Mode
† I/O Address must be qualified by CE = 1(81C56RH) or CE =
0(81C55RH) and IO/M = 1 in order to select the appropriate register.
X = Don’t Care
FIGURE 5. I/O PORT AND TIMER ADDRESSING SCHEME
Figure 6 shows how I/O Ports A and B are structured within
the HS-81C55RH and HS-81C56RH.
Note in the diagram that when the I/O ports are programmed
to be output ports, the contents of the output ports can still
be read by a READ operation when appropriately
addressed.
The outputs of the HS-81C55/56RH are “glitch-free”
meaning that you can write a “1” to a bit position that was
previously “1” and the level at the output pin will not change.
Note also that the output latch is cleared when the port
enters the input mode. the output latch cannot be loaded by
writing to the port if the port is in the input mode. The result
is that each time a port mode is changed from input to
output, the output pins will go low. When the HS-
81C55/56RH is RESET, the output latches are all cleared
and all 3 ports enter the input mode.
8
HS-81C55RH, HS-81C56RH
HS-81C55RH AND HS-81C56RH
ONE BIT OF PORT A OR PORT B
(1) OUTPUT MODE
(2) SIMPLE INPUT
(3) STROBED INPUT
MULTIPLEXER
CONTROL
OUTPUT
LATCH
D
Q
(4) = 1 FOR OUTPUT MODE
= 0 FOR INPUT MODE
CLK
CLR
PA/PB
PIN
WRITE
PORT
(1)
MUX
MODE (4)
(2)
(3)
NOTES:
LATCH
1. READ Port = (IO/M = 1)(RD = 0)(CE Active)
(Port Address Selected)
Q
D
READ
PORT
CLK
2. WRITE Port = (IO/M = 1)(wr = 0)(CE Active)
(Port Address Selected)
STB
FIGURE 6. HS-81C55RH AND HS-81C56RH PORT FUNCTION
Figure 7 shows how the HS-81C55/56RH I/O ports might be
configured in a typical system.
TO HS-80C85RH
RST INPUT
PORT A OUTPUT
PORT A
Timer Section
A INTR (SIGNAL DATA RECEIVED)
A BF (SIGNALS DATA READY)
A STB (ACKNOWL. DATA RCV’D)
B STB (LOAD PORT B LATCH)
B BF (SIGNALS BUFFER IS FULL)
The timer is a 14-bit down counter that counts the TIMER IN
pulses and provides either a square wave or pulse when
terminal count (TC) is reached.
TO/FROM
PERIPHERAL
INTERFACE
PORT C
The timer has the I/O address XXXXX100 for the low order
byte of the register and the I/O address XXXXX101 for the
high order byte of the register. (See Figure 5).
B INTR (SIGNALS BUFFER
READY FOR READING)
To program the timer, the COUNT LENGTH REG is loaded
first, one byte at a time, by selecting the timer addresses.
Bits 0-13 of the high order count register will specify the
length of the next count and bits 14-15 of the high order
register will specify the timer output mode (see Figure 8).
The value loaded into the count length register can have any
value from 2H through 3FFH in Bits 0-13.
TO INPUT PORT
(OPTIONAL)
PORT B
INPUT
TO HS-80C85RH
RST INPUT
FIGURE 7. EXAMPLE: COMMAND REGISTER = 00111001
7
6
5
4
3
2
1
0
M2 M1 T13 T12 T11 T10 T9 T8
TIMER
MODE
MSB OF
CNT LENGTH
7
6
5
4
3
2
1
0
T7
T6
T5
T4
T3
T2
T1
T0
LSB OF
CNT LENGTH
FIGURE 8. TIMER FORMAT
There are four modes to choose from: M2 and M1 define the
timer mode, as shown in Figure 9.
9
HS-81C55RH, HS-81C56RH
Please note that the timer circuit on the HS-81C55/56RH
TIMER OUT WAVEFORMS:
chip is designed to be a square-wave timer, not an event
counter. To achieve this, it counts down by twos twice in
completing one cycle. Thus, its registers do not contain
values directly representing the number of TIMER IN pulses
received. You cannot load an initial value of 1 into the count
register and cause the timer to operate, as its terminal count
value is 10 (binary) or 2 (decimal). (For the detection of
single pulses, it is suggested that one of the hardware
interrupt pins on the HS-80C85RH be used.) After the timer
has started counting down, the values residing in the count
registers can be used to calculate the actual number of
TIMER IN pulses required to complete the timer cycle if
desired. To obtain the remaining count, perform the following
operations in order:
START TERMINAL (TERMINAL
COUNT COUNT COUNT)
MODE BITS
M2 M1
0
0
1. SINGLE SQ.
WAVE
2. CONTINUOUS
SQ. WAVE
0
1
1
0
3. SINGLE PULSE
ON TERM. COUNT
1
1
4. CONTINUOUS
PULSES
FIGURE 9. TIMER MODES
Bits 6-7 (TM2 and TM1) of command register contents are
used to start and stop the counter. there are four commands
to choose from:
1. Stop the count
2. Read in the 16-bit value from the count length registers
3. Reset the upper two mode bits
TM2
TM1
4. Reset the carry and rotate right one position all 16 bits
through carry
0
0
0
1
NOP - Do not affect counter operation
5. If carry is set, add 1/2 of the full original count (1/2 full
count - 1 if full count is odd).
STOP-NOP - If timer has not started; stop
counting if the timer is running
NOTE: If you started with an odd count and you read the
count length register before the third count pulse occurs, you
will not be able to discern whether one or two counts has
occurred. Regardless of this, the HS-81C55/56RH always
counts out the right number of pulses in generating the
TIMER OUT waveforms.
1
1
0
1
STOP AFTER TC - Stop immediately after
present TC is reached (NOP if timer has not
started)
START - Load mode and CNT length and start
immediately after loading (if timer is not
presently running). If timer is running, start the
new mode and CNT length immediately after
present TC is reached.
Note that while the counter is counting, you may load a new
count and mode into the count length registers. Before the
new count and mode will be used by the counter, you must
issue a START command to the counter. This applies even
thought you may only want to change the count and use the
previous mode.
In case of an odd-numbered count, the first half-cycle of the
squarewave output, which is high, is one count longer than
the second (low) half-cycle, as shown in Figure 10.
4
5
FIGURE 10. ASYMMETRICAL SQUARE-WAVE OUTPUT
RESULTING FROM COUNT OF 9
The counter in the HS-81C55/56RH is not initialized to any
particular mode or count when hardware RESET occurs, but
RESET does stop the counting. Therefore, counting cannot
begin following RESET until a START command is issued
via the C/S register.
10
HS-81C55RH, HS-81C56RH
Die Characteristics
DIE DIMENSIONS:
Substrate:
222mils x 202mils x 14mils ± 1mil (Die Thickness)
INTERFACE MATERIALS:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Glassivation:
Silicon
Type: SiO2
Thickness: 8kÅ ± 1kÅ
ASSEMBLY RELATED INFORMATION:
Top Metallization:
Substrate Potential:
Type: AlSi
Unbiased (DI)
Thickness: 11kÅ ± 2kÅ
Metallization Mask Layout
HS-81C55RH, HS-81C56RH
TIMER OUT (6)
IO/M (7)
(34) PB5
CE OR CE (8)
RD (9)
(33) PB4
(32) PB3
WR (10)
ALE (11)
(31) PB2
(30) PB1
AD0 (12)
(29) PB0
(28) PA7
AD1 (13)
AD2 (14)
(27) PA6
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11
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