HS0-82C12RH-Q [INTERSIL]
Radiation Hardened 8-Bit Input/Output Port; 抗辐射的8位输入/输出端口
| 型号： | HS0-82C12RH-Q |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened 8-Bit Input/Output Port |
| 文件： | 总6页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-82C12RH
TM
Data Sheet
August 2000
File Number 3041.3
Radiation Hardened 8-Bit Input/Output
Port
Features
• Electrically Screened to SMD # 5962-95818
The Intersil HS-82C12RH is a radiation hardened 8-bit
input/output port designed for use with the HS-80C85RH
radiation hardened microprocessor. It is manufactured using
a self-aligned, junction-isolated EPI-CMOS process and
features three-state output buffers and device selection and
control logic. A service request flip-flop is included for the
generation and control of interrupts to the microprocessor.
The device can be used in implement many of the peripheral
and input/output functions of a microcomputer system. The
HS-82C12RH is pinout- and function- compatible with
industry-standard 8212 devices.
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Performance
- Hardened EPI-CMOS Process
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
8
- Transient Upset. . . . . . . . . . . . . . . . . > 1 x 10 rad(Si)/s
- Latch-Up Immune
• Low Power Dissipation
• High Noise Immunity
• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V
• Low Input Load Current
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
• 8-Bit Data Register and Buffer
• Asynchronous Register Clear
• Service Request Flip-Flop for Interrupt Generation
• Three-State Outputs
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95818. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
• Bus-Compatible with HS-80C85RH CPU
• Electrically Equivalent to Sandia SA3026
Ordering Information
o
o
INTERNAL
MKT. NUMBER
TEMP. RANGE
• Military Temperature Range . . . . . . . . . . . -55 C to 125 C
o
ORDERING NUMBER
5962R9581801QJC
5962R9581801QXC
5962R9581801V9A
5962R9581801VJC
5962R9581801VXC
( C)
Functional Diagram
HS1-82C12RH-8
HS9-82C12RH-8
HS0-82C12RH-Q
HS1-82C12RH-Q
HS9-82C12RH-Q
-55 to 125
-55 to 125
25
DS1
SERVICE
REQUEST
F.F.
2
3
CONTROL
AND
DS2
STB
CLR
MD
INT
DEVICE
SELECT
LOGIC
-55 to 125
-55 to 125
DATA
LATCH
AND
BUFFER
(8)
DI0-7
DO0-7
Pin Description
PIN
DI0-DI7
DO0-DO7
DS1, DS2
MD
DESCRIPTION
Data In
Data Out
Device Select
Mode
STB
Strobe
INT
Interrupt
Clear
CLR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1
HS-82C12RH
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
DS1
MD
1
2
3
4
5
6
7
8
9
24
VDD
23 INT
22 DI7
21 DO7
20 DI6
19 DO6
18 DI5
17 DO5
16 DI4
15 DO4
14 CLR
13 DS2
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3 10
STB 11
GND 12
24 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
1
24
23
22
21
20
19
18
17
16
15
14
13
DS1
MD
VDD
INT
2
3
DI7
DI0
4
DO7
DI6
DO0
DI1
5
6
DO6
DI5
DO1
DI2
7
8
DO5
DI4
DO2
DI3
9
DO4
CLR
DS2
10
11
12
DO3
STB
GND
2
HS-82C12RH
Timing Waveforms
(DS, • DS2)
tE
0.5VDD
tD
VOH
VOL
OUTPUT
0.5VDD
FIGURE 1. READ TIMING
DATA
tPW
tWE
tH
MD OR (DS, • DS2)
OUTPUT
FIGURE 2. WRITE TIMING
DATA
tSET
tH
STB OR (DS, • DS2)
tPD
OUTPUT
FIGURE 3. DATA SETUP, HOLD, PROPAGATION DELAY TIMING
tPW
STB
tPW
(DS, • DS2)
tR
tS
INT
FIGURE 4. INTERRUPT TIMING
tPW
tC
CLR
DO
FIGURE 5. CLEAR TIMING
3
HS-82C12RH
Functional Description
Data Latch
Mode
The data latch is comprised of eight “D” type flip-flops. The
output of each flip-flop will follow the corresponding data
input (DI0 - DI7) when the clock (C) is high. The clock input
is level sensitive and the data becomes latched when the
clock returns low.
the mode input (MD) is used to control the state of the output
buffer and to determine the source of the data latch clock
(C). When MD is high, the output buffers are enabled and
the source of the data latch clock (C) is the device select
logic (DS1 • DS2).
An asynchronous reset (CLR) is used to clear the latched
data. Since the clock (C) overrides the reset (CLR), the data
must be in the latched state in order to clear the flip-flops. If
the data is not latched (i.e. clock is high) when CLR goes
low, then the Q outputs of the data latch will continue to
follow the data input, overriding the reset signal.
When MD is low, the state of the output buffer is controlled
by the device select logic (DS1 • DS2) and the source of the
data latch clock is the strobe (STB) input.
Strobe
The strobe input (STB) is used as the data latch clock (C)
when the mode input (MD) is low. The service request flip-
flop is synchronously set on the negative going edge of STB.
Output Buffer
Three-state buffers are used to provide output drive for the
data latch. A high level on the “output buffer enable” control
line enables the buffer outputs. When “output buffer enable”
is low the buffer outputs are forced to the high-impedance
state.
Service Request Flip-Flop
The service request flip-flop is to generate interrupts to
microcomputer systems. It is negative edge triggered and
asynchronously cleared (reset).
The output of the service request flip-flop is AND-gated with
the device select logic (DS1 • DS2). The output of the AND
gate is the active low interrupt (INT) signal.
Device Select Logic
The inputs DS1 and DS2 are used for device selection.
When DS1 is low and DS2 is high, the device is selected.
The output buffers are enabled and the service request flip-
flop is asynchronously cleared when the device is selected.
4
HS-82C12RH
Logic Diagram
INT
23
DEVICE
DS1
DATA OUT ENABLE
LATCH RESET
SELECT
13
DI0
3
DO0
4
DS2
D
E
Q
Q
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
S
R
R
R
R
R
R
R
R
D
C
Q
Q
STB
SERVICE
REQUEST
FLIP-FLOP
DI1
5
DO1
6
11
D
E
Q
Q
CLR
14
DI2
7
DO2
8
D
E
Q
Q
LATCH CLOCK
DI3
9
DO3
10
D
E
Q
Q
MD
2
DI4
16
DO4
15
D
E
Q
Q
DI5
18
DO5
17
D
E
Q
Q
DI6
20
DO6
19
D
E
Q
Q
DI7
22
DO7
21
D
E
Q
Q
TABLE 1. DATA OUT
TABLE 2. INT
STB
0
MD
0
DS1 • DS2
DATA OUT EQUALS
High Z State
High Z State
Data Latch
Data Latch
Data Latch
Data In
(NOTE)
CLR
DS1 • DS2
STB
Q
INT
1
0
0
0
0
1
1
1
1
0 RESET
0
0
0
0
0
1
0
0
1
0
1
1
1
1
0
1
0
1
0
1 RESET
0
0
1
1
0
0
0
0
0
1
1
0
NOTE: Internal Service Request Flip-Flop
0
1
Data In
1
1
Data In
5
HS-82C12RH
Die Characteristics
DIE DIMENSIONS:
Substrate:
Radiation Hardened Silicon Gate,
90 mils x 76 mils x 14 mils ±1 mil
Dielectric Isolation
INTERFACE MATERIALS:
Glassivation:
Backside Finish:
Silicon
Type: SiO2
Thickness: 8kÅ ±1kÅ
ASSEMBLY RELATED INFORMATION:
Top Metallization:
Substrate Potential:
Type: AlSi
Unbiased (DI)
Thickness: 11kÅ ±2kÅ
Metallization Mask Layout
HS-82C12RH
(22) DI7
DO0 (4)
(21) DO7
(20) DI6
DI1 (5)
DO1 (6)
(19) DO6
(18) DI5
DI2 (7)
DO2 (8)
DI3 (9)
(17) DO5
(16) DI4
(15) DO4
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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6
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