HS9-26CT32RH-T [INTERSIL]

Radiation Hardened Quad Differential Line Receiver; 抗辐射四路差动线路接收器
HS9-26CT32RH-T
型号: HS9-26CT32RH-T
厂家: Intersil    Intersil
描述:

Radiation Hardened Quad Differential Line Receiver
抗辐射四路差动线路接收器

文件: 总3页 (文件大小:47K)
中文:  中文翻译
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HS-26CT32RH-T  
Data Sheet  
July 1999  
File Number 4593.1  
Radiation Hardened  
Features  
Quad Differential Line Receiver  
• QML Class T, Per MIL-PRF-38535  
Intersil’s Satellite Applications FlowTM (SAF) devices are fully  
tested and guaranteed to 100kRAD total dose. These QML  
Class T devices are processed to a standard flow intended  
to meet the cost and shorter lead-time needs of large  
volume satellite manufacturers, while maintaining a high  
level of reliability.  
• Radiation Performance  
5
- Gamma Dose . . . . . . . . . . . . . . . . . . . . 1 x 10 RAD(Si)  
2
- SEU and SEL . . . . . . . . . . Immune to 100MeV/mg/cm  
• EIA RS-422 Compatible Inputs  
• TTL Compatible Enable Inputs  
The Intersil HS-26CT32RH-T is a Quad Differential Line  
Receiver designed for digital data transmission over  
balanced lines and meets the requirements of EIA Standard  
RS-422. Radiation Hardened CMOS processing assures low  
power consumption, high speed, and reliable operation in  
the most severe radiation environments.  
• Input Fail Safe Circuitry  
• High Impedance Inputs when Disabled or Powered Down  
• Low Power Dissipation 138mW Standby (Max)  
• Single 5V Supply  
o
o
• Full -55 C to 125 C Military Temperature Range  
The HS-26CT32RH-T has an input sensitivity of 200mV (typ.)  
over the common mode input voltage range of ±7V. The  
receivers are also equipped with input fail safe circuitry, which  
causes the outputs to go to a logic “1” when the inputs are  
open. TTL compatible Enable and Disable functions are  
common to all four receivers.  
Pinouts  
HS1-26CT32RH-T (SBDIP) CDIP2-T16  
TOP VIEW  
AIN  
AIN  
1
2
3
4
5
6
7
8
16 V  
DD  
15 BIN  
Specifications  
AOUT  
ENABLE  
COUT  
CIN  
14 BIN  
Specifications for Rad Hard QML devices are controlled by  
the Defense Supply Center in Columbus (DSCC). The SMD  
numbers listed below must be used when ordering.  
13 BOUT  
12 ENABLE  
11 DOUT  
10 DIN  
Detailed Electrical Specifications for the HS-26CT32RH-T  
are contained in SMD 5962-95631. A “hot-link” is provided  
from our website for downloading.  
CIN  
9
DIN  
GND  
www.intersil.com/spacedefense/newsafclasst.asp  
Intersil’s Quality Management Plan (QM Plan), listing all  
Class T screening operations, is also available on our  
website.  
HS9-26CT32RH-T (FLATPACK), CDFP4-F16  
TOP VIEW  
www.intersil.com/quality/manuals.asp  
AIN  
AIN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
DD  
Ordering Information  
BIN  
ORDERING  
NUMBER  
PART  
NUMBER  
TEMP.  
AOUT  
ENABLE  
COUT  
CIN  
BIN  
o
RANGE ( C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
BOUT  
ENABLE  
DOUT  
DIN  
5962R9563101TEC  
HS1-26CT32RH/Proto  
5962R9563101TXC  
HS9-26CT32RH/Proto  
HS1-26CT32RH-T  
HS1-26CT32RH/Proto  
HS9-26CT32RH-T  
CIN  
GND  
DIN  
HS9-26CT32RH/Proto  
NOTE: Minimum order quantity for -T is 150 units through  
distribution, or 450 units direct.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.  
HS-26CT32RH-T  
Functional Diagram  
ENABLE ENABLE DIN DIN  
CIN CIN  
BIN BIN  
AIN AIN  
+
-
+
-
+
-
+
-
DOUT  
COUT  
BOUT  
AOUT  
TRUTH TABLE  
INPUTS  
OUTPUT  
DEVICE POWER  
ON/OFF  
ENABLE ENABLE  
INPUT  
OUT  
ON  
ON  
ON  
ON  
ON  
ON  
ON  
0
1
1
X
X
0
0
X
0
X
HI-Z  
1
VID VTH (Max)  
VID VTH (Min)  
VID VTH (Max)  
VID VTH (Min)  
Open  
1
0
X
X
1
1
0
1
X
Open  
1
2
HS-26CT32RH-T  
Die Characteristics  
DIE DIMENSIONS:  
BACKSIDE FINISH:  
2140µm x 3290µm x 533µm ±25.4µm  
(85 x 130 x 21mils ±1mil)  
Silicon  
PASSIVATION:  
METALLIZATION:  
M1: Mo/Tiw  
Type: SiO  
Thickness: 8kÅ ±1kÅ  
2
Thickness: 5800Å  
M2: Al/Si/Cu  
WORST CASE CURRENT DENSITY:  
2
< 2.0e5 A/cm  
Thickness: 10kÅ ±1kÅ  
TRANSISTOR COUNT:  
SUBSTRATE POTENTIAL:  
315  
Internally connected to V . May be left floating.  
DD  
PROCESS:  
Radiation Hardened CMOS, AVLSI  
Metallization Mask Layout  
HS-26CT32RH-T  
AIN  
(1)  
V
(16)  
BIN  
(15)  
DD  
(14) BIN  
AIN (2)  
(13) BOUT  
(12) ENAB  
AOUT (3)  
ENAB (4)  
(11) DOUT  
COUT (5)  
(10) DIN  
CIN (6)  
(7)  
CIN  
(8)  
GND  
(9)  
DIN  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com  
3

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