HS9-80C86RH_技术文档

HS-80C86RH

Radiation Hardened

16-Bit CMOS Microprocessor

September 1995

Features

Description

• Radiation Hardened

The Intersil HS-80C86RH high performance radiation

hardened 16-bit CMOS CPU is manufactured using a

hardened ﬁeld, self aligned silicon gate CMOS process. Two

modes of operation, MINimum for small systems and

MAXimum for larger applications such as multiprocessing,

allow user conﬁguration to achieve the highest performance

level. Industry standard operation allows use of existing

NMOS 8086 hardware and software designs.

- Latch Up Free EPl-CMOS

- Total Dose >100K RAD (Si)

- Transient Upset >10⁸RAD (Si)/s

• Low Power Operation

- ICCSB = 500µA (Max)

- ICCOP = 12mA/MHz (Max)

• Pin Compatible with NMOS 8086 and Intersil 80C86

• Completely Static Design DC to 5MHz

• 1MB Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word, and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

- Binary or Decimal

- Multiply and Divide

• Bus-hold Circuitry Eliminates Pull-up Resistors for

CMOS Designs

• Hardened Field, Self-Aligned, Junction-Isolated CMOS

Process

• Single 5V Power Supply

• Military Temperature Range -35^oC to +125^oC

• Minimum LET for Single Event Upset -6MEV/mg/cm²

(Typ)

Ordering Information

PART NUMBER

HS1-80C86RH-8

TEMPERATURE RANGE

SCREENING LEVEL

Intersil Class B Equivalent

Intersil Class S Equivalent

Intersil Class B Equivalent

Intersil Class S Equivalent

Sample

PACKAGE

o

-35 C to +125 C

40 Lead Braze Seal DIP

42 Lead Braze Seal Flatpack

40 Lead Braze Seal DIP

42 Lead Braze Seal Flatpack

40 Lead Braze Seal DIP

o

HS1-80C86RH-Q

-35 C to +125 C

o

HS9-80C86RH-8

-35 C to +125 C

o

HS9-80C86RH-Q

-35 C to +125 C

o

HS9-80C86RH-SAMPLE

HS1-80C86RH-SAMPLE

HS9-80C86RH-PROTO

HS1-80C86RH-PROTO

25 C

o

25 C

Sample

o

-35 C to +125 C

Prototype

o

-35 C to +125 C

Prototype

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Spec Number 518055

File Number 3035.1

856

HS-80C86RH

Pinouts

HS-80C86RH 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835, CDIP2-T40

TOP VIEW

MAX

MIN

GND

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NMI

1

2

40 VDD

39 AD15

3

38 AD16/S3

4

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A17/S4

A18/S5

A19/S6

BHE/S7

MN/MX

RD

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

RQ/GT0

RQ/GT1

LOCK

S2

(HOLD)

(HLDA)

(WR)

(M/IO)

(DT/R)

(DEN)

(ALE)

(INTA)

S1

S0

QS0

QS1

INTR

CLK

GND

TEST

READY

RESET

HS-80C86RH 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK)

INTERSIL OUTLINE K42.A

TOP VIEW

MAX

VDD

MIN

GND

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NC

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

2

AD15

NC

3

A16/S3

A17/S4

A18/S5

A19/S6

BHE/S7

MN/MX

RD

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

(HOLD)

RQ/GT0

RQ/GT1 (HLDA)

LOCK

S2

(WR)

(M/IO)

(DT/R)

(DEN)

(ALE)

(INTA)

S1

S0

QS0

NMI

QS1

INTR

CLK

GND

TEST

READY

RESET

Spec Number 518055

857

HS-80C86RH

Functional Diagram

BUS INTERFACE UNIT

EXECUTION UNIT

REGISTER FILE

RELOCATION

REGISTER FILE

DATA POINTER

AND

INDEX REGS

(8 WORDS)

SEGMENT REGISTERS

AND

INSTRUCTION POINTER

(5 WORDS)

BHE/S7

A19/S6

A16/S3

16-BIT ALU

FLAGS

4

16

3

AD15-AD0

BUS INTERFACE UNIT

INTA, RD, WR

DT/R, DEN, ALE, M/IO

4

6-BYTE

INSTRUCTION

QUEUE

TEST

INTR

NMI

LOCK

2

QS0, QS1

CONTROL AND TIMING

RQ/GT0, 1

2

HOLD

HLDA

3

S2, S1, S0

3

CLK RESET READY MN/MX GND

VDD

MEMORY INTERFACE

C-BUS

INSTRUCTION

STREAM BYTE

B+BUS

QUEUE

ES

CS

SS

BUS

INTERFACE

UNIT

DS

IP

EXECUTION UNIT

CONTROL SYSTEM

A-BUS

AH

BH

CH

DH

AL

BL

CL

DL

ARITHMETIC/

LOGIC UNIT

EXECUTION

UNIT

SP

BP

SI

DI

FLAGS

Spec Number 518055

858

HS-80C86RH

Pin Description

SYMBOL

NUMBER

TYPE

DESCRIPTION

The following pin function descriptions are for HS-80C86RH systems in either minimum or maximum mode. The “Local Bus” in these de-

scriptions is the direct multiplexed bus interface connection to the HS-80C86RH (without regard to additional bus buffers).

AD15-AD0

2-16, 39

I/O

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1)

and data (T2, T3, TW, T4) bus. AO is analogous to BHE for the lower byte of the data bus, pins

D7-D0. It is LOW during T1 when a byte is to be transferred on the lower portion of the bus in

memory or I/O operations. Eight-bit oriented devices tied to the lower half would normally use

AD0 to condition chip select functions (See BHE). These lines are active HIGH and are held at

high impedance to the last valid logic level during interrupt acknowledge and local bus “hold ac-

knowledge” or “grant sequence”.

A19/S6

A18/S5

A17/S4

A16/S3

35-38

O

ADDRESS/STATUS: During T1, these are the four most significant address lines for memory

operations. During I/O operations these lines are low. During memory and I/O operations, status

information is available on these lines during T2, T3, TW, T4. S6 is always zero. The status of

the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle. S4 and S3 are

encoded.

This information indicates which segment register is presently being used for data accessing.

These lines are held at high impedance to the last valid logic level during local bus “hold acknowl-

edge” or “grant sequence”.

S4

0

S3

0

Extra Data

Stack

0

1

0

Code or None

Data

1

BHE/S7

34

O

BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to

enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices

tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE

is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-

ferred on the high portion of the bus. The S7 status information is available during T2, T3 and

T4. The signal is active LOW, and is held at high impedance to the last valid logic level during

interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”; it is LOW during

T1 for the first interrupt acknowledge cycle.

BHE

A0

0

1

Whole Word

1

Upper Byte from/to Odd Address

Lower Byte from/to Even Address

None

0

1

RD

32

O

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-

pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on

the HS-80C86RH local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is

guaranteed to remain HIGH in T2 until the 80C86 local bus has floated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grant se-

quence”.

READY

INTR

22

18

I

READY: is the acknowledgment from the addressed memory or I/O device that will complete the

data transfer. The RDY signal from memory or I/O is synchronized by the HS-82C85RH Clock

Generator to form READY. This signal is active HIGH. The HS-80C86RH READY input is not

synchronized. Correct operation is not guaranteed if the Setup and Hold Times are not met.

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle

of each instruction to determine if the processor should enter into an interrupt acknowledge op-

eration. If so, an interrupt service routine is called via an interrupt vector lookup table located in

system memory. INTR is internally synchronized and can be internally masked by software re-

setting the interrupt enable bit. This signal is active HIGH.

TEST

NMI

23

17

I

TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,

otherwise the processor waits in an “Idle” state. This input is synchronized internally during each

clock cycle on the leading edge of CLK.

NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. An

interrupt service routine is called via an interrupt vector lookup table located in system memory.

NMI is not maskable internally by software. A transition from LOW to HIGH initiates the interrupt

at the end of the current instruction. This input is internally synchronized.

Spec Number 518055

859

HS-80C86RH

Pin Description (Continued)

SYMBOL

NUMBER

TYPE

DESCRIPTION

RESET

21

I

RESET: causes the processor to immediately terminate its present activity. The signal must

change from LOW to HIGH and remain active HIGH for at least 4 CLK cycles. It restarts

execution, as described in the Instruction Set description, when RESET returns LOW. RESET is

internally synchronized.

CLK

VDD

19

40

I

CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a

33% duty cycle to provide optimized internal timing.

VDD: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for

decoupling.

GND

1, 20

33

GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is

recommended for decoupling.

MN/MX

I

MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are

discussed in the following sections.

The following pin function descriptions are for the HS-80C86RH system in maximum mode (i.e., MN/MX = GND). Only the pin functions

which are unique to maximum mode are described below.

S0, S1, S2

26-28

O

STATUS: is active during T4, T1 and T2 and is returned to the passive state (1,1,1) during T3

or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate

all memory and I/O access control signals. Any change by S2, S1, or S0 during T4 is used to

indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to

indicate the end of a bus cycle. These status lines are encoded. These signals are held at a high

impedance logic one state during “grant sequence”.

S2

0

S1

0

S0

0

Interrupt Acknowledge

Read I/O Port

Write I/O Port

Halt

0

1

0

1

0

1

0

Code Access

Read Memory

Write Memory

Passive

1

0

1

0

1

RQ/GT0

RQ/GT1

31, 30

I/O

REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the

local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0 hav-

ing higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so it may be left

unconnected. The request/grant sequence is as follows (see RQ/GT Sequence Timing.)

1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”) to

the HS-80C86RH (pulse 1).

2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the HS-80C86RH to the requesting

master (pulse 2) indicates that the HS-80C86RH has allowed the local bus to float and that

it will enter the “grant sequence” state at the next CLK. The CPU’s bus interface unit is dis-

connected logically from the local bus during “grant sequence”.

3. A pulse 1 CLK wide from the requesting master indicates to the HS-80C86RH (pulse 3) that

the “hold” request is about to end and that the HS-80C86RH can reclaim the local bus at the

next CLK. The CPU then enters T4 (or T1 if no bus cycles pending).

Each Master-Master exchange of the local bus is a sequence of 3 pulses. There must be

one idle CLK cycle after each bus exchange. Pulses are active low.

If the request is made while the CPU is performing a memory cycle, it will release the local

bus during T4 of the cycle when all the following conditions are met:

1. Request occurs on or before T2.

2. Current cycle is not the low byte of a word (on an odd address).

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing.

If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next cycle.

2. A memory cycle will start within 3 CLKs. Now the four rules for a currently active memory

cycle apply with condition number 1 already satisfied.

Spec Number 518055

860

HS-80C86RH

Pin Description (Continued)

SYMBOL

NUMBER

TYPE

DESCRIPTION

LOCK

29

O

LOCK: output indicates that other system bus masters are not to gain control of the system bus

while LOCK is active LOW. The LOCK signal is activated by the “LOCK” preﬁx instruction and re-

mains active until the completion of the next instruction. This signal is active LOW, and is held at a

HIGH impedance logic one state during “grant sequence”. In MAX mode, LOCK is automatically

generated during T2 of the ﬁrst INTA cycle and removed during T2 of the second INTA cycle.

QS1, QS0

24, 25

O

QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue

operation is performed.

QS1 and QS2 provide status to allow external tracking of the internal HS-80C86RH instruction

queue. Note that QS1, QS0 never become high impedance.

QS1

QS0

0

1

0

1

0

1

No Operation

First Byte of Opcode from Queue

Empty the Queue

Subsequent Byte from Queue

The following pin function descriptions are for the HS-80C86RH in minimum mode (i.e. MN/MX = VDD). Only the pin functions which are

unique to minimum mode are described; all other pin functions are as described below.

M/IO

28

O

STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-

ory access from an I/O access. M/IO becomes valid in the T4 preceding a bus cycle and remains

valid until the final T4 of the cycle (M = HIGH, IO = LOW). M/IO is held to a high impedance logic

zero during local bus “hold acknowledge”.

WR

INTA

ALE

29

24

25

27

O

WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending

on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active

LOW, and is held to high impedance logic one during local bus “hold acknowledge”.

INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is

active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never

floated.

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82

latch. It is a HIGH pulse active during clock LOW of Tl of any bus cycle. Note that ALE is never

floated.

DT/R

DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus

transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R

is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HlGH, R =

LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.

DEN

26

O

DATA ENABLE: provided as an output enable fora bus transceiver in a minimum system which

uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA

cycles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for

a write cycle it is active from the beginning of T2 until the middle of T4. DEN is held to a high

impedance logic one during local bus “hold acknowledge”.

HOLD

HLDA

31

30

I

O

HOLD: indicates that another master is requesting a local bus “hold”. To be a acknowledged,

HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge”

(HLDA) in the middle of a T4 or T1 clock cycle. Simultaneously with the issuance of HLDA, the

processor will float the local bus and control lines. After HOLD is detected as being LOW, the

processor will lower HLDA, and when the processor needs to run another cycle, it will again drive

the local bus and control lines.

HOLD is not an asynchronous input. External synchronization should be provided if the system

cannot otherwise guarantee the setup time.

Spec Number 518055

861

Speciﬁcations HS-80C86RH

Absolute Maximum Ratings

Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance

θ

JC

JA

o

Input or Output Voltage

SBDIP Package. . . . . . . . . . . . . . . . . . . . 40.0 C/W 8.6 C/W

o

Applied for all Grades. . . . . . . . . . . . . . . . . .VSS-0.3V to VDD+0.3V

Ceramic Flatpack Package . . . . . . . . . . . 72.1 C/W 9.7 C/W

Maximum Package Power Dissipation at +125 C Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W

o

Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C

o

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C

o

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C

Typical Derating Factor. . . . . . . . . . . 12mA/MHz Increase in IDDOP If Device Power Exceeds Package Dissipation Capability, Provide

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Heat Sinking or Derate Linearly at the Following Rate

o

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.0mW/ C

o

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 13.9mW/ C

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Operating Conditions

Operating Supply Voltage Range (VDD) . . . . . . . +4.75V to +5.25V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . . . 3.5V to VDD

o

Operating Temperature Range (T ) . . . . . . . . . . . . -35 C to +125 C

Clock Input Low Voltage (VILC) . . . . . . . . . . . . . . . . . . 0.0V to 0.8V

A

Input Low Voltage (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V CLK and MN/MX Input High (VIHC) . . . . . . . . . .VDD - 0.8V to VDD

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

GROUP A

PARAMETERS

SYMBOL

CONDITIONS

SUBGROUPS TEMPERATURE

MIN

MAX

UNITS

o

TTL High Level

Output Voltage

VOH1

VDD = 4.75V, IO = -2.5mA

VIN = 0V or VDD

1, 2, 3

-35 C, +25 C,

3.0

-

V

o

+125 C

o

CMOS High Level

Output Voltage

VOH2

VOL

VDD = 4.75V, IO = -100µA

VIN = 0V or VDD

-35 C, +25 C,

VDD -

0.4V

-

V

o

+125 C

o

Low Level Output

Voltage

VDD = 4.75V, IO = +2.5mA

VIN = 0V or VDD

-35 C, +25 C,

-

0.4

1.0

o

+125 C

o

Input Leakage

Current

IIH or

IIL

VDD = 5.25V

VIN = 0V or VDD

Pins: 17-19, 21-23, 33

-35 C, +25 C,

-1.0

µA

o

+125 C

o

Output Leakage

Current

IOZL or

IOZH

VDD = 5.25V

VIN = 0V or VDD

Pins: 2-16, 26-29, 32, 34-39

1, 2, 3

-35 C, +25 C,

-10

-600

40

10

-40

600

µA

o

+125 C

o

Input Current Bus

Hold High

IBHH

IBHL

VDD = 4.75V and 5.25V

VIN = 3.0V (Note 1)

Pins: 2-16, 26-32, 34-39

-35 C, +25 C,

o

+125 C

o

Input Current Bus

Hold Low

VDD = 4.75V and 5.25V

VIN = 0.8V (Note 2)

Pins: 2-16, 34-39

-35 C, +25 C,

o

+125 C

o

Standby Power

Supply Current

IDDSB

IDDOP

FT

VDD = 5.25V, VIN = GND or

VDD, IO = 0mA (Note 3)

1, 2, 3

-35 C, +25 C,

-

500

12

-

µA

mA/MHz

-

o

+125 C

o

Operating Power

Supply Current

VDD = 5.25V, VIN = GND or

VDD, IO = 0mA, f = 1MHz

-35 C, +25 C,

o

+125 C

o

Functional Tests

VDD = 4.75V and 5.25V,

VIN = GND or VDD,

f = 1MHz

7, 8A, 8B

-35 C, +25 C,

o

+125 C

o

Noise Immunity

Functional Tests

FN

VDD = 4.75V and 5.25V,

VIN = GND or 3.5V and

VDD = 4.5V,

7, 8A, 8B

-35 C, +25 C,

-

o

+125 C

VIN = 0.8V or VDD (Note 4)

NOTES:

1. IBHH should be measured after raising VIN to VDD and then lowering to 3.0V.

2. IBHL should be measured after lowering VIN to VSS and then raising to 0.8V.

3. IDDSB tested during Clock high time after halt instruction executed.

4. CLK and MN/MX Input High (VIHC) = VDD -0.8

Spec Number 518055

862

Speciﬁcations HS-80C86RH

TABLE 2A. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (MIN MODE)

ACs tested at worst case VDD, ACs guaranteed over full operating speciﬁcations.

LIMITS

MAX

GROUP A

SUBGROUPS TEMPERATURE

PARAMETERS

CLK Cycle Period

SYMBOL

CONDITIONS

VDD = 4.75V

MIN

UNITS

o

TCLCL

9, 10, 11

-35 C, +25 C,

200

-

ns

o

VDD = 5.25V

+125 C

o

CLK Low Time

TCLCH

TCHCL

TDVCL

VDD = 4.75V

-35 C, +25 C,

118

69

30

10

113

30

-8

ns

o

+125 C

o

CLK High Time

VDD = 4.75V

VDD = 5.25V

-35 C, +25 C,

o

+125 C

o

Data in Setup Time

Data in Hold Time

VDD = 4.75V

-35 C, +25 C,

o

+125 C

o

TCLDX1 VDD = 4.75V

TRYHCH VDD = 4.75V

TCHRYX VDD = 4.75V

TRYLCL VDD = 4.75V

-35 C, +25 C,

o

+125 C

o

Ready Setup Time into

80C86RH

-35 C, +25 C,

o

+125 C

o

Ready Hold Time into

80C86RH

-35 C, +25 C,

o

+125 C

o

Ready Inactive to CLK

(Note 2)

-35 C, +25 C,

o

+125 C

o

Hold Setup Time

THVCH

TINVCH

VDD = 4.75V

-35 C, +25 C,

35

30

o

+125 C

o

INTR, NMI, Test/Setup Time

-35 C, +25 C,

o

+125 C

MIN MODE TIMING RESPONSES (CL = 100pF)

o

Address Valid Delay

TCLAV

TLHLL

TCLLH

TCHLL

TLLAX

VDD = 4.75V

9, 10, 11

-35 C, +25 C,

10

110

-

ns

o

+125 C

o

ALE Width

-35 C, +25 C,

TCLCH -

20

o

+125 C

o

ALE Active Delay

ALE Inactive Delay

-35 C, +25 C,

-

80

o

+125 C

o

-35 C, +25 C,

-

85

o

+125 C

o

Address Hold Time to ALE

Inactive

-35 C, +25 C,

TCHCL -

10

-

o

+125 C

o

Control Active Delay 1

Control Active Delay 2

Control Inactive Delay

RD Active Delay

TCVCTV VDD = 4.75V

TCHCTV VDD = 4.75V

TCVCTX VDD = 4.75V

-35 C, +25 C,

10

110

165

150

-

o

+125 C

o

-35 C, +25 C,

o

+125 C

o

-35 C, +25 C,

o

+125 C

o

TCLRL

TCLRH

TRHAV

VDD = 4.75V

-35 C, +25 C,

o

+125 C

o

RD Inactive Delay

-35 C, +25 C,

o

+125 C

o

RD Inactive to Next

Address Active

-35 C, +25 C,

TCLCL -

45

o

+125 C

o

HLDA Valid Delay

TCLHAV VDD = 4.75V

-35 C, +25 C,

10

160

o

+125 C

Spec Number 518055

863

Speciﬁcations HS-80C86RH

TABLE 2A. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (MIN MODE) (Continued)

ACs tested at worst case VDD, ACs guaranteed over full operating speciﬁcations.

LIMITS

GROUP A

PARAMETERS

RD Width

SYMBOL

CONDITIONS

VDD = 4.75V

SUBGROUPS TEMPERATURE

MIN

MAX

UNITS

o

TRLRH

9, 10, 11

-35 C, +25 C,

2TCLCL -

75

-

ns

o

+125 C

o

WR Width

TWLWH VDD = 4.75V

-35 C, +25 C,

2TCLCL -

60

-

ns

o

+125 C

o

Address Valid to ALE Low

Output Rise Time

Output Fall Time

NOTES:

TAVLL

TOLOH

TOHOL

VDD = 4.75V

-35 C, +25 C,

TCLCH -

60

-

o

+125 C

o

VDD = 4.75V

From 0.8V to 2.0V

-35 C, +25 C,

-

20

o

+125 C

o

VDD = 4.75V

From 2.0V to 0.8V

-35 C, +25 C,

-

o

+125 C

1. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

2. Applies only to T2 State (8ns into T3).

TABLE 2B. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (MAX MODE)

ACs tested at worst case VDD, ACs guaranteed over full operating speciﬁcations.

LIMITS

GROUP A

PARAMETERS

TIMING REQUIREMENTS

CLK Cycle Period

SYMBOL

CONDITIONS

SUBGROUPS TEMPERATURE

MIN

MAX

UNITS

o

TCLCL

TCLCH

TCHCL

TDVCL

VDD = 4.75V

VDD = 5.25V

9, 10, 11

-35 C, +25 C,

200

118

69

-

ns

o

+125 C

o

CLK Low Time

VDD = 4.75V

-35 C, +25 C,

o

+125 C

o

CLK High Time

VDD = 4.75V

VDD = 5.25V

-35 C, +25 C,

o

+125 C

o

Data in Setup Time

Data in Hold Time

VDD = 4.75V

-35 C, +25 C,

30

o

+125 C

o

TCLDX1 VDD = 4.75V

TRYHCH VDD = 4.75V

TCHRYX VDD = 4.75V

TRYLCL VDD = 4.75V

-35 C, +25 C,

10

o

+125 C

o

Ready Setup Time into

80C86RH

-35 C, +25 C,

113

30

o

+125 C

o

Ready Hold Time into

80C86RH

-35 C, +25 C,

o

+125 C

o

Ready Inactive to CLK

(Note 2)

-35 C, +25 C,

-8

o

+125 C

o

INTR, NMI, Test/Setup Time

TINVCH

TGVCH

TCHGX

VDD = 4.75V

-35 C, +25 C,

30

o

+125 C

o

RQ/GT Setup Time

-35 C, +25 C,

30

o

+125 C

o

RQ Hold Time into

HS-80C86RH (Note 3)

-35 C, +25 C,

40

TCHCL +

10

o

+125 C

MAX MODE TIMING RESPONSES (CL = 100pF)

o

Ready Active to Status

Passive (Notes 2 and 4)

TRYHSH VDD = 4.75V

9, 10, 11

-35 C, +25 C,

-

110

ns

o

+125 C

o

Status Active Delay

TCHSV

VDD = 4.75V

-35 C, +25 C,

10

o

+125 C

Spec Number 518055

864

Speciﬁcations HS-80C86RH

TABLE 2B. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (MAX MODE) (Continued)

ACs tested at worst case VDD, ACs guaranteed over full operating speciﬁcations.

LIMITS

GROUP A

PARAMETERS

SYMBOL

CONDITIONS

VDD = 4.75V

SUBGROUPS TEMPERATURE

MIN

MAX

UNITS

o

Status Inactive Delay

(Note 4)

TCLSH

9, 10, 11

-35 C, +25 C,

10

130

ns

o

+125 C

o

Address Valid Delay

TCLAV

TCLRL

TCLRH

TRHAV

TCLGL

TCLGH

TRLRH

TOLOH

TOHOL

VDD = 4.75V

-35 C, +25 C,

10

110

165

150

-

ns

o

+125 C

o

RD Active Delay

-35 C, +25 C,

o

+125 C

o

RD Inactive Delay

-35 C, +25 C,

o

+125 C

o

RD Inactive to Next

Address Active

-35 C, +25 C,

TCLCL -

45

o

+125 C

o

GT Active Delay

GT Inactive Delay

RD Width

-35 C, +25 C,

0

85

-

o

+125 C

o

-35 C, +25 C,

0

o

+125 C

o

-35 C, +25 C,

2TCLCL -

75

o

+125 C

o

Output Rise Time

Output Fall Time

NOTES:

VDD = 4.75V

From 0.8V to 2.0V

-35 C, +25 C,

-

20

o

+125 C

o

VDD = 4.75V

From 2.0V to 0.8V

-35 C, +25 C,

-

o

+125 C

1. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

2. Applies only to T2 State (8ns into T3).

3. The HS-80C86RH actively pulls the RQ/GT pin to a logic one on the following clock low time.

4. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.

TABLE 3A. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETERS

Input Capacitance

SYMBOL

CONDITIONS

TEMPERATURE

MIN

MAX

UNITS

o

CIN

VDD = Open, f = 1MHz

(Note 1)

T = +25 C

-

15

pF

A

o

Output Capacitance

I/O Capacitance

COUT

CI/O

VDD = Open, f = 1MHz

(Note 1)

T = +25 C

-

15

20

pF

A

o

VDD = Open, f = 1MHz

(Note 1)

T = +25 C

A

TIMING REQUIREMENTS

CLK Rise Time

o

TCH1CH2 VDD = 4.75V and 5.25V

Min and Max Mode

-35 C < T < +125 C

-

15

25

ns

A

from 1.0V to 3.5V

o

CLK Fall Time

Input Rise Time

Input Fall Time

TCL2CL1 VDD = 4.75V and 5.25V

Min and Max Mode

-35 C < T < +125 C

A

from 3.5V to 1.0V

o

TILIH

TIHIL

VDD = 4.75V and 5.25V

Min and Max Mode

from 0.8V to 2.0V

-35 C < T < +125 C

A

o

VDD = 4.75V and 5.25V

Min and Max Mode

from 2.0V to 0.8V

-35 C < T < +125 C

A

Spec Number 518055

865

Speciﬁcations HS-80C86RH

TABLE 3A. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETERS

TIMING RESPONSES

Address Hold Time

SYMBOL

CONDITIONS

TEMPERATURE

MIN

MAX

UNITS

o

TCLAX

TCLAZ

TCLDV

VDD = 4.75V and 5.25V

Min and Max Mode

-35 C < T < +125 C

10

-

80

110

-

ns

A

o

Address Float Delay (Note 2)

Data Valid Delay

VDD = 4.75V and 5.25V

Min and Max Mode

-35 C < T < +125 C

TCLAX

10

A

o

VDD = 4.75V and 5.25V

Min and Max Mode

-35 C < T < +125 C

A

o

Data Hold Time

TCLDX2 VDD = 4.75V and 5.25V

Min and Max Mode

-35 C < T < +125 C

10

A

o

Data Hold Time After WR

Status Float Delay (Note 2)

TWHDX

TCHSZ

TAZRL

VDD = 4.75V and 5.25V

Min Mode

-35 C < T < +125 C TCLCL - 30

-

A

o

VDD = 4.75V and 5.25V

Max Mode

-35 C < T < +125 C

-

80

-

A

o

Address Float to Read Active

(Note 2)

VDD = 4.75V and 5.25V

Min and Max Mode

-35 C < T < +125 C

0

A

NOTES:

1. All measurements referenced to device ground.

2. Output drivers disabled. Bus hold circuitry still active.

3. The parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon

initial design release and upon design changes which would affect these characteristics.

TABLE 3B. ELECTRICAL PERFORMANCE CHARACTERISTICS

Timing Signals at HS-82C85RH or 82C88 for Reference Only.

LIMITS

PARAMETERS

RDY Setup Time into HS-82C85RH (Note 1)

RDY Hold Time into HS-82C85RH (Note 1)

Command Active Delay

Command Inactive

SYMBOL

CONDITIONS

TEMPERATURE

MIN MAX UNITS

o

TR1VCL Min and Max Mode

TCLR1X Min and Max Mode

-35 C < T < +125 C

35

0

5

-

ns

A

o

-35 C < T < +125 C

-

A

o

TCLML

TCLMH

TSVLH

Max Mode Only

-35 C < T < +125 C

35

20

30

20

25

18

15

45

A

o

-35 C < T < +125 C

A

o

Status Valid to ALE High

Status Valid to MCE High

CLK Low to ALE Valid

-35 C < T < +125 C

A

o

TSVMCH Max Mode Only

TCLLH Max Mode Only

TCLMCH Max Mode Only

TCHLL Max Mode Only

TCLMCL Max Mode Only

-35 C < T < +125 C

-

A

o

-35 C < T < +125 C

-

A

o

CLK Low to MCE High

ALE Inactive Delay

-35 C < T < +125 C

-

A

o

-35 C < T < +125 C

4

-

A

o

MCE Inactive Delay

-35 C < T < +125 C

A

o

Control Active Delay

TCVNV

TCVNX

Max Mode Only

-35 C < T < +125 C

5

10

A

o

Control Inactive Delay

-35 C < T < +125 C

A

NOTE:

1. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS

NOTE: See 25 C limits in Table 1 and Table 2 for Post RAD limits (Subgroups 1, 7 and 9).

o

Spec Number 518055

866

Speciﬁcations HS-80C86RH

o

TABLE 5. BURN-IN DELTA PARAMETERS (+25 C)

PARAMETER

SYMBOL

IDDSB

IOZL, IOZH

IIH, IIL

DELTA LIMITS

Standby Power Supply Current

Output Leakage Current

±100µA

± 2µA

Input Leakage Current

± 200nA

± 80mV

± 600mV

±150mV

Low Level Output Voltage

TTL High Level Output Voltage

CMOS High Level Output Voltage

VOL

VOH1

VOH2

TABLE 6. APPLICABLE SUBGROUPS

GROUP A SUBGROUPS

RECORDED

CONFORMANCE

GROUP

MIL-STD-883

METHOD

RECORDED

FOR -8

TESTED FOR -Q

FOR -Q

1 (Note 2)

1, ∆ (Note 2)

TESTED FOR -8

Initial Test

100%/5004

Sample 5005

1, 7, 9

Interim Test 1

PDA 1

1, 7, 9, ∆

1, 7, 9

1, 7, ∆

1, 7

Interim Test 2

PDA 2

1, 7, 9, ∆

1, ∆ (Note 2)

N/A

1, 7, ∆

2, 3, 8A, 8B, 10, 11

1, 2, 3, 7, 8A, 8B, 9, 10, 11

1, 7, 9

N/A

Final Test

2, 3, 8A, 8B, 10, 11

Group A (Note 1)

Subgroup B5

Subgroup B6

Group C

1, 2, 3, 7, 8A, 8B, 9, 10, 11

1, 2, 3 (Note 2)

N/A

1, 2, 3, 7, 8A, 8B, 9, 10, 11

1, 7, 9

N/A

Group D

1, 7, 9

Group E, Subgroup 2

NOTES:

1, 7, 9

1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised.

2. Table 5 parameters only.

Functional Description

system frequency is reduced, so is the operating power until,

ultimately, at a DC input frequency, the HS-80C86RH power

requirement is the standby current, (500µA maximum).

Static Operation

All HS-80C86RH circuitry is of static design. Internal

registers, counters and latches are static and require no

refresh as with dynamic circuit design. This eliminates the

minimum operating frequency restriction placed on other

microprocessors. The CMOS HS-80C86RH can operate

from DC to 5MHz. The processor clock may be stopped in

either state (HIGH/LOW) and held there indeﬁnitely. This

type of operation is especially useful for system debug or

power critical applications.

Internal Architecture

The internal functions of the HS-80C86RH processor are

partitioned logically into two processing units. The ﬁrst is the

Bus Interface Unit (BIU) and the second is the Execution

Unit (EU) as shown in the CPU functional diagram.

These units can interact directly but for the most part

perform as separate asynchronous operational processors.

The bus interface unit provides the functions related to

instruction fetching and queuing, operand fetch and store,

and address relocation. This unit also provides the basic bus

control. The overlap of instruction pre-fetching provided by

this unit serves to increase processor performance through

improved bus bandwidth utilization. Up to 6 bytes of the

instruction stream can be queued while waiting for decoding

and execution.

The HS-80C86RH can be single stepped using only the CPU

clock. This state can be maintained as long as is necessary.

Single step clock operation allows simple interface circuitry to

provide critical information for bringing up your system.

Static design also allows very low frequency operation

(down to DC). In a power critical situation, this can provide

extremely low power operation since HS-80C86RH power

dissipation is directly related to operating frequency. As the

Spec Number 518055

867

HS-80C86RH

The instruction stream queuing mechanism allows the BlU to All memory references are made relative to base addresses

keep the memory utilized very efﬁciently. Whenever there is contained in high speed segment registers. The segment

space for at least 2 bytes in the queue, the BlU will attempt a types were chosen based on the addressing needs of

word fetch memory cycle. This greatly reduces “dead-time” programs. The segment register to be selected is

on the memory bus. The queue acts as a First-In-First-Out automatically chosen according to the speciﬁc rules of

(FlFO) buffer, from which the EU extracts instruction bytes Table 7. All information in one segment type share the same

as required. If the queue is empty (following a branch logical attributes (e.g. code or data). By structuring memory

instruction, for example), the ﬁrst byte into the queue into relocatable areas of similar characteristics and by

immediately becomes available to the EU.

automatically selecting segment registers, programs are

shorter, faster and more structured. (See Table 7).

The execution unit receives pre-fetched instructions from the

BlU queue and provides un-relocated operand addresses to Word (16-bit) operands can be located on even or odd

the BlU. Memory operands are passed through the BlU for address boundaries and are thus not constrained to even

processing by the EU, which passes results to the BlU for boundaries as is the case in many 16-bit computers. For

storage.

address and data operands, the least signiﬁcant byte of the

word is stored in the lower valued address location and the

most signiﬁcant byte in the next higher address location. The

BlU automatically performs the proper number of memory

accesses, one if the word operand is on an even byte

boundary and two if it is on an odd byte boundary. Except for

the performance penalty, this double access is transparent to

the software. The performance penalty does not occur for

instruction fetches; only word operands.

Memory Organization

The processor provides a 20-bit address to memory, which

locates the byte being referenced. The memory is organized

as a linear array of up to 1 million bytes, addressed as

00000(H) to FFFFF(H). The memory is logically divided into

code, data, extra and stack segments of up to 64K bytes

each, with each segment falling on 16 byte boundaries. (See

Figure 1).

Physically, the memory is organized as a high bank (D15-

D6) and a low bank (D7-D0) of 512K bytes addressed in par-

allel by the processor’s address lines.

FFFFFH

Byte data with even addresses is transferred on the D7-D0

bus lines while odd addressed byte data (A0 HIGH) is

transferred on the D15-D6 bus lines. The processor provides

two enable signals, BHE and A0, to selectively allow reading

from or writing into either an odd byte location, even byte

location, or both. The instruction stream is fetched from

memory as words and is addressed internally by the

processor at the byte level as necessary.

64K BIT

CODE SEGMENT

XXXXOH

STACK SEGMENT

DATA SEGMENT

+ OFFSET

SEGMENT

REGISTER FILE

In referencing word data, the BlU requires one or two

memory cycles depending on whether the starting byte of

the word is on an even or odd address, respectively. Con-

sequently, in referencing word operands performance can be

optimized by locating data on even address boundaries. This

is an especially useful technique for using the stack, since

odd address references to the stack may adversely affect the

context switching time for interrupt processing or task multi-

plexing.

CS

SS

DS

ES

EXTRA SEGMENT

00000H

Certain locations in memory are reserved for speciﬁc CPU

operations (See Figure 2). Locations from address FFFF0H

through FFFFFH are reserved for operations including a

jump to the initial program loading routine. Following RESET,

the CPU will always begin execution at location FFFF0H

where the jump must be located. Locations 00000H through

003FFH are reserved for interrupt operations. Each of the

256 possible interrupt service routines is accessed through

its own pair of 16-bit pointers - segment address pointer and

offset address pointer. The ﬁrst pointer, used as the offset

address, is loaded into the 1P and the second pointer, which

designates the base address is loaded into the CS. At this

point program control is transferred to the interrupt routine.

The pointer elements are assumed to have been stored at

the respective places in reserved memory prior to occur-

rence of interrupts.

FIGURE 1. HS-80C86RH MEMORY ORGANIZATION

TABLE 7.

DEFAULT

TYPE OF MEMORY SEGMENT

ALTERNATE

SEGMENT

BASE

REFERENCE

Instruction Fetch

Stack Operation

BASE

OFFSET

IP

CS

None

SS

SP

Variable

(Except Following)

DS

CS, ES, SS

Effective

Address

String Source

DS

ES

SS

CS, ES, SS

None

SI

DI

String Destination

BP Used as Base

Register

CS, DS, ES

Effective

Address

Spec Number 518055

868

HS-80C86RH

FFFFFH

FFFFOH

Status bits S0, S1 and S2 are used by the bus controller, in

maximum mode, to identify the type of bus transaction

according to Table 8.

RESET BOOTSTRAP

PROGRAM JUMP

TABLE 8.

3FFH

3FCH

INTERRUPT POINTER

FOR TYPE 255

S2

0

S1

0

S0

0

CHARACTERISTICS

Interrupt Acknowledge

7H

0

1

Read I/O Port

INTERRUPT POINTER

FOR TYPE 1

0

1

0

Write I/O Port

4H

3H

0

1

Halt

INTERRUPT POINTER

FOR TYPE 0

0H

1

0

Instruction Fetch

Read Data from Memory

Write Data to Memory

Passive (no bus cycle)

FIGURE 2. RESERVED MEMORY LOCATIONS

Minimum and Maximum Operation Modes

1

0

1

0

The requirements for supporting minimum and maximum

HS-80C86RH systems are sufﬁciently different that they

cannot be met efﬁciently using 40 uniquely deﬁned pins.

Consequently, the HS-80C86RH is equipped with a strap pin

(MN/MX) which deﬁnes the system conﬁguration. The deﬁni-

tion of a certain subset of the pins changes, dependent on

the condition of the strap pin. When the MN/MX pin is

strapped to GND, the HS-80C86RH deﬁnes pins 24 through

31 and 34 in maximum mode. When the MN/MX pin is

strapped to VDD, the HS-80C86RH generates bus control

signals itself on pins 24 through 31 and 34.

1

Status bits S3 through S7 are time multiplexed with high

order address bits and the BHE signal, and are therefore

valid during T2 through T4. S3 and S4 indicate which seg-

ment register (see Instruction Set Description) was used for

this bus cycle in forming the address, according to Table 9.

TABLE 9.

S4

0 (Low)

0

S3

0

CHARACTERISTICS

Alternate Data (extra segment)

Bus Operation

1

Stack

The HS-80C86RH has a combined address and data bus

commonly referred to as a time multiplexed bus. This tech-

nique provides the most efﬁcient use of pins on the proces-

sor while permitting the use of a standard 40-lead package.

This “local bus” can be buffered directly and used throughout

the system with address latching provided on memory and

I/O modules. In addition, the bus can also be demultiplexed

at the processor with a single set of 82C82 latches if a stan-

dard non-multiplexed bus is desired for the system.

1 (High)

1

0

Code or None

Data

1

S5 is a reﬂection of the PSW interrupt enable bit. S6 is

always zero and S7 is a spare status bit.

I/O Addressing

In the HS-80C86RH, I/O operations can address up to a

maximum of 64K I/O byte registers or 32K I/O word regis-

ters. The I/O address appears in the same format as the

memory address on bus lines A15-A0. The address lines

A19-A16 are zero in I/O operations. The variable I/O instruc-

tions which use register DX as a pointer have full address

capability while the direct I/O instructions directly address

one or two of the 256 I/O byte locations in page 0 of the I/O

address space.

Each processor bus cycle consists of at least four CLK cy-

cles. These are referred to as T1, T2, T3 and T4 (see Figure

3). The address is emitted from the processor during T1 and

data transfer occurs on the bus during T3 and T4. T2 is used

primarily for changing the direction of the bus during read

operations. In the event that a “NOT READY” indication is

given by the addressed device, “Wait” states (TW) are

inserted between T3 and T4. Each inserted wait state is the

same duration as a CLK cycle. Idle periods occur between

HS-80C86RH driven bus cycles whenever the processor

performs internal processing.

I/O ports are addressed in the same manner as memory

locations. Even addressed bytes are transferred on the D7-

D0 bus lines and odd addressed bytes on D15-D8. Care

must be taken to ensure that each register within an 8-bit

peripheral located on the lower portion of the bus be

addressed as even.

During T1 of any bus cycle, the ALE (Address Latch Ena-

ble) signal is emitted (by either the processor or the 82C88

bus controller, depending on the MN/MX strap). At the trail-

ing edge of this pulse, a valid address and certain status

information for the cycle may be latched.

Spec Number 518055

869

HS-80C86RH

(4 + NWAIT) = TCY

T3 TWAIT

T1

T2

T3

TWAIT

T4

T1

T2

T4

CLK

GOES INACTIVE IN THE STATE

JUST PRIOR TO T4

ALE

S2-S0

BHE,

A19-A16

ADDR/

STATUS

S7-S3

D15-D0

VALID

A15-A0

DATA OUT (D15-D0)

ADDR/DATA

RD, INTA

READY

WAIT

DT/R

DEN

WP

MEMORY ACCESS TIME

FIGURE 3. BASIC SYSTEM TIMING

Spec Number 518055

870

HS-80C86RH

Interrupt Operations

External Interface

Interrupt operations fall into two classes: software or hard-

ware initiated. The software initiated interrupts and software

aspects of hardware interrupts are speciﬁed in the Instruc-

tion Set Description. Hardware interrupts can be classiﬁed

as non-maskable or maskable.

Processor RESET and lnitialization

Processor initialization or start up is accomplished with acti-

vation (HIGH) of the RESET pin. The HS-80C86RH RESET

is required to be HIGH for greater than 4 CLK cycles. The

HS-80C86RH will terminate operations on the high-going

edge of RESET and will remain dormant as long as RESET

is HIGH. The low-going transition of RESET triggers an

internal reset sequence for approximately 7 CLK cycles.

After this interval, the HS-80C86RH operates normally

beginning with the instruction in absolute location FFFFOH.

(See Figure 2). The RESET input is internally synchronized

to the processor clock. At initialization, the HIGH-to-LOW

transition of RESET must occur no sooner than 50µs (or

4 CLK cycles, whichever is greater) after power-up, to allow

complete initialization of the HS-80C86RH.

Interrupts result in a transfer of control to a new program

location. A 256-element table containing address pointers to

the interrupt service routine locations resides in absolute

locations 0 through 3FFH, which are reserved for this pur-

pose. Each element in the table is 4 bytes in size and corre-

sponds to an interrupt “type”. An interrupting device supplies

an 8-bit type number during the interrupt acknowledge

sequence, which is used to “vector” through the appropriate

element to the interrupt service routine location. All ﬂags and

both the Code Segment and Instruction Pointer register are

saved as part of the INTA sequence. These are restored

upon execution of an Interrupt Return (lRET) instruction.

NMl will not be recognized prior to the second clock cycle fol-

lowing the end of RESET. If NMI is asserted sooner than

9 CLK cycles after the end of RESET, the processor may

execute one instruction before responding to the interrupt.

Non-Maskable Interrupt (NMI)

The processor provides a single non-maskable interrupt pin

(NMl) which has higher priority than the maskable interrupt

request pin (INTR). A typical use would be to activate a

power failure routine. The NMl is edge-triggered on a LOW-

to-HIGH transition. The activation of this pin causes a type 2

interrupt.

Bus Hold Circuitry

To avoid high current conditions caused by ﬂoating inputs to

CMOS devices and to eliminate need for pull- up/down resis-

tors, “bus-hold” circuitry has been used on the HS-80C86RH

pins 2-16, 26-32 and 34-39. (See Figure 4A and 4B). These

circuits will maintain the last valid logic state if no driving

source is present (i.e. an unconnected pin or a driving

source which goes to a high impedance state). To overdrive

the “bus hold” circuits, an external driver must be capable of

supplying approximately 400µA minimum sink or source cur-

rent at valid input voltage levels. Since this “bus hold” cir-

cuitry is active and not a “resistive” type element, the

associated power supply current is negligible and power dis-

sipation is signiﬁcantly reduced when compared to the use

of passive pull-up resistors.

NMl is required to have a duration in the HIGH state of

greater than 2 CLK cycles, but is not required to be synchro-

nized to the clock. Any positive transition of NMl is latched

on-chip and will be serviced at the end of the current instruc-

tion or between whole moves of a block-type instruction.

Worst case response to NMl would be for multiply, divide,

and variable shift instructions. There is no speciﬁcation on

the occurrence of the low-going edge; it may occur before,

during or after the servicing of NMl. Another positive edge

triggers another response if it occurs after the start of the

NMl procedure. The signal must be free of logical spikes in

general and be free of bounces on the low-going edge to

avoid triggering extraneous responses.

EXTERNAL

BOND

PAD

Maskable Interrupt (INTR)

OUTPUT

DRIVER

The HS-80C86RH provides a single interrupt request input

(INTR) which can be masked internally by software with the

resetting of the interrupt enable ﬂag (IF) status bit. The inter-

rupt request signal is level triggered. It is internally synchro-

nized during each clock cycle on the high-going edge of

CLK. To be responded to, INTR must be present (HIGH) dur-

ing the clock period preceding the end of the current instruc-

tion or the end of a whole move for a block- type instruction.

INTR may be removed anytime after the falling edge of the

ﬁrst INTA signal. During the interrupt response sequence fur-

ther interrupts are disabled. The enable bit is reset as part of

the response to any interrupt (INTR, NMl, software interrupt

or single-step), although the FLAGS register which is auto-

matically pushed onto the stack reﬂects the state of the pro-

cessor prior to the interrupt. Until the old FLAGS register is

restored the enable bit will be zero unless speciﬁcally set by

an instruction.

INPUT

BUFFER

INPUT

PROTECTION

CIRCUITRY

FIGURE 4A. BUS HOLD CIRCUITRY PIN 2-16, 34-39

EXTERNAL

BOND

PAD

VCC

P

OUTPUT

DRIVER

INPUT

BUFFER

INPUT

PROTECTION

CIRCUITRY

FIGURE 4B. BUS HOLD CIRCUITRY PIN 26-32

Spec Number 518055

871

HS-80C86RH

During the response sequence (Figure 5) the processor exe- External Synchronization Via TEST

cutes two successive (back-to-back) interrupt acknowledge

As an alternative to interrupts, the HS-80C86RH provides a

cycles. The HS-80C86RH emits the LOCK signal (Max

mode only) from T2 of the ﬁrst bus cycle until T2 of the sec-

ond. A local bus “hold” request will not be honored until the

end of the second bus cycle. In the second bus cycle, a byte

is supplied to the HS-80C86RH by the HS-82C89ARH Inter-

rupt Controller, which identiﬁes the source (type) of the inter-

rupt. This byte is multiplied by four and used as a pointer into

the interrupt vector lookup table. An INTR signal left HIGH

will be continually responded to within the limitations of the

enable bit and sample period. The INTERRUPT RETURN

instruction includes a FLAGS pop which returns the status of

the original interrupt enable bit when it restores the FLAGS.

single software-testable input pin (TEST). This input is uti-

lized by executing a WAIT instruction. The single WAIT

instruction is repeatedly executed until the TEST input goes

active (LOW). The execution of WAIT does not consume bus

cycles once the queue is full.

If a local bus request occurs during WAIT execution, the HS-

80C86RH three-states all output drivers while inputs and I/O

pins are held at valid logic levels by internal bus-hold circuits.

If interrupts are enabled, the HS-80C86RH will recognize

interrupts and process them when it regains control of the

bus. The WAIT instruction is then refetched, and reexecuted.

Basic System Timing

T1

T3

T1

T2

T3

T4 TI

T2

T4

Typical system conﬁgurations for the processor operating in

minimum mode and in maximum mode are shown in Figures

6A and 6B, respectively. In minimum mode, the MN/MX pin

is strapped to VDD and the processor emits bus control sig-

nals (e.g. RD, WR, etc.) directly. In maximum mode, the

MN/MX pin is strapped to GND and the processor emits

coded status information which the 82C88 bus controller

used to generate MULTIBUS™ compatible bus control sig-

nals. Figure 3 shows the signal timing relationships.

ALE

LOCK

INTA

FLOAT

TYPE

VECTOR

AD0-

AD15

TABLE 10. HS-80C86RH REGISTER MODEL

FIGURE 5. INTERRUPT ACKNOWLEDGE SEQUENCE

AX

BX

CX

DX

AH

BH

CH

DH

AL

BL

CL

DL

ACCUMULATOR

BASE

Halt

COUNT

When a software “HALT” instruction is executed the pro- ces-

sor indicates that it is entering the “HALT” state in one of two

ways depending upon which mode is strapped. In minimum

mode, the processor issues one ALE with no qualifying bus

control signals. In maximum mode the processor issues

appropriate HALT status on S2, S1, S0 and the 82C88 bus

controller issues one ALE. The HS-80C86RH will not leave

the “HALT” state when a local bus “hold” is entered while in

“HALT”. In this case, the processor reissues the HALT indi-

cator at the end of the local bus hold. An NMl or interrupt

request (when interrupts enabled) or RESET will force the

HS-80C86RH out of the “HALT” state.

DATA

SP

BP

SI

STACK POINTER

BASE POINTER

SOURCE INDEX

DESTINATION INDEX

DI

IP

INSTRUCTION POINTER

STATUS FLAGS

FLAGSH

FLAGSL

CS

DS

SS

ES

CODE SEGMENT

DATA SEGMENT

STACK SEGMENT

EXTRA SEGMENT

Read/Modify/Write (Semaphore)

Operations Via Lock

MULTIBUS™ is an Intel Trademark

The LOCK status information is provided by the processor

when consecutive bus cycles are required during the execu-

tion of an instruction. This gives the processor the capability

of performing read/modify/write operations on memory (via

the Exchange Register With Memory instruction, for exam-

ple) without another system bus master receiving interven-

ing memory cycles. This is useful in multiprocessor system

conﬁgurations to accomplish “test and set lock” operations.

The LOCK signal is activated (forced LOW) in the clock cycle

following decoding of the software “LOCK” preﬁx instruction.

It is deactivated at the end of the last bus cycle of the

instruction following the “LOCK” preﬁx instruction. While

LOCK is active a request on a RQ/GT pin will be recorded

and then honored at the end of the LOCK.

System Timing - Minimum System

The read cycle begins in T1 with the assertion of the

Address Latch Enable (ALE) signal. The trailing (low-going)

edge of this signal is used to latch the address information,

which is valid on the address/data bus (AD0-AD15) at this

time, into the 82C82 latches. The BHE and A0 signals

address the low, high or both bytes. From T1 to T4 the M/IO

signal indicates a memory or I/O operation. At T2, the

address is removed from the address/data bus and the bus

is held at the last valid logic state by internal bus hold

devices. The read control signal is also asserted at T2. The

read (RD) signal causes the addressed device to enable its

data bus drivers to the local bus. Some time later, valid data

Spec Number 518055

872

HS-80C86RH

will be available on the bus and the addressed device will Bus Timing - Medium and Large Size Systems

drive the READY line HIGH. When the processor returns the

For medium complexity systems the MN/MX pin is

read signal to a HIGH level, the addressed device will three-

connected to GND and the 82C88 Bus Controller is added to

state its bus drivers. If a transceiver is required to buffer the

the system as well as three 82C82 latches for latching the

HS-80C86RH local bus, signals DT/R and DEN are provided

system address, and a transceiver to allow for bus loading

by the HS-80C86RH.

greater than the HS-80C86RH is capable of handling. Bus

A write cycle also begins with the assertion of ALE and the control signals are generated by the 82C88 instead of the

emission of the address. The M/IO signal is again asserted processor in this conﬁguration, although their timing remains

to indicate a memory or I/O write operation. In T2, immed- relatively the same. The HS-80C86RH status outputs (S2,

iately following the address emission, the processor emits S1, and S0) provide type-of-cycle information and become

the data to be written into the addressed location. This data 82C88 inputs. This bus cycle information speciﬁes read

remains valid until at least the middle of T4. During T2, T3 (code, data or I/O), write (data or I/O), interrupt acknowl-

and TW, the processor asserts the write control signal. The edge, or software halt. The 82C88 issues control signals

write (WR) signal becomes active at the beginning of T2 as specifying memory read or write, I/O read or write, or inter-

opposed to the read which is delayed somewhat into T2 to rupt acknowledge. The 82C88 provides two types of write

provide time for output drivers to become inactive.

strobes, normal and advanced, to be applied as required.

The normal write strobes have data valid at the leading edge

of write. The advanced write strobes have the same timing

as read strobes, and hence, data is not valid at the leading

edge of write. The transceiver receives the usual T and 0E

inputs from the 82C88 DT/R and DEN signals.

The BHE and A0 signals are used to select the proper

byte(s) of the memory/IO word to be read or written accord-

ing to Table 11.

TABLE 11.

For large multiple processor systems, the 82C89 bus arbiter

must be added to the system to provide system bus man-

agement. In this case, the pointer into the interrupt vector

table, which is passed during the second INTA cycle, can be

derived from an HS-82C59ARH located on either the local

bus or the system bus. The processor’s INTA output should

drive the SYSB/RESB input of the 82C89 to the proper state

when reading the interrupt vector number from the HS-

82C59ARH during the interrupt acknowledge sequence and

software “poll”.

BHE

A0

0

CHARACTERISTICS

0

1

Whole word

1

Upper byte from/to odd address

Lower byte from/to even address

None

0

1

A Note on Radiation Hardened Product Availability

There are no immediate plans to develop the 82C88 Bus

Controller or the 82C89 Arbiter as radiation hardened

integrated circuits.

I/O ports are addressed in the same manner as memory

location. Even addressed bytes are transferred on the D7-D0

bus lines and odd address bytes on D15-D6.

A Note on SEU Capability of the HS-80C86RH

The basic difference between the interrupt acknowledge

cycle and a read cycle is that the interrupt acknowledge sig-

nal (INTA) is asserted in place of the read (RD) signal and

the address bus is held at the last valid logic state by internal

bus hold devices. (See Figure 4). In the second of two suc-

cessive INTA cycles a byte of information is read from the

data bus (D7-D0) as supplied by the interrupt system logic

(i.e. HS-82CS9ARH Priority Interrupt Controller). This byte

identiﬁes the source (type) of the interrupt. It is multiplied by

four and used as a pointer into an interrupt vector Iookup

table, as described earlier.

Previous heavy ion testing of the HS-80C86RH has indi-

cated that the SEU threshold of this part is about 6

MEV/mg/cm². Based upon these results and other analysis,

a deep space galactic cosmic-ray environment will result in

an SEU rate of about 0.08 upsets/day.

Spec Number 518055

873

HS-80C86RH

VDD

CLK

GND

MRDC

MN/MX

S0

HS-82C85RH

CLOCK

CONTROLLER/

GENERATOR

RDY

CLK

MWTC

AMWC

IORC

S0

82C88

BUS

CTRLR

NC

READY

RESET

S1

S2

S1

S2

RES

IOWC

AIOWC

INTA

DEN

DT/R

ALE

HS-80C86RH

CPU

NC

LOCK

WAIT

STATE

GND

VDD

GENERATOR

STB

OE

GND

ADDR/DATA

GND

1

AD0-AD15

A16-A19

ADDR

82C82

(2 OR 3)

C1

C2

BHE

GND

20

T/R

OE

VDD

40

DATA

HS-82C08RH

TRANSCEIVER

(2)

C1 = C2 = 0.1µF

A0

BHE

E

G

CS

RD WR

W

E

HS-6617RH

CMOS

CMOS PROM (2)

HS-82CXXRH

HS-65262RH

CMOS RAM (16)

16K x 1

PERIPHERALS

2K x 8 2K x 8

FIGURE 6A. MAXIMUM MODE HS-80C86RH TYPICAL CONFIGURATION

VDD

MN/MX

M/IO

HS-82C85RH

CLK

CLOCK

CONTROLLER/

GENERATOR

RDY

READY INTA

RES

RD

RESET

WR

DT/R

DEN

WAIT

STATE

HS-80C86RH

CPU

GND

VDD

GENERATOR

ALE

STB

OE

GND

ADDR/DATA

GND

1

AD0-AD15

A16-A19

ADDR

82C82

(2 OR 3)

C1

C2

BHE

GND

20

T/R

VDD

40

OE

DATA

HS-82C08RH

TRANSCEIVER

(2)

C1 = C2 = 0.1µF

A0

BHE

E

G

CS

RD WR

OPTIONAL

FOR INCREASED

DATA BUS DRIVE

W

E

HS-6617RH

CMOS PROM (2)

CMOS

HS-82CXXRH

PERIPHERALS

HS-65262RH

CMOS RAM (16)

16K x 1

2K x 8 2K x 8

FIGURE 6B. MINIMUM MODE HS-80C86RH TYPICAL CONFIGURATION

Spec Number 518055

874

HS-80C86RH

Waveforms

T1

T2

T3

T4

TCL2CL1

TCH1CH2

TW

CLK (HS-82C85RH OUTPUT)

TCLDV

TCLAX

TCLAV

TCLDX2

AD15-AD0

DATA OUT

AD15-AD0

DEN

TWHDX

TCVCTV

TCVCTX

WRITE CYCLE

(NOTE 1)

(RD, INTA,

TCVCTV

TCLAZ

DT/R = VOH)

TWLWH

WR

TCVCTX

TCLDX1

TDVCL

POINTER

AD15-AD0

TCHCTV

DT/R

INTA

INTA CYCLE

(NOTES 1, 3)

(RD, WR = VOH

BHE = VOL)

TCVCTV

TCVCTX

TCVCTV

DEN

SOFTWARE

HALT -

INVALID ADDRESS

SOFTWARE HALT

AD15-AD0

DEN, RD,

WR, INTA = VOH

TCLAV

DT/R = INDETERMINATE

FIGURE 7. BUS TIMING - MINIMUM MODE SYSTEM

NOTES:

1. All signals switch between VOH and VOL unless otherwise speciﬁed.

2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

3. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control signals are

shown for the second INTA cycle.

4. Signals at HS-82C85RH are shown for reference only.

5. All timing measurements are made at 1.5V unless otherwise noted.

Spec Number 518055

875

HS-80C86RH

Waveforms (Continued)

T1

T2

T3

TCL2CL1

T4

TCH1CH2

TW

TCLCL

CLK (HS-82C85RH OUTPUT)

TCHCTV

TCLAV

TCHCL

TCHCTV

TCLCH

M/IO

TCLDV

TCLAX

TCLAV

TCLLH

BHE, A19-A16

TLHLL

S7-S3

BHE/S7, A19/S6-A16/S3

TLLAX

ALE

TCHLL

TAVLL

TR1VCL

VIH

VIL

RDY (HS-82C85RH INPUT)

SEE NOTE 4

TCLRIX

TRYLCL

READY (HS-80C86RH INPUT)

TCHRYX

TCLDX1

TRYHCH

TCLAZ

TDVCL

DATA IN

TCLRH

AD15-AD0

TAZRL

AD15-AD0

TRHAV

RD

READ CYCLE

TCHCTV

(NOTE 1)

TCLRL

TRLRH

TCHCTV

(WR, INTA = VOH)

DT/R

DEN

TCVCTX

TCVCTV

FIGURE 8. BUS TIMING - MINIMUM MODE SYSTEM

NOTES:

1. All signals switch between VOH and VOL unless otherwise speciﬁed.

2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

3. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control signals are

shown for the second INTA cycle.

4. Signals at HS-82C85RH are shown for reference only.

5. All timing measurements are made at 1.5V unless otherwise noted.

Spec Number 518055

876

HS-80C86RH

Waveforms (Continued)

T1

T2

T3

T4

TCH1CH2

TCL2CL1 TW

TCLCL

CLK

TCLAV

TCHCL

TCLCH

QS0, QS1

TCHSV

TCLSH

S2, S1, S0 (EXCEPT HALT)

(SEE NOTE 8)

TCLAV

TCLDV

TCLAX

TCLAV

BHE/S7, A19/S6-A16/S3

BHE, A19-A16

S7-S3

TSVLH

TCLLH

TCHLL

ALE (82C88 OUTPUT)

NOTE 5

TR1VCL

RDY

(HS-82C85RH INPUT)

TCLR1X

TRYLCL

TCHRYX

READY (HS-80C86RH INPUT)

TRYHSH

TCLAZ

TCLAX

TRYHCH

TDVCL

DATA IN

TCLRH

TCLDX1

READ CYCLE

AD15-AD0

TCLAV

AD15-AD0

TAZRL

TRHAV

RD

TCHDTL

TCHDTH

TRLRH

TCLRL

DT/R

TCLML

TCLMH

82C88

OUTPUTS

SEE NOTES

5, 6

MRDC OR IORC

DEN

TCVNV

TCVNX

FIGURE 9. BUS TIMING - MAXIMUM MODE SYSTEM

NOTES:

1. All signals switch between VOH and VOL unless otherwise speciﬁed.

2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

3. Cascade address is valid between first and second INTA cycle.

4. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control for pointer ad-

dress is shown for the second INTA cycle.

5. Signals at HS-82C85RH or 82C88 are shown for reference only.

6. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active

high 82C88 CEN.

7. All timing measurements are made at 1.5V unless otherwise noted.

8. Status inactive in state just prior to T4.

Spec Number 518055

877

HS-80C86RH

Waveforms (Continued)

T1

T2

T3

T4

TW

CLK

TCHSV

(SEE NOTE 8)

TCLDX2

S2, S1, S0 (EXCEPT HALT)

TCLSH

TCLDV

TCLAX

TCLAV

WRITE CYCLE

AD15-AD0

TCVNV

DEN

TCLMH

82C88

OUTPUTS

TCLML

TCVNX

SEE NOTES

5, 6

AMWC OR AIOWC

TCLMH

TCLML

MWTC OR IOWC

INTA CYCLE

AD15-AD0

RESERVED FOR

CASCADE ADDR

(SEE NOTES 3, 4)

TCLAZ

TDVCL

TCLDX1

AD15-AD0

POINTER

TSVMCH

TCLMCL

MCE/PDEN

TCLMCH

DT/R

TCHDTL

TCHDTH

82C88 OUTPUTS

SEE NOTES 5, 6

TCLML

INTA

DEN

TCLMH

TCVNV

TCVNX

SOFTWARE

HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH

INVALID ADDRESS

AD15-AD0

TCLAV

S2

TCLSH

TCHSV

FIGURE 10. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88)

NOTES:

1. All signals switch between VOH and VOL unless otherwise speciﬁed.

2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

3. Cascade address is valid between first and second INTA cycle.

4. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control for pointer ad-

dress is shown for the second INTA cycle.

5. Signals at HS-82C85RH or 82C88 are shown for reference only.

6. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active

high 82C88 CEN.

7. All timing measurements are made at 1.5V unless otherwise noted.

8. Status inactive in state just prior to T4.

Spec Number 518055

878

HS-80C86RH

Waveforms (Continued)

CLK

TINVCH (SEE NOTE)

NMI

INTR

TEST

NOTE: Setup Requirements for

asynchronous signals only to

guarantee recognition at next CLK.

SIGNAL

FIGURE 11. ASYNCHRONOUS SIGNAL RECOGNITION

≥ 50µs

ANY CLK CYCLE

VCC

ANY CLK CYCLE

CLK

TCLAV

TCLDX

TDVCL

LOCK

RESET

≥ 4 CLK CYCLES

FIGURE 12. BUS LOCK SIGNAL TIMING (MAXIMUM MODE

ONLY)

FIGURE 13. RESET TIMING

TCLGL

ANY

CLK

≥ 0-CLK

CYCLES

TCLGH

CYCLE

CLK

TGVCH

TCLGH

TCLCL

TCHGX

PULSE 2

HS-80C86RH

RQ/GT

PREVIOUS GRANT

GT

PULSE 3

PULSE 1

COPROCESSOR

RELEASE

COPROCESSOR

TCLAZ

TCHSZ

RQ

AD15-AD0

HS-80C86RH

(SEE NOTE) TCHSV

RD, LOCK

BHE/S7, A19/S6-A16/S3

S2, S1, S0

NOTE: The coprocessor may not drive the buses outside the region shown without risking contention.

FIGURE 14. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

≥ 1CLK

CYCLE

1 OR 2

CYCLES

CLK

THVCH

HOLD

HLDA

TCLHAV

TCLAZ

COPROCESSOR

TCHSZ

80C86

AD15-AD0

BHE/S7, A19/S6-A16/S3

RD, WR, M/IO, DT/R, DEN

FIGURE 15. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

Spec Number 518055

879

HS-80C86RH

AC Testing Input, Output Waveform

AC Test Circuit

INPUT

VIH

VIL - 0.4V

OUTPUT

VOH

OUTPUT FROM

DEVICE UNDER TEST

TEST POINT

1.5V

CL (Note)

VOH

NOTE: All inputs signals (other than CLK) must switch between VIL

Max -0.4V and VIH Min +0.4. CLK must switch between 0.4V

and VDD -0.4V. TR and TF must be less than or equal to

15ns. CLK TR and TF must be less than or equal to 10ns.

NOTE: Includes stray and jig capacitance.

Burn-In Circuits

HS-80C86RH 40 PIN DIP

VDD

1

2

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

1

2

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

F15

F14

F13

F12

F11

F10

F9

F16

3

LOAD

MN/MX

LOAD

3

4

5

6

7

8

9

F8

9

10

11

12

13

14

15

16

17

18

19

20

F7

10

11

12

13

14

15

16

17

F6

F5

LOAD

F4

F3

F2

F1

NMI

18

F0

CLK

READY

RESET

19

20

VDD

2.7KΩ

LOAD

T

≥ 5.0µs

T

2.7KΩ

STATIC

DYNAMIC

VDD = +6.5V ±10%

TA = +125 C Minimum

Part is Static Sensitive

Voltages Must Be Ramped 2.7kΩ ±5% (Pins 2-16, 39)

Resistors:

10kΩ ±10%

(Pins 17, 18, 21-23, 31, 33)

VDD = 6.5V ±5% (Burn-In)

VDD = 6.0V ±5% (Life Test)

TA = +125 C

Package: 40 Lead DIP

Part is Static Sensitive

Voltage Must Be Ramped

Resistors:

o

10kΩ (Pins 17, 18, 21, 22, 23, 33)

3.3kΩ (Pins 2-16, 19, 30, 31, 39)

2.7kΩ Loads As Indicated

All Resistors Are At Least 1/8W,

±10%

F0 = 100kHz, F1 = F0/2, F2 = F1/2 . . .

RESET, NMI low after initialization.

READY pulsed low every 320ms

MN/MX changes state every 5.24s

o

Package: 40 Lead DIP

1.0kΩ ±5% 1/10W Min (Pin 19)

Minimum of 5 CLK Pulses

After Initial Pulses, CLK is Left High

Pulses are 50% Duty Cycle Square

Wave

Spec Number 518055

880

HS-80C86RH

Burn-In Circuits (Continued)

HS-80C86RH 42 LEAD FLATPACK

VDD

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

F15

F14

F13

F12

F11

F10

F9

F16

3

OPEN

LOAD

3

4

5

6

7

8

F8

9

MN/MX

LOAD

9

F7

10

11

12

13

14

10

11

12

13

14

F6

F5

F4

LOAD

F3

F2

15

16

17

18

19

20

21

15

16

17

18

19

20

21

F1

NMI

F0

OPEN

READY

RESET

CLK

VDD

2.7kΩ

LOAD

2.7kΩ

STATIC

DYNAMIC

VDD = +6.5V ±10%

TA = +125 C Minimum

Part is Static Sensitive

Voltages Must Be Ramped 2.7kΩ ±5% (Pins 2-16, 41)

Package: 42 Lead Flatpack 1.0kΩ ±5% 1/10W Min (Pin 20)

Minimum of 5 CLK Pulses

Resistors:

10kΩ ±10%

(Pins 18, 19, 22-24, 32, 34)

VDD = 6.5V ±5% (Burn-In)

VDD = 6.0V ±5% (Life Test)

TA = +125 C

Package: 42 Lead Flatpack

Part is Static Sensitive

Voltage Must Be Ramped

Resistors:

o

10kΩ (Pins 17, 18, 19, 22, 23, 24, 34)

3.3kΩ (Pins 2-16, 20, 31, 32, 41)

2.7kΩ Loads As Indicated

All Resistors Are At Least 1/8W, ±10%

F0 = 100kHz, F1 = F0/2, F2 = F1/2 . . .

RESET, NMI low after initialization.

READY pulsed low every 320µs

MN/MX changes state every 5.24s

o

After Initial Pulses, CLK is Left High

Pulses are 50% Duty Cycle Square

Wave

Spec Number 518055

881

HS-80C86RH

Timing Diagrams

F5

READY

4T

READY TIMING AS COMPARED TO F5

F14

F16

PULSE

RESET

NMI

RESET, NMI, AND MN/MX TIMING AS COMPARED TO F14 AND F16

F0 = 100kHz, 50% duty cycle square wave.

F1 = F0/2, F2 = F1/2 . . . F16 = F15/2.

RESET has a pulse width = 8T and occurs every two cycles of F16.

NMI has a pulse width = 4T and occurs every two cycles of F16.

READY, RESET, and NMI timing are as shown below:

T = 10µs.

MN/MX is a 50% duty cycle square wave and changes every eight

cycles of F16.

All signals have rise/fall time limits:

100ns < t-rise, t-fall < 500ns

Irradiation Circuit

VDD

1

VSS

VCC 40

R2

LOAD

2

3

4

5

6

7

8

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

R2

LOAD

2.7KΩ

LOAD

R2

MN/MX

R3

R2

LOAD

R2

9

R2

10

HOLD

HLDA

R2

11

LOAD

R2

12

R2

13

R2

14

R2

15

R2

16

R3

LOAD

R3

17

NMI

R3

18

TEST

READY

RESET

INTR

CLK

R3

19

CLOCK

20 GND

RESET

NOTES:

1. VDD = 5.0V ± 0.5V

4. Clock and reset should be brought out separately so they can be

toggled before irradiation.

2. R2 = 3.3kΩ, R3 = 47kΩ

5. Group E Sample Size is 2 Die/Wafer.

3. Pins Tied to GND: 1-18, 20, 23, 39

Pins Tied to VCC: 22, 31, 33, 40

Pins With Loads: 24-29, 30, 32, 34-38

Pins Brought Out: 19 (Clock), 21 (Reset)

Spec Number 518055

882

HS-80C86RH

Intersil Space Level Product Flow - Q

All Lots - Wafer Lot Acceptance (Including SEM)

Method 5007

100% Interim Electrical Test 1 (T1)

100% Delta Calculation (T0-T1)

Each Wafer - GAMMA Radiation Veriﬁcation,

Two samples/wafer, 0 rejects, Method 1019

100% PDA 1, Method 5004 (Note 1)

100% Dynamic Burn-In, Condition D, 240 hours, +125^oC or

Equivalent Per Method 1015

100% Nondestructive Bond Pull, Method 2023

Sample - Wire Bond Pull Monitor, Method 2011

Sample - Die Shear Monitor, Method 2019 or 2027

100% Internal Visual Inspection, Method 2010, Condition A

100% Interim Electrical Test 2 (T2)

100% Delta Calculation (T0-T2)

100% PDA 2, Method 5004 (Note 2)

100% Final Electric Test (T3)

100% Temperature Cycle - Method 1010, Condition C,

10 cycles

100% Fine/Gross Leak, Method 1014

100% Radiographic, Method 2012 (Note 3)

100% External Visual, Method 2009

Sample - Group A, Method 5005 (Note 4)

Sample - Group B, Method 5005 (Note 5)

Sample - Group D, Method 5005 (Notes 5, 6)

100% Data Package Generation (Note 6)

100% Constant Acceleration, Method 2001, Condition

Per Method 5004

100% PIND - Method 2020, Condition A

100% External Visual

100% Serialization

100% Initial Electrical Test (T0)

100% Static Burn-In 1, Method 1015, Condition A or B,

72 Hours Minimum, 125^oC minimum

NOTES:

1. Modiﬁed SEM Inspection, not compliant to MIL-STD-883, Method 2018. This device does not meet the Class S minimum metal step cov-

5

2

erage of 50%. The metal does meet the current density requirement of <2 E A/cm . Data provided upon request.

2. Failures from subgroups 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the

failures from subgroup 7.

3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.

4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.

5. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include

separate line items for Group B test, Group B samples, Group D tests and Group D samples.

6. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the

P.O. should include separate line items for Group D generic data. Generic Data is not guaranteed to be available and is therefore not

available in all cases.

7. Data Package Contents:

• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quan-

tity). Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos with percent of step coverage.

• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, test package used, speciﬁcation numbers, test

equipment, etc. Radiation Read and Record data on ﬁle at Intersil.

• X-Ray Report and Film, including penetrameter measurements.

• Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).

• Variables Data (All Delta operations). Data is identiﬁed by serial number. Data header includes lot number and date of test.

• Group B and D attributes and/or Generic data is included when required by P.O.

• The Certiﬁcate of Conformance is a part of the shipping invoice and is not part of Data Book. The Certiﬁcate of Conformance

is signed by an authorized Quality Representative.

Spec Number 518055

883

HS-80C86RH

Intersil Space Level Product Flow - 8

Each Wafer - GAMMA Radiation Veriﬁcation,

2 samples/wafer, 0 rejects, Method 1019

100% Interim Electrical Test

100% PDA, Method 5004 (Note 1)

100% Final Electric Test

100% Die Attach

Periodic - Wire Bond Pull Monitor, Method 2011

Periodic - Die Shear Monitor, Method 2019 or 2027

100% Internal Visual Inspection, Method 2010, Condition B

CSI and/or GSI PreCap (Note 5)

100% Fine/Gross Leak, Method 1014

100% External Visual, Method 2009

Sample - Group A, Method 5005 (Note 2)

Sample - Group B, Method 5005 (Note 3)

Sample - Group C, Method 5005 (Notes 3, 4)

Sample - Group D, Method 5005 (Notes 3, 4)

100% Data Package Generation (Note 6)

CSI and/or GSI Final (Note 5)

100% Temperature Cycle, Method 1010, Condition C,

10 cycles

100% Constant Acceleration, Method 2001, Condition Per

Method 5004

100% External Visual

100% Initial Electrical Test

100% Dynamic Burn-In, Condition D, 160 hours, +125^oC, or

Equivalent, Per Method 1015

NOTES:

1. Failures from subgroups 1, 7 are used for calculating PDA. The maximum allowable PDA = 5%.

2. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005 may be performed.

3. Group B, C, and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include

separate line items for Group B Test, Group C Test, Group C Samples, Group D Test and Group D Samples.

4. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When

required, the P.O. should include separate line items for Group D generic data. Generic Data is not guaranteed to be available and is

therefore not available in all cases.

5. CSI and /or GSI inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include

separate line items for CSI PreCap inspection, CSI final inspection, GSI PreCap inspection, and/or GSI final inspection.

6. Data Package Contents:

• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quan-

tity).

• GAMMA Radiation Report. Contains Cover page, disposition, RAD Dose, Lot Number, test package used, speciﬁcation numbers, test

equipment, etc. Radiation Read and Record data on ﬁle at Intersil.

• Screening, Electrical, and Group A attributes (Screening attributes begins at Initial Electrical Test).

• Group B, C and D attributes and/or Generic data is included when required by P.O.

• Variables Data (All Delta operations) Data is identiﬁed by serial number. Data header includes lot number and date of test.

• Group B and D attributes and/or Generic data is included when required by P.O.

• The Certiﬁcate of Conformance is a part of the shipping invoice and is not part of Data Book. The Certiﬁcate of Conformance is signed by

an authorized Quality Representative.

Spec Number 518055

884

HS-80C86RH

Metallization Topology

DIE DIMENSIONS:

6370µm x 7420µm x 485µm

GLASSIVATION:

Thickness: 8kÅ ±1kÅ

METALLIZATION:

Type: Al/S

WORST CASE CURRENT DENSITY:

<2 x 10⁵A/cm²

Thickness: 11kÅ ±2kÅ

Metallization Mask Layout

HS-80C86RH

(36) A18/S5

(35) A19/S6

AD10 (6)

AD9 (7)

(34) BHE/S7

(33) MN/MX

AD8 (8)

AD7 (9)

(32) RD

(31) RQ/GT0

AD6 (10)

AD5 (11)

(30) RQ/GT1

AD4 (12)

AD3 (13)

(29) LOCK

(28) S2

AD2 (14)

AD1 (15)

(27) S1

(26) S0

AD0 (16)

Spec Number 518055

885

HS-80C86RH

Instruction Set Summary

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

7 6 5 4 3 2 1 0

DATA TRANSFER

MOV = MOVE:

Register/Memory to/from Register

Immediate to Register/Memory

Immediate to Register

Memory to Accumulator

Accumulator to Memory

Register/Memory to Segment Register ††

Segment Register to Register/Memory

PUSH = Push:

1 0 0 0 1 0 d w

1 1 0 0 0 1 1 w

1 0 1 1 w reg

mod reg r/m

mod 0 0 0 r/m

data

data if w 1

addr-high

1 0 1 0 0 0 0 w

1 0 1 0 0 0 1 w

1 0 0 0 1 1 1 0

1 0 0 0 1 1 0 0

addr-low

mod 0 reg r/m

Register/Memory

1 1 1 1 1 1 1 1

0 1 0 1 0 reg

0 0 0 reg 1 1 0

mod 1 1 0 r/m

Register

Segment Register

POP = Pop:

Register/Memory

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 reg 1 1 1

mod 0 0 0 r/m

Register

Segment Register

XCHG = Exchange:

Register/Memory with Register

Register with Accumulator

IN = Input from:

1 0 0 0 0 1 1 w

1 0 0 1 0 reg

mod reg r/m

port

Fixed Port

1 1 1 0 0 1 0 w

1 1 1 0 1 1 0 w

Variable Port

OUT = Output to:

Fixed Port

1 1 1 0 0 1 1 w

1 1 1 0 1 1 1 w

1 1 0 1 0 1 1 1

1 0 0 0 1 1 0 1

1 1 0 0 0 1 0 1

1 1 0 0 0 1 0 0

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

1 0 0 1 1 1 0 0

1 0 0 1 1 1 0 1

port

Variable Port

XLAT = Translate Byte to AL

LEA = Load EA to Register2

LDS = Load Pointer to DS

LES = Load Pointer to ES

LAHF = Load AH with Flags

SAHF = Store AH into Flags

PUSHF = Push Flags

POPF = Pop Flags

mod reg r/m

Spec Number 518055

886

HS-80C86RH

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

7 6 5 4 3 2 1 0

data if s:w = 01

ARITHMETIC

ADD = Add:

Register/Memory with Register to Either

Immediate to Register/Memory

Immediate to Accumulator

ADC = Add with Carry:

0 0 0 0 0 0 d w

1 0 0 0 0 0 s w

0 0 0 0 0 1 0 w

mod reg r/m

mod 0 0 0 r/m

data

data if w = 1

Register/Memory with Register to Either

Immediate to Register/Memory

Immediate to Accumulator

INC = Increment:

0 0 0 1 0 0 d w

1 0 0 0 0 0 s w

0 0 0 1 0 1 0 w

mod reg r/m

mod 0 1 0 r/m

data

data if w = 1

Register/Memory

1 1 1 1 1 1 1 w

0 1 0 0 0 reg

mod 0 0 0 r/m

Register

AAA = ASCll Adjust for Add

DAA = Decimal Adjust for Add

SUB = Subtract:

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

Register/Memory and Register to Either

Immediate from Register/Memory

Immediate from Accumulator

SBB = Subtract with Borrow

Register/Memory and Register to Either

Immediate from Register/Memory

Immediate from Accumulator

DEC = Decrement:

0 0 1 0 1 0 d w

1 0 0 0 0 0 s w

0 0 1 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

data if s:w = 01

data if w = 1

0 0 0 1 1 0 d w

1 0 0 0 0 0 s w

0 0 0 1 1 1 0 w

mod reg r/m

mod 0 1 1 r/m

data

data if w = 1

Register/Memory

1 1 1 1 1 1 1 w

0 1 0 0 1 reg

mod 0 0 1 r/m

mod 0 1 1 r/m

Register

NEG = Change Sign

1 1 1 1 0 1 1 w

CMP = Compare:

Register/Memory and Register

Immediate with Register/Memory

Immediate with Accumulator

AAS = ASCll Adjust for Subtract

DAS = Decimal Adjust for Subtract

MUL = Multiply (Unsigned)

IMUL = Integer Multiply (Signed)

AAM = ASCll Adjust for Multiply

DlV = Divide (Unsigned)

0 0 1 1 1 0 d w

1 0 0 0 0 0 s w

0 0 1 1 1 1 0 w

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

1 1 1 1 0 1 1 w

1 1 0 1 0 1 0 0

1 1 1 1 0 1 1 w

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

mod reg r/m

mod 1 1 1 r/m

data

data if s:w = 01

data if w = 1

mod 1 0 0 r/m

mod 1 0 1 r/m

0 0 0 0 1 0 1 0

mod 1 1 0 r/m

mod 1 1 1 r/m

0 0 0 0 1 0 1 0

IDlV = Integer Divide (Signed)

AAD = ASClI Adjust for Divide

CBW = Convert Byte to Word

CWD = Convert Word to Double Word

Spec Number 518055

887

HS-80C86RH

Instruction Set Summary (Continued)

INSTRUCTION CODE

MNEMONIC AND DESCRIPTION

7 6 5 4 3 2 1 0

LOGIC

NOT = Invert

1 1 1 1 0 1 1 w

1 1 0 1 0 0 v w

mod 0 1 0 r/m

SHL/SAL = Shift Logical/Arithmetic Left

SHR = Shift Logical Right

SAR = Shift Arithmetic Right

ROL = Rotate Left

mod 1 0 0 r/m

mod 1 0 1 r/m

mod 1 1 1 r/m

mod 0 0 0 r/m

mod 0 0 1 r/m

mod 0 1 0 r/m

mod 0 1 1 r/m

ROR = Rotate Right

RCL = Rotate Through Carry Flag Left

RCR = Rotate Through Carry Right

AND = And:

Reg./Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

TEST = And Function to Flags, No Result:

Register/Memory and Register

Immediate Data and Register/Memory

Immediate Data and Accumulator

OR = Or:

0 0 1 0 0 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 0 0 1 0 w

mod reg r/m

mod 1 0 0 r/m

data

data if w = 1

1 0 0 0 0 1 0 w

1 1 1 1 0 1 1 w

1 0 1 0 1 0 0 w

mod reg r/m

mod 0 0 0 r/m

data

data if w = 1

Register/Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

XOR = Exclusive or:

0 0 0 0 1 0 d w

1 0 0 0 0 0 0 w

0 0 0 0 1 1 0 w

mod reg r/m

mod 1 0 1 r/m

data

data if w = 1

Register/Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

STRING MANIPULATION

REP = Repeat

0 0 1 1 0 0 d w

1 0 0 0 0 0 0 w

0 0 1 1 0 1 0 w

mod reg r/m

mod 1 1 0 r/m

data

data if w = 1

1 1 1 1 0 0 1 z

1 0 1 0 0 1 0 w

1 0 1 0 0 1 1 w

1 0 1 0 1 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

MOVS = Move Byte/Word

CMPS = Compare Byte/Word

SCAS = Scan Byte/Word

LODS = Load Byte/Word to AL/AX

STOS = Stor Byte/Word from AL/A

CONTROL TRANSFER

CALL = Call:

Direct Within Segment

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

1 0 0 1 1 0 1 0

disp-low

mod 0 1 0 r/m

offset-low

disp-high

Indirect Within Segment

Direct Intersegment

offset-high

seg-high

seg-low

Indirect Intersegment

1 1 1 1 1 1 1 1

mod 0 1 1 r/m

Spec Number 518055

888

HS-80C86RH

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

7 6 5 4 3 2 1 0

JMP = Unconditional Jump:

Direct Within Segment

Direct Within Segment-Short

Indirect Within Segment

Direct Intersegment

1 1 1 0 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 1 1 1

1 1 1 0 1 0 1 0

disp-low

disp

disp-high

mod 1 0 0 r/m

offset-low

seg-low

offset-high

seg-high

Direct Intersegment

Indirect Intersegment

1 1 1 1 1 1 1 1

mod 1 0 1 r/m

RET = Return from CALL:

Within Segment

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

1 1 0 0 1 0 1 1

1 1 0 0 1 0 1 0

0 1 1 1 0 1 0 0

0 1 1 1 1 1 0 0

0 1 1 1 1 1 1 0

0 1 1 1 0 0 1 0

0 1 1 1 0 1 1 0

0 1 1 1 1 0 1 0

0 1 1 1 0 0 0 0

0 1 1 1 1 0 0 0

0 1 1 1 0 1 0 1

0 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1

0 1 1 1 0 0 1 1

0 1 1 1 0 1 1 1

0 1 1 1 1 0 1 1

0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 1

1 1 1 0 0 0 1 0

1 1 1 0 0 0 0 1

1 1 1 0 0 0 0 0

1 1 1 0 0 0 1 1

Within Seg Adding lmmed to SP

Intersegment

data-low

data-high

Intersegment Adding Immediate to SP

JE/JZ = Jump on Equal/Zero

data-low

disp

JL/JNGE = Jump on Less/Not Greater or Equal

JLE/JNG = Jump on Less or Equal/ Not Greater

JB/JNAE = Jump on Below/Not Above or Equal

JBE/JNA = Jump on Below or Equal/Not Above

JP/JPE = Jump on Parity/Parity Even

JO = Jump on Overtlow

JS = Jump on Sign

JNE/JNZ = Jump on Not Equal/Not Zero

JNL/JGE = Jump on Not Less/Greater or Equal

JNLE/JG = Jump on Not Less or Equal/Greater

JNB/JAE = Jump on Not Below/Above or Equal

JNBE/JA = Jump on Not Below or Equal/Above

JNP/JPO = Jump on Not Par/Par Odd

JNO = Jump on Not Overﬂow

JNS = Jump on Not Sign

LOOP = Loop CX Times

LOOPZ/LOOPE = Loop While Zero/Equal

LOOPNZ/LOOPNE = Loop While Not Zero/Equal

JCXZ = Jump on CX Zero

INT = Interrupt

Type Specified

1 1 0 0 1 1 0 1

1 1 0 0 1 1 0 0

1 1 0 0 1 1 1 0

1 1 0 0 1 1 1 1

type

Type 3

INTO = Interrupt on Overﬂow

IRET = Interrupt Return

Spec Number 518055

889

HS-80C86RH

Instruction Set Summary (Continued)

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MNEMONIC AND DESCRIPTION

7 6 5 4 3 2 1 0

PROCESSOR CONTROL

CLC = Clear Carry

1 1 1 1 1 0 0 0

1 1 1 1 0 1 0 1

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 0

1 1 1 1 1 1 0 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 1 0 0

1 0 0 1 1 0 1 1

1 1 0 1 1 x x x

1 1 1 1 0 0 0 0

CMC = Complement Carry

STC = Set Carry

CLD = Clear Direction

STD = Set Direction

CLl = Clear Interrupt

ST = Set Interrupt

HLT = Halt

WAIT = Wait

ESC = Escape (to External Device)

LOCK = Bus Lock Prefix

mod x x x r/m

NOTES:

AL = 8-bit accumulator

AX = 16-bit accumulator

if s:w = 01 then 16 bits of immediate data form the operand.

if s:w. = 11 then an immediate data byte is sign extended

to form the 16-bit operand.

CX = Count register

DS= Data segment

if v = 0 then “count” = 1; if v = 1 then “count” in (CL)

x = don't care

ES = Extra segment

z is used for string primitives for comparison with ZF FLAG.

Above/below refers to unsigned value.

Greater = more positive;

Less = less positive (more negative) signed values

if d = 1 then “to” reg; if d = 0 then “from” reg

if w = 1 then word instruction; if w = 0 then byte

instruction

if mod = 11 then r/m is treated as a REG ﬁeld

if mod = 00 then DISP = O†, disp-low and disp-high

are absent

if mod = 01 then DISP = disp-low sign-extended

16-bits, disp-high is absent

if mod = 10 then DISP = disp-high:disp-low

if r/m = 000 then EA = (BX) + (SI) + DISP

if r/m = 001 then EA = (BX) + (DI) + DISP

if r/m = 010 then EA = (BP) + (SI) + DISP

if r/m = 011 then EA = (BP) + (DI) + DISP

if r/m = 100 then EA = (SI) + DISP

if r/m = 101 then EA = (DI) + DISP

if r/m = 110 then EA = (BP) + DISP †

if r/m = 111 then EA = (BX) + DISP

DISP follows 2nd byte of instruction (before data

if required)

SEGMENT OVERRIDE PREFIX

001 reg 11 0

REG is assigned according to the following table:

16-BIT (w = 1)

000 AX

001 CX

010 DX

011 BX

100 SP

101 BP

110 SI

8-BIT (w = 0)

000 AL

SEGMENT

00 ES

01 CS

10 SS

11 DS

00 ES

001 CL

010 DL

011 BL

100 AH

101 CH

110 DH

111 BH

111 DI

Instructions which reference the flag register file as a 16-bit

object use the symbol FLAGS to represent the file:

FLAGS =

†

except if mod = 00 and r/m = 110 then

EA = disp-high: disp-low.

X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)

Mnemonics Intel, 1978

†† MOV CS, REG/MEMORY not allowed.

Spec Number 518055

890

HS-80C86RH

Ceramic Dual-In-Line Metal Seal Packages (SBDIP)

D40.6 MIL-STD-1835 CDIP2-T40 (D-5, CONFIGURATION C)

40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

c1 LEAD FINISH

-A-

-D-

E

INCHES MILLIMETERS

MIN

BASE

METAL

(c)

SYMBOL

MAX

0.225

0.026

0.023

0.065

0.045

0.018

0.015

2.096

0.620

MIN

-

MAX

5.72

NOTES

A

b

-

b1

M

0.014

0.045

0.023

0.008

-

0.36

1.14

0.58

0.20

-

0.66

2

-B-

(b)

b1

b2

b3

c

0.58

3

SECTION A-A

S

D

bbb

C

A - B

1.65

-

D

1.14

4

BASE

PLANE

S2

Q

0.46

2

A

-C-

SEATING

PLANE

c1

D

0.38

3

L

53.24

15.75

4

S1

b2

eA

A A

E

0.510

12.95

4

e

0.100 BSC

2.54 BSC

-

e

eA/2

C A - B

b

C A - B

c

eA

eA/2

L

0.600 BSC

0.300 BSC

15.24 BSC

7.62 BSC

-

ccc

D

aaa

D

S S

M

S

M

-

NOTES:

0.125

0.200

3.18

5.08

-

1. Index area: A notch or a pin one identiﬁcation mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identiﬁcation shall not be used

as a pin one identiﬁcation mark.

Q

0.015

0.005

0.070

0.38

0.13

1.78

5

S1

S2

α

-

6

7

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

o

90

105

90

105

-

aaa

bbb

ccc

M

-

0.015

0.030

0.010

0.0015

-

0.38

0.76

0.25

0.038

-

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

-

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

2

8

N

40

Rev. 0 4/94

5. Dimension Q shall be measured from the seating plane to the

base plane.

6. Measure dimension S1 at all four corners.

7. Measure dimension S2 from the top of the ceramic body to the

nearest metallization or lead.

8. N is the maximum number of terminal positions.

9. Braze fillets shall be concave.

10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

11. Controlling dimension: INCH.

Spec Number 518055

891

HS-80C86RH

Ceramic Metal Seal Flatpack Packages (Flatpack)

K42.A TOP BRAZED

E

N

42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

INCHES MILLIMETERS

MIN

1

A

e

SYMBOL

MAX

0.100

0.025

0.023

0.013

0.010

1.075

0.650

0.680

0.550

MIN

-

MAX

2.54

NOTES

D

A

b

-

0.017

0.007

1.045

0.630

-

0.43

0.18

26.54

16.00

-

0.64

b

b1

c

0.58

-

E1

S1

C

0.33

-

c1

D

0.25

-

L

27.31

16.51

17.27

13.97

3

-

A

Q

E

E2

E1

E2

e

3

-

0.530

13.46

c1

LEAD FINISH

0.050 BSC

1.27 BSC

11

-

k

-

8.13

1.14

0.00

-

8.89

1.65

-

BASE

(c)

L

0.320

0.045

0.000

-

0.350

0.065

-

METAL

Q

S1

M

N

8

6

-

b1

M

0.0015

0.04

(b)

42

-

SECTION A-A

Rev. 0 6/17/94

NOTES:

1. Index area: A notch or a pin one identiﬁcation mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identiﬁcation shall not be used

as a pin one identiﬁcation mark. Alternately, a tab (dimension k)

may be used to identify pin one.

6. Measure dimension S1 at all four corners.

7. For bottom-brazed lead packages, no organic or polymeric mate-

rials shall be molded to the bottom of the package to cover the

leads.

8. Dimension Q shall be measured at the point of exit (beyond the

meniscus) of the lead from the body. Dimension Q minimum

shall be reduced by 0.0015 inch (0.038mm) maximum when sol-

der dip lead ﬁnish is applied.

2. If a pin one identiﬁcation mark is used in addition to a tab, the lim-

its of dimension k do not apply.

3. This dimension allows for off-center lid, meniscus, and glass

overrun.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

4. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and ﬁnish thickness. The maximum lim-

its of lead dimensions b and c or M shall be measured at the cen-

troid of the ﬁnished lead surfaces, when solder dip or tin plate

lead ﬁnish is applied.

11. The basic lead spacing is 0.050 inch (1.27mm) between center

lines. Each lead centerline shall be located within ±0.005 inch

(0.13mm) of its exact longitudinal position relative to lead 1 and

the highest numbered (N) lead.

5. N is the maximum number of terminal positions.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

EUROPE

ASIA

Intersil Corporation

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

Intersil (Taiwan) Ltd.

Taiwan Limited

7F-6, No. 101 Fu Hsing North Road

Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (407) 724-7000

FAX: (407) 724-7240

Spec Number 518055

892


型号：	HS9-80C86RH
厂家：	Intersil
描述：	Radiation Hardened 16-Bit CMOS Microprocessor 抗辐射16位CMOS微处理器微处理器
文件：	总37页 (文件大小：241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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