HSP45106JC-25 [INTERSIL]
16-Bit Numerically Controlled Oscillator; 16位数控振荡器
| 型号： | HSP45106JC-25 |
| 厂家： | 
Intersil |
| 描述： | 16-Bit Numerically Controlled Oscillator |
| 文件： | 总14页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HSP45106
Data Sheet
October 1999
File Number 2809.5
16-Bit Numerically Controlled Oscillator
Features
The Intersil HSP45106 is a high performance 16-bit
quadrature Numerically Controlled Oscillator (NCO16). The
NCO16 simplifies applications requiring frequency and
phase agility such as frequency-hopped modems, PSK
modems, spread spectrum communications, and precision
signal generators. As shown in the block diagram, the
HSP45106 is divided into a Phase/Frequency Control
Section (PFCS) and a Sine/Cosine Section.
• 25.6MHz, 33MHz Versions
• 32-Bit Center and Offset Frequency Control
• 16-Bit Phase Control
• 8 Level PSK Supported Through Three Pin Interface
• Simultaneous 16-Bit Sine and Cosine Outputs
• Output in Two’s Complement or Offset Binary
• <0.008Hz Tuning Resolution at 33MHz
• Serial or Parallel Outputs
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The frequency resolution is 32 bits, which provides for
resolution of better than 0.008Hz at 33MHz. User
• Spurious Frequency Components <-90dBc
• 16-Bit Microprocessor Compatible Control Interface
programmable center frequency and offset frequency
registers give the user the capability to perform phase
coherent switching between two sinusoids of different
frequencies. Further, a programmable phase control register
Applications
o
• Direct Digital Synthesis
allows for phase control of better than 0.006 . In applications
requiring up to 8-level PSK, three discrete inputs are
provided to simplify implementation.
• Quadrature Signal Generation
• Spread Spectrum Communications
• PSK Modems
The output of the PFCS is a 28-bit phase which is input to
the Sine/Cosine Section for conversion into sinusoidal
amplitude. The outputs of the Sine/Cosine Section are two
16-bit quadrature signals. The spurious free dynamic range
of this complex vector is greater than 90dBc.
• Modulation - FM, FSK, PSK (BPSK, QPSK, 8PSK)
• Frequency Hopping Communications
• Precision Signal Generation
For added flexibility when using the NCO16 in conjunction
with DAC’s, a choice of either parallel or serial outputs with
either two’s complement or offset binary encoding is
provided. In addition, a synchronization signal is available
which indicates serial word boundaries.
• Related Products
- Use with Data Acquisition Parts HI5731 or HI5741
Ordering Information
TEMP.
o
PART NUMBER RANGE ( C)
PACKAGE
84 Ld PLCC
84 Ld PLCC
84 Ld PLCC
85 Ld CPGA
PKG. NO.
N84.1.15
N84.1.15
N84.1.15
G85.A
HSP45106JC-25
HSP45106JI-25
HSP45106JC-33
HSP45106GC-33
0 to 70
-40 to 85
0 to 70
0 to 70
Block Diagram
SIN/COS
ARGUMENT
MICROPROCESSOR
16
16
INTERFACE
SINE
PHASE/
FREQUENCY
CONTROL
32
SINE/
COSINE
SECTION
CLOCK
COSINE
SECTION
DISCRETE
CONTROL SIGNALS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HSP45106
Pinouts
85 PIN CPGA
TOP VIEW
11
10
9
8
7
6
5
4
3
2
1
DAC
STRB
L
GND SIN0
SIN1
SIN3
SIN5
SIN4
SIN9 SIN12 SIN13 SIN14
L
K
BINFMT
INITPAC
V
CLK
SIN2
V
SIN8
SIN7
SIN10 GND SIN15
SIN11
OES
OEC
COS0
COS1
K
J
CC
CC
PAR/
SER
SIN6
J
EN
COS2 COS3
H
G
PACI
H
G
PHAC
ENTI
REG
INITT INHOF
ENPO ENOF
COS6 COS4 COS5
ENCF
REG
COS7 COS8
V
CC
F
E
F
E
REG
REG
CS
GND
WR
COS11 COS10 COS9
GND COS12
D
V
TEST
D
CC
INDEX
MOD2 MOD0
C10
C12
C9
C6
COS15 COS13
PIN
C
B
A
C
B
A
MOD1
A2
A1
C15
C13
V
C4
C1
TICO COS14
CC
PMSEL
11
A0
10
GND
9
C0
8
C0
7
C0
6
C0
5
C0
4
C0
3
C2
2
C0
1
PIN ‘A1’
ID
85 PIN CPGA
BOTTOM VIEW
1
2
3
4
5
6
7
8
9
10
SIN0
11
DAC
STRB
L
K
J
SIN14
OES
SIN13 SIN12
SIN9
SIN4
SIN5
SIN3 SIN1
SIN2 CLK
GND
L
COS0
COS1
SIN15 GND SIN10
SIN11
SIN8
SIN7
V
V
BINFMT
INITPAC
K
CC
CC
PAR/
SER
OEC
SIN6
J
EN
PHAC
H
G
COS3 COS2
PACI
H
G
ENTI
REG
COS5 COS4 COS6
INHOF INITT
ENOF ENPO ENCF
V
COS8 COS7
CC
F
E
F
E
REG
REG
REG
COS9 COS10 COS11
COS12 GND
WR
GND
CS
D
TEST
V
D
CC
INDEX
COS13 COS15
PIN
C
B
A
C6
C9
C10
C12
MOD0 MOD2
C
B
A
COS14 TICO
C1
C4
V
C13
C15
A1
A2
MOD1
CC
C0
1
C2
2
C0
3
C0
4
C0
5
C0
6
C0
7
C0
8
GND
9
A0
10
PMSEL
11
PIN ‘A1’
ID
2
HSP45106
Pinouts (Continued)
84 LEAD PLCC
TOP VIEW
11 10 9
8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
PMSEL
MOD0
MOD1
MOD2
TEST
TICO
COS15
COS14
COS13
GND
COS12
COS11
COS10
COS9
COS8
COS7
COS6
COS5
COS4
V
CC
WR
GND
CS
ENCFREG
ENOFREG
INHOFR
ENTIREG
INITTAC
ENPOREG
INPHAC
PACI
V
CC
COS3
COS2
COS1
COS0
OEC
INITPAC
BINFMT
PAR/SER
V
DACSTRB
CC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Pin Descriptions
NAME
TYPE
DESCRIPTION
V
+5 power supply pin.
Ground.
CC
GND
C(15:0)
A(2:0)
CS
I
I
I
I
Control input bus for loading phase, frequency, and timer data into the PFCS. C0 is LSB.
Address pins for selecting destination of C(15:0) data (Table 2). A0 is the LSB
Chip select (active low). Enables data to be written into Control Registers by WR.
WR
Write enable (active low). Data is clocked into the register selected by A(2:0) on the rising edge of WR when CS
is low.
CLK
I
I
Clock. All registers, except the Control Registers clocked with WR, are clocked (when enabled) by the rising edge
of CLK.
ENPOREG
Phase Offset Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip,
ENPOREG enables the clocking of data into the Phase Offset Register. Allows ROM address to be updated
regardless of ENPHAC.
ENOFREG
ENCFREG
ENPHAC
ENTIREG
INHOFR
I
I
I
I
I
Offset Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENOFREG enables the clocking of data into the Offset Frequency Register.
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENCFREG enables the clocking of data into the Center Frequency Register.
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENPHAC enables the clocking of data into the Phase Accumulator Register.
Timer Increment Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENTIREG enables the clocking of data into the Timer Increment Register.
Inhibit Offset Frequency Register Output (active low). Registered on chip by CLK. When active, after being clocked
onto chip, INHOFR zeroes the data path from the Offset Frequency Register to the Frequency Adder. New data
can be still clocked into the Offset Frequency Register. INHOFR does not affect the contents of the register.
INITPAC
I
I
Initialize Phase Accumulator (active low). Registered on chip by CLK. Zeroes the feedback path in the Phase
Accumulator. Does not clear the Phase Accumulator Register.
MOD(2:0)
Modulation Control Inputs. When selected with the PMSEL line, these bits add an offset of 0, 45, 90, 135, 180,
225, 270, or 315 degrees to the current phase (i.e., modulate the output). The lower 13 bits of the phase control
are set to zero. These bits are registered when the Phase Offset Register is enabled.
3
HSP45106
Pin Descriptions (Continued)
NAME
TYPE
DESCRIPTION
PMSEL
I
Phase Modulation Select input. Registered on chip by CLK. This input determines the source of the data clocked
into the Phase Offset Register. When high, the Phase Input Register is selected. When low, the external
modulation pins (MOD(2:1)) control the three most significant bits of the Phase Offset Register and the 13 least
significant bits are set to zero.
PACI
I
I
Phase Accumulator Carry Input (active low). Registered on chip by CLK.
INITTAC
Initialize Timer Accumulator (active low). This input is registered on chip by CLK. When active, after being clocked
onto chip, INITTAC enables the clocking of data into the Timer increment Register, and also zeroes the feedback
path in the Timer Accumulator.
TEST
I
I
Test Select Input. Registered on chip by CLK. This input is active high. When active, this input enables test busses
to the outputs instead of the sine and cosine data.
PAR/SER
Parallel/Serial Output Select. This input is registered on chip by CLK. When low, the sine and cosine outputs are
in serial mode. The Output Shift Registers will load in new data after ENPHAC goes low and will start shifting the
data out after ENPHAC goes high. When this input is high, the Output Registers are loaded every clock and no
shifting takes place.
BINFMT
I
Format. This input is registered on chip by CLK. When low, the MSB of the SIN and COS are inverted to form an
offset binary (unsigned) number.
OES
OEC
TICO
I
I
Three-state control for bits SIN(15:0). Outputs are enabled when OES is low.
Three-state control for bits COS(15:0). Outputs are enabled when OEC is low.
O
Timer Accumulator Carry Output. Active low, registered. This output goes low when a carry is generated by the
Timer Accumulator.
DACSTRB
SIN(15:0)
O
O
DAC Strobe (active low). In serial mode, this output will go low when the first bit of a new output word is valid at
the shift register output. This pin is active only in serial mode.
Sine Output Data. When parallel mode is enabled, data is output on SIN(15:0). When serial mode is enabled,
output data bits are shifted out of SIN15 and SIN0. The bit stream on SIN15 is provided MSB first while the bit
stream on SIN0 is provided LSB first.
COS(15:0)
Index Pin
O
Cosine Output Data. When parallel mode is enabled, data is output on COS(15:0). When serial mode is enabled,
output data bits are shifted out of COS15 and COS0. The bit stream on COS15 is provided MSB first while the bit
stream in COS0 is provided LSB first.
Used to align chip in socket or on circuit board. Must be left as a no connect in circuit. (CPGA Package only).
Functional Description
Phase/Frequency Control Section
The 16-bit Numerically Controlled Oscillator (NCO16)
produces a digital complex sinusoid waveform whose
frequency and phase are controlled through a standard
microprocessor interface and discrete inputs. The NCO16
generates 16-bit sine and cosine vectors at a maximum
sample rate of 33MHz. The NCO16 can be preprogrammed
to produce a constant (CW) sine and cosine output for Direct
Digital Synthesis (DDS) applications. Alternatively, the
phase and frequency inputs can be updated in real time to
produce a FM, PSK, FSK, or MSK modulated waveform. To
simplify PSK generation, a 3 pin interface is provided to
support modulation of up to 8 levels.
The phase and frequency of the quadrature outputs are
controlled by the PFCS (Figure 1). The PFCS generates a
32-bit word which represents the instantaneous phase
(Sin/Cos argument) of the sine and cosine waves being
generated. This phase is incremented on the rising edge of
each CLK by the preprogrammed amounts in the phase and
Frequency Control Registers. As the instantaneous phase
32
steps from 0 through full scale (2 - 1), the phase of the
o
quadrature outputs proceeds from 0 around the unit circle
counter clockwise.
The PFCS is comprised of a Phase Accumulator Section,
Phase Offset adder, Input Section, and a Timer Accumulator
Section. The Phase Accumulator computes the
As shown in Figure 1, the HSP45106 Block Diagram, the
NCO16 is comprised of a Phase and Frequency Control
Section (PFCS) and Sine/ Cosine Section. The PFCS stores
the phase and frequency control inputs and uses them to
calculate the phase angle of a rotating complex vector. The
Sine/Cosine Section performs a lookup on this phase and
generates the appropriate amplitude values for the sine and
cosine. These quadrature outputs may be configured as
serial or parallel with either two's complement or offset
binary format.
instantaneous phase angle from user programmed values in
the Center and Offset Frequency Registers. This angle is
then fed into the Phase Offset adder where it is offset by the
preprogrammed value in the Phase Offset Register. The Input
Section routes data from a microprocessor compatible control
bus and discrete input signals into the appropriate configuration
registers. The Timer Accumulator supplies a pulse to mark the
passage of a user programmed period of time.
4
HSP45106
M U X
0
1
M U X
0
1
M U X
0
1
M U X
0
1
5
HSP45106
The number of steps required for this transition depends on
Input Section
the phase increment calculated by the frequency adder. For
example, if the Center and Offset Frequency Registers are
programmed such that the output of the Frequency Adder is
4000 0000 hex, the Phase Accumulator will step the phase
from 0 to 360 degrees every 4 clock cycles. Thus, for a
30MHz CLK, the quadrature outputs will have a frequency of
30/4MHz or 7.5MHz. In general, the frequency of the
quadrature output is determined by:
The Input Section loads the data on C(15:0) into one of the
seven input registers, the LSB and MSB Center Frequency
Input Registers, the LSB and MSB Offset Frequency
Registers, the LSB and MSB Timer Input Registers, and the
Phase Input Register. The destination depends on the state of
A(2:0) when CS and WR are low (Table 1).
TABLE 1. ADDRESS DECODE MAPPING
MOD(2:0) DECODING
32
(EQ. 1)
F
= (N × f
⁄ 2 ), or
LO
CLK
A2
A1
A0
CS
WR
FUNCTION
0
0
0
0
Load least significant bits of
Center Frequency input.
↑
f
32
OUT
(EQ. 2)
-------------
N = INT
2
,
f
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
Load most significant bits of
Center Frequency input.
↑
↑
↑
↑
↑
CLK
Load least significant bits of
Offset Frequency input.
where N is the 32 bits of frequency control word that is
programmed. INT[•] is the integer of the computation. For
example, if the control word is 20000000 hexadecimal and the
clock frequency is 30MHz, then the output frequency would
Load most significant bits of
Offset Frequency input.
Load least significant bits of
Timing Interval input.
be f
/8, or 3.75MHz.
CLK
Load most significant bits of
Timing Interval input.
The Frequency Adder sums the contents of both the Center
and Offset Frequency Registers to produce a phase
increment. By enabling INHOFR, the output of the Offset
Frequency Register is disabled so that the output frequency is
determined from the Center Frequency Register alone. For
BFSK modems, INHOFR can be asserted/ de-asserted to
toggle the quadrature outputs between two programmed
frequencies. NOTE: Enabling/disabling INHOFR preserves
the contents of the Offset Frequency Register.
1
1
1
1
0
1
0
0
1
Load Phase Register
Reserved
↑
↑
X
X
X
X
Input Disabled
Once the Input Registers have been loaded, the control inputs
ENCFREG, ENOFREG, ENTIREG, ENCTIREG, and
ENPOREG will allow the Input Registers to be downloaded to
the PFCS Control Registers with the input CLK. The control
inputs are latched on the rising edge of CLK and the Control
Registers are updated on the rising edge of the following CLK.
For example, to load the Center Frequency Register, the data
is loaded into the LSB and MSB Center Frequency Input
Register, and ENCFREG is set to zero; the next rising edge of
CLK will pass the registered version of ENCFREG,
R.ENCFREG, to the clock enable of the Center Frequency
Register; this register then gets loaded on the following rising
edge of CLK. The contents of the Input Registers are
downloaded to the Control Registers every clock, if the control
inputs are enabled.
The Block Diagram shown in Figure 2 illustrates the method of
reading the phase accumulator of the NCO16 from a
microprocessor. The setup shown is very similar to that used
when the part is used for generating a complex sinusoid,
except that the internal SIN/COS lookup is bypassed by
setting the TEST pin to a logic 1(high). While the TEST pin is
high, the phase accumulator continues to drive the inputs of
the SIN/COS Generator while the most significant 28 bits of
the phase accumulator are multiplexed out onto the output
pins. Because of this, the part can be operated in two modes,
one where the SIN/COS Generator is permanently bypassed,
and one where the phase accumulator output is brought out to
the outputs as a check.
Phase Accumulator Section
The Phase Accumulator adds the 32-bit output of the
Frequency Adder with the contents of a 32-bit Phase
Accumulator Register on every clock cycle. When the sum
causes the adder to overflow, the accumulation continues with
the least significant 32 bits of the result.
Figure 2 illustrates a circuit for reading out the phase
accumulator all the time. In this case, a microprocessor loads
the frequency and phase registers of the NCO16. This is fairly
straightforward, except for the Start Logic Block, which needs
to be synchronous to the oscillator clock and the
Initializing the Phase Accumulator Register is done by putting
a low on the INITPAC and ENPHAC lines. This zeroes the
feedback path to the accumulator, so that the register is
loaded with the current value of the Frequency Adder on the
next clock.
microprocessor interface. This has been left as an undefined
function, since it is dependent on the implementation. Also
note that all COS outputs (COS(15:0)) are connected,
although only COS(15:4) are valid in this application. The
microprocessor reads the sine and cosine data busses as if
they were RAMs, using the decoded address bus to select
one or the other.
The frequency of the quadrature outputs is based on the
number of clock cycles required to step from 0 to full scale.
6
HSP45106
The timing for loading the Center Frequency Register (MSB
WRITE
WRITE
LS INPUT
REGISTER
MS INPUT
REGISTER
and LSB) and data being output on COS(15:0) and SIN(15:0)
is shown in Figure 3. This timing is independent of whether
the output data represents the phase accumulator data or the
SIN/COS Generator output.
WR
CS
When it is desired for the output of the NCO16 to be switched
back and forth between sine/cosine and the phase
A0-2
accumulator, a circuit such as the one shown in Figure 4 could
be used. In this case, the sinusoidal output cannot be
interrupted, so the phase accumulator must be read out
between samples. This is possible due to the fact that the
TEST signal is simply the control line for a multiplexer on the
output of the SIN/COS Generator, but carries with it a
limitation on the maximum possible clock rate. Since TEST is
a synchronous input, the output of the NCO16 must be either
driven by the SIN/COS Generator or the phase accumulator
for an entire clock cycle. Therefore, the part must be driven at
twice the desired speed at all times so there is a clock cycle
available for TEST, when necessary. Note that the processor
must be driven from the same clock that generates the NCO
clock in order to maintain synchronous operation.
C0-15
TRANSFER DATA
TO CENTER OR OFFSET
FREQUENCY REGISTER
ENCFREG,
ENOFREG
NEW
FREQUENCY
DATA
COS0-15,
SIN0-15
CLK
FIGURE 3. NCO16 PIPELINE DELAY
HSP45106
MICROPROCESSOR
MICROPROCESSOR
HSP45106
MOD0(2:0) (15:0)
PMSEL
GND
DAC
DAC
SIN0-15
V
GND
V
MOD0-2
CC
DATA
WE
ADDRESS
C(15:0)
WR
SIN0-15
COS0-15
PMSEL
C0-15
WR
A0-2
CS
ENPOREG
ENCFREG
OES
CC
COS(15:0)
DATA
WE
ADDRESS
A(2:0)
CS
ENPOREG
ENCFREG
OES
>
REGISTER
OEC
ENOFREG
V
CC
DECODE
OEC
ENPHAC
ENTIGEG
INHOFR
INITPAC
PACI
INITTAC
TEST
PAR/SER
BINFMT
CLK
GND
V
V
ENOFREG
ENPHAC
ENTIGEG
INHOFR
INITPAC
PACI
INITTAC
TEST
PAR/SER
BINFMT
CLK
CC
CC
GND
DECODE
GND
V
CC
GND
V
CC
START
LOGIC
V
CC
V
V
CC
CC
V
V
CC
CC
START
LOGIC
V
CC
V
V
CC
CC
OSCILLATOR
÷2
FIGURE 2. CIRCUIT FOR READING PHASE ACCUMULATOR
OF NCO16
OSCILLATOR
FIGURE 4. CIRCUIT FOR READING PHASE ACCUMULATOR
OF NCO16 WHILE GENERATING SINUSOID
7
HSP45106
values are computed to reduce the amount of ROM needed.
Phase Offset Adder
The magnitude of the error in the computed value of the
complex vector is less than -90.2dB. The error in the sine or
cosine alone is approximately 2dB better. The 20-bit phase
word maps into 2p radians so that the angular resolution is
The output of the Phase Accumulator goes to the Phase
Offset Adder, which adds the 16-bit contents of the Phase
Offset Register to the 16 MSBs of the phase. Twenty-eight
(28) bits of the resulting 32-bit number forms the
20
(2p)/2 . An address of zero corresponds to 0 radians and
instantaneous phase which is fed to the Sine/Cosine Section.
20
an address of hex FFFFF corresponds to 2π-((2π)/2
)
The user has the option of loading the Phase Offset Registers
with the contents of the Phase Input Register or with the
MOD(2:0) inputs depending on the state of PMSEL. When
PMSEL is high, the contents of the Phase Input Register are
loaded. If PMSEL is low, MOD(2:0) encode the upper 3 bits of
the Phase Offset Register while the lower 13 bits are cleared.
The MOD(2:0) inputs simplify PSK modulation by providing a
3 input interface to phase modulate the carrier as shown in
Table 2. The control input ENPOREG acts as a clock enable
and must be low to enable clocking of data into the Phase
Offset Register.
radians. The outputs of the Sine/Cosine Section are two's
complement sine and cosine values. The ROM contents have
been scaled by (2 -1)/(2 +1) for symmetry about zero.
16
16
To simplify interfacing with D/A converters, the format of the
Sine/cosine outputs may be changed to offset binary by
enabling BINFMT. When BINFMT is enabled, the MSB of the
Sine and Cosine outputs (SIN15 and COS15 when the
outputs are in parallel mode) are inverted. Depending upon
the state of BINFMT, the output is centered around midscale
and ranges from 8001H to 7FFFH (two's complement mode)
or 0001H to FFFFH (offset binary mode).
TABLE 2. MODULATION CONTROL MAP
MOD(2:0) DECODING
Serial output mode is chosen by enabling PAR/SER. In this
mode the user loads the Output Shift Registers with
Sine/Cosine ROM output by enabling ENPHAC. After
ENPHAC goes inactive the data is shifted out serially. For
example, to clock out one 16-bit Sine/Cosine output,
ENPHAC would be active for one cycle to load the output
Shift Register, and would then go inactive for the following 15
cycles to clock the remaining bits out. Output bit streams are
provided in formats with either MSB first or LSB first. The
MSB first format is available on the SIN15 and COS15
output pins. The LSB first format is available on the SIN0
and COS0 output pins. In MSB first format, zero’s follow the
LSB if a new output word is not loaded into the Shift
Register. In LSB first format, the sine extension bit follows
the MSB if a new data word is not loaded. The output signal
DACSTRB is provided to signal the first bit of a new output
word is valid (Figure 6). NOTE: All unused pins of
SIN(15:0) and COS(15:0) should be left floating.
PHASE SHIFT
MOD2
MOD1
MOD0
(DEGREES)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
45
90
135
270
315
180
225
Timer Accumulator Section
The Timer Accumulator consists of a register which is
incremented on every clock. The amount by which it
increments is loaded into the Timer Increment Input
Registers and is latched into the Timer Increment Register
on rising edges of CLK while ENTIREG is low. The output of
the Timer Accumulator is the accumulator carry out, TICO.
TICO can be used as a timer to enable the periodic sampling
of the output of the NCO-16. The number programmed into
this register equals:
A test mode is supplied which enables the user to access
the phase input to the Sine/Cosine ROM. If TEST and
PAR/SER are both high, the 28 MSBs of the phase input to
the Sine/Cosine Section are made available on SIN(15:0)
and COS(15:4). The SIN(15:0) outputs represent the MSW
of the address.
f
32
OUT
-------------
N = INT
2
,
(EQ. 3)
f
CLK
The Timing Diagrams in Figure 7, 8 and 9 show the pipeline
delays through the HSP45106 NCO16 from the time that
data is applied to the inputs until the outputs are affected by
the change. The delay is shown as a number of clock cycles,
with no attempt made to accurately represent the setup and
hold times or the clock to output delays.
where INT[x] is the integer portion of the result of the
computation.
Sine/Cosine Section
The Sine/Cosine Section (Figure 5) converts the
instantaneous phase from the PFCS Section into the
appropriate amplitude values for the sine and cosine
outputs. It takes the most significant 20 bits of the PFCS
output and passes them through a Sine/Cosine look up to
form the 16-bit quadrature outputs. The sine and cosine
8
HSP45106
16 COSINE
/
DACSTRB
20
ADDRESS
DECODE
SINE/COSINE
ROM
FORMAT
CONTROL
SIN/COS
ARGUMENT
/
16 SINE
/
SIN (15:0)
16
16
/
/
OUTPUT
CONTROL
28
/
COS (15:0)
BINFMT
R.ENPHAC, TEST, PAR/SER
OES
OEC
FIGURE 5. SINE/COSINE SECTION BLOCK DIAGRAM
0
1
2
3
4
5
6
10
7
9
CLK
8
t
ECS
ENPHAC
t
DSO
DACSTRB
SERIAL DATA OUTPUT
BIT
0
1
2
3
FIGURE 6. SERIAL OUTPUT I/O TIMING DIAGRAM
CLK
CS
WRITE
MS INPUT
REGISTER
WRITE
LS INPUT
REGISTER
WR
A(2:0)
C(15:0)
TRANSFER DATA
TO CENTER OR OFFSET
FREQUENCY REGISTER
ENCFREG
ENOFREG
NEW
FREQUENCY
DATA
COS(15:0),
SIN(15:0)
FIGURE 7. FREQUENCY TO OUTPUT DELAY
9
HSP45106
CLK
WR
WRITE
PHASE INPUT
REGISTER
A(2:0)
C(15:0)
TRANSFER DATA TO
PHASE REGISTER
ENPOREG
NEW
PHASE
DATA
COS(15:0),
SIN(15:0)
FIGURE 8. PHASE TO OUTPUT DELAY
CLK
MOD0-2
PMSEL
TRANSFER DATA TO
PHASE REGISTER
ENPOREG
NEW
PHASE
DATA
COS(15:0),
SIN(15:0)
FIGURE 9. PHASE MODULATION TO OUTPUT DELAY
10
HSP45106
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
o
o
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage Applied . . . . .GND -0.5V to V +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
CC
PLCC Package. . . . . . . . . . . . . . . . . . .
CPGA Package . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
36
36
N/A
7
o
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C
CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300 C
Operating Conditions
o
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.75V to +5.25V
o
o
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
o
(PLCC - Lead Tips Only)
Die Characteristics
Backside Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
High Level Clock Input
SYMBOL
TEST CONDITIONS
MIN
2.0
-
MAX
-
UNITS
V
V
V
V
V
V
= 5.25V
= 4.75V
= 5.25V
= 4.75V
IH
CC
CC
CC
CC
V
0.8
-
V
IL
V
3.0
-
V
IHC
Low Level Clock Input
V
0.8
-
V
ILC
Output HIGH Voltage
V
I
I
= -400µA, V
= 4.75V
= 4.75V
CC
2.6
-
V
OH
OH
CC
Output LOW Voltage
V
= +2.0mA, V
0.4
10
10
500
180
V
OL
OL
Input Leakage Current
I
V
= V
or GND, V
= 5.25V
-10
-10
-
µA
µA
µA
mA
I
IN
CC
CC
I/O Leakage Current
I
V
= V
or GND, V
= 5.25V
CC
O
OUT
CC
or GND, V
Standby Power Supply Current
Operating Power Supply Current
I
V
= V
= 5.25V, Note 4
CCSB
IN
CC
CC
I
f = 25.6MHz, V = V
or GND
-
CCOP
IN
CC
V
= 5.25V, Notes 2 and 4
CC
o
Capacitance T = 25 C, Note 3
A
PARAMETER
Input Capacitance
SYMBOL
TEST CONDITIONS
FREQ = 1MHz, V = Open. All
measurements are referenced to device
ground
MIN
MAX
10
UNITS
pF
C
-
-
IN
CC
Output Capacitance
C
10
pF
O
NOTES:
2. Power supply current is proportional to operating frequency. Typical rating for I
is 7mA/MHz.
CCOP
3. Not tested, but characterized at initial design and at major process/design changes.
4. Output load per test load circuit with switch open and C = 40pF.
L
11
HSP45106
o
o
AC Electrical Specifications
V
= 5.0V 5%, T = 0 C to 70 C (Note 5)
CC A
25.6MHz
33MHz
PARAMETER
SYMBOL
NOTES
MIN
MAX
MIN
MAX
UNITS
ns
CLK Period
CLK High
CLK Low
WR Period
WR High
WR Low
t
39
15
15
39
15
15
13
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
12
12
30
12
12
13
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CP
t
ns
CH
t
ns
CL
t
ns
WP
WH
t
ns
t
ns
WL
Setup Time A(2:0), CS to WR Going High
Hold Time A(2:0), CS from WR Going High
Setup Time C(15:0) to WR Going High
Hold Time C(15:0) from WR Going High
Setup Time WR High to CLK High
t
ns
AWS
AWH
CWS
CWH
t
ns
t
15
0
15
0
ns
t
ns
t
Note 6
16
15
0
12
15
0
ns,
ns
WC
Setup Time MOD(2:0) to CLK Going High
Hold Time MOD(2:0) from CLK Going High
t
MCS
MCH
t
ns
Setup Time ENPOREG, ENOFREG, ENCFREG,
ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC,
BINFMT, TEST, PAR/SER, PACI, INITTAC
to CLK Going High
t
12
12
ns
ECS
Hold Time ENPOREG, ENOFREG, ENCFREG,
ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC,
BINFMT, TEST, PAR/SER, PACI, INITTAC
from CLK Going High
t
0
-
0
-
ns
ECH
CLK to Output Delay SIN(15:0), COS(15:0), TICO
CLK to Output Delay DACSTRB
Output Enable Time
t
-
2
-
18
18
12
15
8
-
2
-
15
15
12
15
8
ns
ns
ns
ns
ns
DO
t
DSO
t
OE
Output Disable Time
t
Note 7
Note 7
-
-
OD
Output Rise, Fall Time
t
-
-
RF
NOTES:
5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 0V and 3.0V; timing reference levels (CLK)
2.0V; all others 1.5V. Output load per test load circuit with switch closed and C = 40pF. Output transition is measured at V
> 1.5V and V
OL
L
OH
< 1.5V.
6. If ENOFREG, ENCFREG, ENTIREG, or ENPOREG are active, care must be taken to not violate setup and hold times to these registers when
writing data into the chip via the C(15:0) port.
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.
12
HSP45106
AC Test Load Circuit
S
1
DUT
C
(NOTE)
L
I
1.5V
I
OL
OH
SWITCH S1 OPEN FOR I
AND I
CCOP
CCSB
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
Waveforms
t
CP
t
t
CL
CH
CLK
t
t
t
MCS
MCH
MOD(2:1)
t
ECS
ECH
ENABLE/CONTROL
SIGNALS
t
DO
SIN(15:0), COS(15:0), TICO
t
DSO
DACSTRB
(SERIAL MODE ONLY)
t
WC
FIGURE 10. SYNCHRONOUS TIMING
t
WC
t
WP
t
WL
t
WH
WR
t
AWS
t
AWH
A(2:0), CS
t
CWS
t
CWH
C(15:0)
FIGURE 11. ASYNCHRONOUS TIMING
13
HSP45106
Waveforms (Continued)
1.5V
1.5V
OES, OEC
t
t
OD
OE
COS(15:0),
SIN(15:0)
1.7V
1.3V
HIGH
HIGH
IMPEDANCE
IMPEDANCE
FIGURE 12. OUTPUT ENABLE, DISABLE TIMING
2.0V
0.8V
2.0V
0.8V
t
t
RF
RF
FIGURE 13. OUTPUT RISE AND FALL TIMES
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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14
相关型号：
HSP45106JC-33Z
16-Bit Numerically Controlled Oscillator; PLCC84; Temp Range: 0° to 70°
RENESAS
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