ICL3241EIB-T [INTERSIL]
+,-15kV ESD Protected, +3V to +5.5V, 1Microamp, 250kbps, RS-232 Transmitters/Receivers; + , - 15kV ESD保护, + 3V至+ 5.5V , 1Microamp , 250kbps的, RS - 232发射器/接收器型号: | ICL3241EIB-T |
厂家: | Intersil |
描述: | +,-15kV ESD Protected, +3V to +5.5V, 1Microamp, 250kbps, RS-232 Transmitters/Receivers |
文件: | 总27页 (文件大小:833K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ICL3221E, ICL3222E, ICL3223E,
ICL3232E, ICL3241E, ICL3243E
®
Data Sheet
March 8, 2005
FN4910.18
±15kV ESD Protected, +3V to +5.5V,
1Microamp, 250kbps, RS-232
Transmitters/Receivers
Features
• Pb-free Available (RoHS Compliant) (See Ordering Info)
• ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000)
The Intersil ICL32XXE devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
• Drop in Replacements for MAX3221E, MAX3222E,
MAX3223E, MAX3232E, MAX3241E, MAX3243E,
SP3243E
• ICL3221E is a Low Power, Pin Compatible Upgrade for 5V
MAX221E
• ICL3222E is a Low Power, Pin Compatible Upgrade for 5V
MAX242E, and SP312E
• ICL3232E is a Low Power Upgrade for HIN232E, ICL232
and Pin Compatible Competitor Devices
• RS-232 Compatible with V
CC
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Manual and Automatic Powerdown Features
V.28/V.24 specifications, even at V
= 3.0V. Additionally,
CC
they provide ±15kV ESD protection (IEC61000-4-2 Air Gap
and Human Body Model) on transmitter outputs and receiver
inputs (RS-232 pins). Targeted applications are PDAs,
Palmtops, and notebook and laptop computers where the
low operational, and even lower standby, power
consumption is critical. Efficient on-chip charge pumps,
coupled with manual and automatic powerdown functions
(except for the ICL3232E), reduce the standby supply
current to a 1µA trickle. Small footprint packaging, and the
use of small, low value capacitors ensure board space
savings as well. Data rates greater than 250kbps are
guaranteed at worst case load conditions. This family is fully
compatible with 3.3V-only systems, mixed 3.3V and 5.0V
systems, and 5.0V-only systems.
= 2.7V
• Guaranteed Mouse Driveability (ICL324XE Only)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
The ICL324XE are 3-driver, 5-receiver devices that provide a
complete serial port suitable for laptop or notebook
computers. Both devices also include noninverting always-
active receivers for “wake-up” capability.
The ICL3221E, ICL3223E and ICL3243E, feature an
automatic powerdown function which powers down the on-
chip power-supply and driver circuits. This occurs when an
attached peripheral device is shut off or the RS-232 cable is
removed, conserving system power automatically without
changes to the hardware or operating system. These
devices power up again when a valid RS-232 voltage is
applied to any receiver input.
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
Table 1 summarizes the features of the devices represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32XXE 3V family.
- Cellular/Mobile Phones
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
TABLE 1. SUMMARY OF FEATURES
NO. OF
MONITOR Rx.
DATA
MANUAL
POWER-
DOWN?
AUTOMATIC
POWERDOWN
FUNCTION?
NO. OF NO.OF
RATE
Rx. ENABLE
FUNCTION?
READY
PART NUMBER
ICL3221E
ICL3222E
ICL3223E
ICL3232E
ICL3241E
ICL3243E
Tx.
1
Rx.
1
(R
)
(kbps)
250
OUTPUT?
OUTB
0
Yes
Yes
Yes
No
No
No
No
No
No
No
Yes
Yes
Yes
No
Yes
No
2
2
0
0
0
2
1
250
2
2
250
Yes
No
2
2
250
3
5
250
Yes
No
Yes
Yes
No
3
5
250
Yes
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000-2005. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Ordering Information
Ordering Information (Continued)
(NOTE 1)
TEMP.
(°C)
PKG.
(NOTE 1)
TEMP.
(°C)
PKG.
PART NO.
PACKAGE
DWG. #
PART NO.
PACKAGE
DWG. #
ICL3221ECA
ICL3221ECAZ (Note 2) 0 to 70 16 Ld SSOP (Pb-free)
0 to 70 16 Ld SSOP
M16.209
M16.209
M16.209
ICL3232ECV-20Z
(Note 2)
0 to 70 20 Ld TSSOP (Pb-free) M20.173
ICL3232EIA
-40 to 85 16 Ld SSOP
M16.209
M16.209
M16.3
ICL3221ECAZA
(Note 2)
0 to 70 16 Ld SSOP (Pb-free)
ICL3232EIAZ (Note 2) -40 to 85 16 Ld SSOP (Pb-free)
ICL3232EIB -40 to 85 16 Ld SOIC
ICL3232EIBZ (Note 2) -40 to 85 16 Ld SOIC (Pb-free)
ICL3221ECV
0 to 70 16 Ld TSSOP
M16.173
ICL3221ECVZ (Note 2) 0 to 70 16 Ld TSSOP (Pb-free) M16.173
M16.3
ICL3221EIA
ICL3221EIAZ (Note 2) -40 to 85 16 Ld SSOP (Pb-free)
ICL3221EIV -40 to 85 16 Ld TSSOP
-40 to 85 16 Ld SSOP
M16.209
M16.209
M16.173
ICL3232EIBNZ (Note 2) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15
ICL3232EIV-16
-40 to 85 16 Ld TSSOP
M16.173
ICL3232EIV-16Z
(Note 2)
-40 to 85 16 Ld TSSOP (Pb-free) M16.173
ICL3221EIVZ (Note 2) -40 to 85 16 Ld TSSOP (Pb-free) M16.173
ICL3232EIV-20
-40 to 85 20 Ld TSSOP
M20.173
ICL3222ECA
0 to 70 20 Ld SSOP
M20.209
M20.209
E18.3
ICL3232EIV-20Z
(Note 2)
-40 to 85 20 Ld TSSOP (Pb-free) M20.173
ICL3222ECAZ (Note 2) 0 to 70 20 Ld SSOP (Pb-free)
ICL3222ECP
ICL3222ECV
0 to 70 18 Ld PDIP
ICL3241ECA
0 to 70 28 Ld SSOP
M28.209
M28.209
M28.3
0 to 70 20 Ld TSSOP
M20.173
ICL3241ECAZ (Note 2) 0 to 70 28 Ld SSOP (Pb-free)
ICL3241ECB 0 to 70 28 Ld SOIC
ICL3241ECBZ (Note 2) 0 to 70 28 Ld SOIC (Pb-free)
ICL3241ECV 0 to 70 28 Ld TSSOP
ICL3222ECVZ (Note 2) 0 to 70 20 Ld TSSOP (Pb-free) M20.173
ICL3222EIA
ICL3222EIAZ (Note 2) -40 to 85 20 Ld SSOP (Pb-free)
ICL3222EIB -40 to 85 18 Ld SOIC
ICL3222EIBZ (Note 2) -40 to 85 18 Ld SOIC (Pb-free)
ICL3222EIV -40 to 85 20 Ld TSSOP
-40 to 85 20 Ld SSOP
M20.209
M20.209
M18.3
M28.3
M28.173
ICL3241ECVZ (Note 2) 0 to 70 28 Ld TSSOP (Pb-free) M28.173
M18.3
ICL3241EIA
ICL3241EIAZ (Note 2) -40 to 85 28 Ld SSOP (Pb-free)
ICL3241EIB -40 to 85 28 Ld SOIC
ICL3241EIBZ (Note 2) -40 to 85 28 Ld SOIC (Pb-free)
ICL3241EIV -40 to 85 28 Ld TSSOP
-40 to 85 28 Ld SSOP
M28.209
M28.209
M28.3
M20.173
ICL3222EIVZ (Note 2) -40 to 85 20 Ld TSSOP (Pb-free) M20.173
ICL3223ECA
ICL3223ECAZ (Note 2) 0 to 70 20 Ld SSOP (Pb-free)
ICL3223ECV 0 to 70 20 Ld TSSOP
0 to 70 20 Ld SSOP
M20.209
M20.209
M20.173
M28.3
M28.173
ICL3241EIVZ (Note 2) -40 to 85 28 Ld TSSOP (Pb-free) M28.173
ICL3223ECVZ (Note 2) 0 to 70 20 Ld TSSOP (Pb-free) M20.173
ICL3243ECA
ICL3243ECAZ (Note 2) 0 to 70 28 Ld SSOP (Pb-free)
ICL3243ECB 0 to 70 28 Ld SOIC
ICL3243ECBZ (Note 2) 0 to 70 28 Ld SOIC (Pb-free)
0 to 70 28 Ld SSOP
M28.209
M28.209
M28.3
ICL3223EIA
ICL3223EIAZ (Note 2) -40 to 85 20 Ld SSOP (Pb-free)
ICL3223EIV -40 to 85 20 Ld TSSOP
-40 to 85 20 Ld SSOP
M20.209
M20.209
M20.173
M28.3
ICL3223EIVZ (Note 2) -40 to 85 20 Ld TSSOP (Pb-free) M20.173
ICL3243ECV
0 to 70 28 Ld TSSOP
M28.173
ICL3232ECA
ICL3232ECAZ (Note 2) 0 to 70 16 Ld SSOP (Pb-free)
ICL3232ECB 0 to 70 16 Ld SOIC
ICL3232ECBZ (Note 2) 0 to 70 16 Ld SOIC (Pb-free)
0 to 70 16 Ld SSOP
M16.209
M16.209
M16.3
ICL3243ECVZA
(Note 2)
0 to 70 28 Ld TSSOP (Pb-free) M28.173
ICL3243ECVZ (Note 2) 0 to 70 28 Ld TSSOP (Pb-free) M28.173
ICL3243EIA
ICL3243EIAZ (Note 2) -40 to 85 28 Ld SSOP (Pb-free)
ICL3243EIV -40 to 85 28 Ld TSSOP
-40 to 85 28 Ld SSOP
M28.209
M28.209
M28.173
M16.3
ICL3232ECBN
0 to 70 16 Ld SOIC (N)
M16.15
ICL3232ECBNZ
(Note 2)
0 to 70 16 Ld SOIC (N) (Pb-free) M16.15
ICL3243EIVZ (Note 2) -40 to 85 28 Ld TSSOP (Pb-free) M28.173
ICL3232ECV-16
0 to 70 16 Ld TSSOP
M16.173
NOTES:
1. Most surface mount devices are available on tape and reel; add “-T” to suffix.
ICL3232ECV-16Z
(Note 2)
0 to 70 16 Ld TSSOP (Pb-free) M16.173
2. Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
ICL3232ECV-20
0 to 70 20 Ld TSSOP
M20.173
FN4910.18
2
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Pinouts
ICL3221E (SSOP, TSSOP)
ICL3222E (PDIP, SOIC)
TOP VIEW
TOP VIEW
EN
C1+
V+
1
2
3
4
5
6
7
8
16 FORCEOFF
15
EN
C1+
V+
1
2
3
4
5
6
7
8
9
18
17
SHDN
V
V
CC
CC
14 GND
13 T1
16 GND
15 T1
C1-
C2+
C2-
V-
C1-
C2+
C2-
V-
OUT
OUT
12 FORCEON
11 T1
14 R1
13 R1
12 T1
IN
IN
10 INVALID
R1
OUT
IN
IN
9
T2
OUT
11 T2
10
R1
IN
OUT
R2
R2
IN
OUT
ICL3222E (SSOP, TSSOP)
ICL3223E (SSOP, TSSOP)
TOP VIEW
TOP VIEW
20 SHDN
19
EN
1
2
20 FORCEOFF
19
EN
C1+
1
2
C1+
V+
V
CC
V
CC
3
18 GND
17 T1
3
18 GND
17 T1
V+
C1-
C2+
C2-
V-
C1-
C2+
C2-
V-
4
4
OUT
OUT
16 R1
15 R1
5
16 R1
15 R1
5
IN
IN
6
6
OUT
OUT
7
14 FORCEON
7
14 NC
13 T1
T2
8
13 T1
IN
T2
8
OUT
OUT
IN
R2
9
12
T2
R2
9
12
T2
IN
IN
IN
11 INVALID
IN
11 NC
10
10
R2
OUT
R2
OUT
ICL3232E (SOIC, SSOP, TSSOP-16)
ICL3232E (TSSOP-20)
TOP VIEW
TOP VIEW
C1+
V+
1
2
3
4
5
6
7
8
16 V
CC
NC
C1+
V+
1
2
20 NC
19
15 GND
14 T1
V
CC
C1-
C2+
C2-
V-
3
18 GND
17 T1
OUT
13 R1
12 R1
11 T1
IN
C1-
C2+
C2-
V-
4
OUT
5
16 R1
15 R1
14 T1
OUT
IN
IN
6
OUT
T2
10 T2
IN
7
OUT
R2
IN
IN
9
R2
OUT
T2
8
13
12
T2
R2
OUT
IN
R2
9
OUT
IN
10
11 NC
NC
FN4910.18
3
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Pinouts (Continued)
ICL3241E (SOIC, SSOP, TSSOP)
TOP VIEW
ICL3243E (SOIC, SSOP, TSSOP)
TOP VIEW
C2+
C2-
V-
1
2
28 C1+
27 V+
C2+
C2-
V-
1
2
28 C1+
27 V+
3
26 V
CC
25 GND
24 C1-
3
26 V
CC
25 GND
R1
R2
R3
R4
R5
4
IN
IN
IN
IN
IN
R1
R2
R3
R4
R5
4
IN
IN
IN
IN
IN
5
5
24 C1-
6
23 EN
6
23 FORCEON
22 FORCEOFF
21 INVALID
7
22 SHDN
7
8
21 R1
OUTB
OUTB
OUT
OUT
OUT
OUT
OUT
8
T1
9
20
R2
OUT
OUT
OUT
T1
9
20
R2
OUT
OUT
OUT
OUTB
OUT
OUT
OUT
OUT
OUT
10
11
12
13
14
19 R1
18 R2
17 R3
16 R4
15 R5
T2
T3
10
11
12
13
14
19 R1
18 R2
17 R3
16 R4
15 R5
T2
T3
T3
T2
T1
IN
IN
IN
T3
T2
T1
IN
IN
IN
Pin Descriptions
PIN
FUNCTION
V
System power supply input (3.0V to 5.5V).
Internally generated positive transmitter supply (+5.5V).
Internally generated negative transmitter supply (-5.5V).
Ground connection.
CC
V+
V-
GND
C1+
C1-
External capacitor (voltage doubler) is connected to this lead.
External capacitor (voltage doubler) is connected to this lead.
External capacitor (voltage inverter) is connected to this lead.
External capacitor (voltage inverter) is connected to this lead.
TTL/CMOS compatible transmitter Inputs.
C2+
C2-
T
IN
T
±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs.
±15kV ESD Protected, RS-232 compatible receiver inputs.
TTL/CMOS level receiver outputs.
OUT
R
IN
R
OUT
R
TTL/CMOS level, noninverting, always enabled receiver outputs.
OUTB
INVALID
EN
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
Active low receiver enable control; doesn’t disable R outputs.
OUTB
Active low input to shut down transmitters and on-board power supply, to place device in low power mode.
SHDN
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2).
FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).
FN4910.18
4
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits
ICL3221E
C
(OPTIONAL CONNECTION, NOTE)
3
+3.3V
+
0.1µF
15
2
C
3
C1+
V
CC
1
C
3
+
+
V+
V-
0.1µF
4
0.1µF
C1-
C2+
5
C
0.1µF
2
+
7
C
4
6
C2-
0.1µF
+
T
1
11
13
T1
T1
OUT
IN
TTL/CMOS
RS-232
LEVELS
LOGIC LEVELS
9
1
8
R1
R1
IN
OUT
5kΩ
R
1
EN
16
10
V
CC
FORCEOFF
INVALID
12
TO POWER
FORCEON
CONTROL LOGIC
GND
14
NOTE: The negative terminal of C can be connected to either V
3
or GND
CC
ICL3222E
C
(OPTIONAL CONNECTION, NOTE)
3
+3.3V
C
+
0.1µF
17
2
3
C1+
V
CC
1
+
+
C
3
+
+
V+
V-
0.1µF
4
5
0.1µF
C1-
C2+
C
0.1µF
2
7
C
4
6
C2-
0.1µF
T
T
1
2
12
15
8
T1
T2
T1
T2
IN
IN
OUT
OUT
11
13
TTL/CMOS
RS-232
LOGIC LEVELS
14
9
LEVELS
R1
R1
R2
OUT
IN
IN
5kΩ
R
1
10
1
R2
OUT
5kΩ
R
2
EN
18
V
CC
SHDN
GND
16
NOTE: The negative terminal of C can be connected to either V
3
or GND
CC
FN4910.18
5
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits (Continued)
ICL3223E
+3.3V
+
0.1µF
19
2
C
C1+
3
1
V
CC
C
+
3
+
V+
V-
0.1µF
4
5
0.1µF
C1-
C2+
C
0.1µF
2
+
7
C
4
6
C2-
0.1µF
+
T
T
1
2
13
17
8
T1
T2
T1
T2
IN
IN
OUT
OUT
12
15
TTL/CMOS
RS-232
LOGIC LEVELS
16
9
LEVELS
R1
R2
R1
R2
OUT
OUT
IN
IN
5kΩ
5kΩ
R
1
10
1
R
2
EN
20
11
V
FORCEOFF
INVALID
CC
14
TO POWER
FORCEON
CONTROL LOGIC
GND
18
ICL3232E
C
(OPTIONAL CONNECTION, NOTE)
C
3
+3.3V
+
0.1µF
16
1
C
C1+
V
2
1
CC
+
3
+
V+
V-
0.1µF
3
4
0.1µF
C1-
C2+
C
0.1µF
2
+
6
C
4
5
C2-
0.1µF
+
T
T
1
2
11
14
T1
T2
T1
IN
OUT
OUT
7
10
12
T2
IN
TTL/CMOS
RS-232
LOGIC LEVELS
13
LEVELS
R1
R1
OUT
IN
R
5kΩ
5kΩ
1
9
8
R2
R2
OUT
IN
R
2
GND
15
NOTE: The negative terminal of C can be connected to either V
3
or GND
CC
FN4910.18
6
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits (Continued)
ICL3241E
ICL3243E
26
+3.3V
+3.3V
+
+
0.1µF
28
0.1µF
28
26
27
3
C
27
C
3
C
0.1µF
+
1
C1+
V
CC
C1+
1
V
C
3
V+
V-
CC
+
+
0.1µF
+
V+
V-
0.1µF
24
1
0.1µF
24
C1-
C2+
C1-
C2+
1
C
2
C
2
C
4
+
3
9
+
0.1µF
C
4
0.1µF
2
0.1µF
2
C2-
+
0.1µF
OUT
C2-
T
T
T
+
1
2
3
14
9
T
T
T
1
2
3
T1
14
IN
T1
T1
OUT
IN
T1
13
10
11
RS-232
LEVELS
T2
T3
IN
IN
10
11
13
12
T2
T3
RS-232
LEVELS
OUT
OUT
T2
T3
IN
IN
12
21
T2
T3
OUT
OUT
R1
R2
OUTB
OUTB
20
19
20
19
R2
OUTB
4
5
R1
TTL/CMOS
OUT
4
5
R1
R2
IN
IN
LOGIC
R1
R1
R2
R
OUT
IN
5kΩ
5kΩ
1
LEVELS
R
TTL/CMOS
1
2
5kΩ
5kΩ
5kΩ
18
17
16
LOGIC
R2
OUT
LEVELS
18
R
R2
2
OUT
IN
R
6
7
8
R3
R4
R5
OUT
OUT
OUT
RS-232
R3
R4
R5
17
16
6
7
IN
IN
IN
LEVELS
5kΩ
RS-232
R
R
3
4
R3
R4
R3
R4
OUT
IN
LEVELS
R
R
3
4
5kΩ
5kΩ
OUT
IN
15
23
5kΩ
5kΩ
15
23
8
EN
R
5
R5
R5
OUT
IN
R
5
22
V
FORCEON
CC
SHDN
GND
25
22
21
V
CC
FORCEOFF
INVALID
TO POWER
CONTROL
LOGIC
GND
25
FN4910.18
7
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 3)
V
to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
θ
JA
(°C/W)
CC
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
18 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld Wide SOIC Package . . . . . . . . . . . . . . . . . . .
16 Ld Narrow SOIC Package. . . . . . . . . . . . . . . . . .
18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
28 Ld SSOP and TSSOP Packages . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC, SSOP, TSSOP - Lead Tips Only)
80
100
115
75
T
R
, FORCEOFF, FORCEON, EN, SHDN . . . . . . . . . -0.3V to 6V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
IN
75
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
135
122
145
140
100
T
R
OUT
, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3V
OUT CC
Short Circuit Duration
T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
OUT
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Operating Conditions
Temperature Range
ICL32XXECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXEIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1µF; Unless Otherwise Specified.
CC
1
4
Typicals are at T = 25°C
A
TEMP
(°C)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
All R Open, FORCEON = GND, FORCEOFF = V
IN
25
-
1.0
10
µA
CC
(ICL3221E, ICL3223E, ICL3243E Only)
Supply Current, Powerdown
FORCEOFF = SHDN = GND (Except ICL3232E)
25
25
-
-
1.0
0.3
10
µA
Supply Current,
Automatic Powerdown Disabled
All Outputs Unloaded,
FORCEON=FORCEOFF = ICL3243
SHDN = V
V
= 3.0V, ICL3241,
1.0
mA
CC
CC
V
= 3.15V, ICL3221,
25
-
0.3
1.0
mA
CC
ICL3222, ICL3223, ICL3232
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low
Input Logic Threshold High
T
, FORCEON, FORCEOFF, EN, SHDN
Full
Full
Full
Full
Full
-
2.0
2.4
-
-
0.8
-
V
V
IN
IN
T
, FORCEON,
V
V
= 3.3V
= 5.0V
-
CC
CC
FORCEOFF, EN, SHDN
-
-
V
Input Leakage Current
T
, FORCEON, FORCEOFF, EN, SHDN
±0.01
±0.05
±1.0
±10
µA
µA
IN
FORCEOFF = GND or EN = V
Output Leakage Current
(Except ICL3232E)
-
CC
Output Voltage Low
Output Voltage High
I
I
= 1.6mA
= -1.0mA
Full
Full
-
-
0.4
-
V
V
OUT
OUT
V
-0.6
V
-0.1
CC
CC
AUTOMATIC POWERDOWN (ICL3221E, ICL3223E, ICL3243E Only, FORCEON = GND, FORCEOFF = V
)
CC
Receiver Input Thresholds to
Enable Transmitters
ICL32XXE Powers Up (See Figure 6)
Full
-2.7
-0.3
-
-
2.7
0.3
V
V
Receiver Input Thresholds to
Disable Transmitters
ICL32XXE Powers Down (See Figure 6)
Full
-
INVALID Output Voltage Low
INVALID Output Voltage High
I
I
= 1.6mA
= -1.0mA
Full
Full
-
-
0.4
-
V
V
OUT
V
-0.6
CC
OUT
FN4910.18
8
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1µF; Unless Otherwise Specified.
CC
1
4
Typicals are at T = 25°C (Continued)
A
TEMP
(°C)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Receiver Threshold to Transmitters
25
-
100
-
µs
Enabled Delay (t
)
WU
Receiver Positive or Negative
25
-
-
1
-
-
µs
µs
Threshold to INVALID High Delay
(t
)
INVH
Receiver Positive or Negative
25
30
Threshold to INVALID Low Delay
(t
)
INVL
RECEIVER INPUTS
Input Voltage Range
Input Threshold Low
25
25
25
25
25
25
25
-25
0.6
0.8
-
-
25
-
V
V
V
V
V
V
= 3.3V
= 5.0V
= 3.3V
= 5.0V
1.2
1.5
1.5
1.8
0.5
5
CC
CC
CC
CC
-
V
Input Threshold High
2.4
2.4
-
V
-
V
Input Hysteresis
-
V
Input Resistance
3
7
kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing
Output Resistance
All Transmitter Outputs Loaded with 3kΩ to Ground
Full
Full
Full
Full
±5.0
±5.4
10M
±35
-
-
V
Ω
V
= V+ = V- = 0V, Transmitter Output = ±2V
300
-
CC
Output Short-Circuit Current
Output Leakage Current
-
-
±60
±25
mA
µA
V
= ±12V, V
CC
= 0V or 3V to 5.5V,
OUT
Automatic Powerdown or FORCEOFF = SHDN = GND
MOUSE DRIVEABILITY (ICL324XE Only)
Transmitter Output Voltage
(See Figure 9)
T1 = T2 = GND, T3 = V , T3
Loaded with 3kΩ
Full
±5
-
-
V
IN
IN
OUT
IN
CC
OUT
to GND, T1
and T2
Loaded with 2.5mA Each
OUT
TIMING CHARACTERISTICS
Maximum Data Rate
R
= 3kΩ, C = 1000pF, One Transmitter Switching
Full
25
25
25
25
25
25
25
25
250
500
0.15
0.15
200
200
100
50
-
-
kbps
µs
L
L
Receiver Propagation Delay
Receiver Input to Receiver
Output, C = 150pF
t
t
-
-
PHL
PLH
L
-
µs
Receiver Output Enable Time
Receiver Output Disable Time
Transmitter Skew
Normal Operation (Except ICL3232E)
Normal Operation (Except ICL3232E)
-
-
ns
-
-
ns
t
t
- t
PHL PLH
(Note 4)
-
-
ns
Receiver Skew
- t
PHL PLH
-
-
ns
Transition Region Slew Rate
V
= 3.3V,
C
C
= 150pF to 2500pF
= 150pF to 1000pF
4
6
-
30
30
V/µs
V/µs
CC
= 3kΩ to 7kΩ,
L
R
L
-
L
Measured from 3V to -3V or
-3V to 3V
ESD PERFORMANCE
RS-232 Pins (T
, R
)
Human Body Model
25
25
25
25
-
-
-
-
±15
±8
-
-
-
-
kV
kV
kV
kV
OUT IN
IEC61000-4-2 Contact Discharge
IEC61000-4-2 Air Gap Discharge
Human Body Model
±15
±2
All Other Pins
NOTE:
4. Transmitter skew is measured at the transmitter zero crossing points.
FN4910.18
9
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
The ICL3221E, ICL3222E, ICL3223E, ICL3241E inverting
Detailed Description
receivers disable only when EN is driven high. ICL3243E
receivers disable during forced (manual) powerdown, but not
during automatic powerdown (see Table 2).
ICL32XXE interface ICs operate from a single +3V to +5.5V
supply, guarantee a 250kbps minimum data rate, require
only four small external 0.1µF capacitors, feature low power
consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections:
charge pump, transmitters and receivers.
ICL3241E and ICL3243E monitor receivers remain active
even during manual powerdown and forced receiver disable,
making them extremely useful for Ring Indicator monitoring.
Standard receivers driving powered down peripherals must be
disabled to prevent current flow through the peripheral’s
protection diodes (see Figures 2 and 3). This renders them
useless for wake up functions, but the corresponding monitor
receiver can be dedicated to this task as shown in Figure 3.
Charge-Pump
Intersil’s new ICL32XXE family utilizes regulated on-chip
dual charge pumps as voltage doublers, and voltage
inverters to generate ±5.5V transmitter supplies from a V
CC
supply as low as 3.0V. This allows these devices to maintain
RS-232 compliant output levels over the ±10% tolerance
range of 3.3V powered systems. The efficient on-chip power
supplies require only four small, external 0.1µF capacitors
V
CC
R
R
XIN
XOUT
GND ≤ V
≤ V
-25V ≤ V
≤ +25V
5kΩ
ROUT
CC
RIN
for the voltage doubler and inverter functions at V
= 3.3V.
CC
GND
See the “Capacitor Selection” section, and Table 3 for
capacitor recommendations for other operating conditions.
The charge pumps operate discontinuously (i.e., they turn off
as soon as the V+ and V- supplies are pumped up to the
nominal values), resulting in significant power savings.
FIGURE 1. INVERTING RECEIVER CONNECTIONS
Low Power Operation
These 3V devices require a nominal supply current of
0.3mA, even at V
= 5.5V, during normal operation (not in
CC
Transmitters
powerdown mode). This is considerably less than the 5mA
to 11mA current required by comparable 5V RS-232 devices,
allowing users to reduce system power simply by switching
to this new family.
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-232 levels over a wide
range of single supply system voltages.
Pin Compatible Replacements for 5V Devices
The ICL3221E, ICL3222E, ICL3232E are pin compatible
with existing 5V RS-232 transceivers - see the Features
section on the front page for details.
Except for the ICL3232E, all transmitter outputs disable and
assume a high impedance state when the device enters the
powerdown mode (see Table 2). These outputs may be
driven to ±12V when disabled.
This pin compatibility coupled with the low I
and wide
CC
operating supply range, make the ICL32XXE potential lower
power, higher performance drop-in replacements for existing
5V applications. As long as the ±5V RS-232 output swings
are acceptable, and transmitter input pull-up resistors aren’t
required, the IICL32XXE should work in most 5V
applications.
All devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), V
≥ 3.0V, with one
CC
transmitter operating at full speed. Under more typical
conditions of V ≥ 3.3V, R = 3kΩ, and C = 250pF, one
CC
L
L
transmitter easily operates at 900kbps.
Transmitter inputs float if left unconnected, and may cause
When replacing a device in an existing 5V application, it is
I
increases. Connect unused inputs to GND for the best
CC
acceptable to terminate C to V
as shown on the Typical
performance.
3
CC
Operating Circuit. Nevertheless, terminate C to GND if
3
Receivers
possible, as slightly better performance results from this
configuration.
All the ICL32XXE devices contain standard inverting
receivers that three-state (except for the ICL3232E) via the
EN or FORCEOFF control lines. Additionally, the two
ICL324XE products include noninverting (monitor) receivers
Powerdown Functionality
(Except ICL3232E)
(denoted by the R
label) that are always active,
OUTB
The already low current requirement drops significantly
when the device enters powerdown mode. In powerdown,
supply current drops to 1µA, because the on-chip charge
regardless of the state of any control lines. All the receivers
convert RS-232 signals to CMOS output levels and accept
inputs up to ±25V while presenting the required 3kΩ to 7kΩ
input impedance (see Figure 1) even if the power is off
pump turns off (V+ collapses to V , V- collapses to GND),
CC
and the transmitter outputs three-state. Inverting receiver
outputs may or may not disable in powerdown; refer to
Table 2 for details. This micro-power mode makes these
devices ideal for battery powered and portable applications.
(V
= 0V). The receivers’ Schmitt trigger input stage uses
CC
hysteresis to increase noise immunity and decrease errors
due to slow input signal transitions.
FN4910.18
10
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
The ICL3221E, ICL3223E, and ICL3243E utilize a two pin
Software Controlled (Manual) Powerdown
approach where the FORCEON and FORCEOFF inputs
determine the IC’s mode. For always enabled operation,
FORCEON and FORCEOFF are both strapped high. To
switch between active and powerdown modes, under logic
or software control, only the FORCEOFF input need be
driven. The FORCEON state isn’t critical, as FORCEOFF
dominates over FORCEON. Nevertheless, if strictly manual
control over powerdown is desired, the user must strap
FORCEON high to disable the automatic powerdown
circuitry. ICL3243E inverting (standard) receiver outputs also
disable when the device is in manual powerdown, thereby
eliminating the possible current path through a shutdown
peripheral’s input protection diode (see Figures 2 and 3).
Most devices in the ICL32XXE family provide pins that allow
the user to force the IC into the low power, standby state.
On the ICL3222E and ICL3241E, the powerdown control is
via a simple shutdown (SHDN) pin. Driving this pin high
enables normal operation, while driving it low forces the IC
into its powerdown state. Connect SHDN to V
if the
CC
powerdown function isn’t needed. Note that all the receiver
outputs remain enabled during shutdown (see Table 2). For
the lowest power consumption during powerdown, the
receivers should also be disabled by driving the EN input
high (see next section, and Figures 2 and 3).
TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE
RS-232
SIGNAL
PRESENT
AT
FORCEOFF
(NOTE 5)
OUTB
OUTPUTS OUTPUTS OUTPUT
RECEIVER
INPUT?
OR SHDN FORCEON
EN
TRANSMITTER RECEIVER
R
INVALID
INPUT
INPUT
INPUT
OUTPUTS
MODE OF OPERATION
ICL3222E, ICL3241E
N/A
N/A
N/A
N/A
L
L
N/A
N/A
N/A
N/A
L
H
L
High-Z
High-Z
Active
Active
Active
High-Z
Active
High-Z
Active
Active
Active
Active
N/A
N/A
N/A
N/A
Manual Powerdown
Manual Powerdown w/Rcvr. Disabled
Normal Operation
H
H
H
Normal Operation w/Rcvr. Disabled
ICL3221E, ICL3223E
No
No
H
H
H
H
H
H
L
H
H
L
L
H
L
Active
Active
Active
Active
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Active
High-Z
Active
High-Z
Active
High-Z
Active
High-Z
Active
High-Z
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
L
L
Normal Operation
(Auto Powerdown Disabled)
Yes
H
H
L
Normal Operation
(Auto Powerdown Enabled)
Yes
L
H
L
No
L
Powerdown Due to Auto Powerdown
Logic
No
L
H
L
L
Yes
X
X
X
X
H
H
L
Manual Powerdown
Yes
L
H
L
Manual Powerdown w/Rcvr. Disabled
Manual Powerdown
No
L
No
L
H
L
Manual Powerdown w/Rcvr. Disabled
ICL3243E
No
H
H
H
H
L
L
N/A
N/A
N/A
Active
Active
High-Z
Active
Active
Active
Active
Active
Active
L
H
L
Normal Operation
(Auto Powerdown Disabled)
Yes
No
Normal Operation
(Auto Powerdown Enabled)
Powerdown Due to Auto Powerdown
Logic
Yes
No
L
L
X
X
N/A
N/A
High-Z
High-Z
High-Z
High-Z
Active
Active
H
L
Manual Powerdown
Manual Powerdown
NOTE:
5. Applies only to the ICL3241E and ICL3243E.
FN4910.18
11
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
The INVALID output always indicates whether or not a valid
FORCEOFF
FORCEON
RS-232 signal is present at any of the receiver inputs (see
Table 2), giving the user an easy way to determine when the
interface block should power down. In the case of a
disconnected interface cable where all the receiver inputs
are floating (but pulled to GND by the internal receiver pull
down resistors), the INVALID logic detects the invalid levels
and drives the output low. The power management logic
then uses this indicator to power down the interface block.
Reconnecting the cable restores valid levels at the receiver
inputs, INVALID switches high, and the power management
logic wakes up the interface block. INVALID can also be
used to indicate the DTR or RING INDICATOR signal, as
long as the other receiver inputs are floating, or driven to
GND (as in the case of a powered down driver). Connecting
FORCEOFF and FORCEON together disables the
PWR
MGT
LOGIC
INVALID
ICL3221E,
ICL3223E,
ICL3243E
I/O
UART
CPU
automatic powerdown feature, enabling them to function as
a manual SHUTDOWN input (see Figure 4).
FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
V
CC
V
With any of the above control schemes, the time required to
exit powerdown, and resume transmission is only 100µs. A
mouse, or other application, may need more time to wake up
from shutdown. If automatic powerdown is being utilized, the
RS-232 device will reenter powerdown if valid receiver levels
aren’t reestablished within 30µs of the ICL32XXE powering
up. Figure 5 illustrates a circuit that keeps the ICL32XXE
from initiating automatic powerdown for 100ms after
powering up. This gives the slow-to-wake peripheral circuit
time to reestablish valid RS-232 output levels.
CC
CURRENT
FLOW
V
CC
V
= V
CC
OUT
Rx
POWERED
DOWN
UART
Tx
OLD
SHDN = GND
GND
RS-232 CHIP
MASTER POWERDOWN LINE
0.1µF
POWER
MANAGEMENT
UNIT
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
1MΩ
FORCEOFF
FORCEON
V
CC
ICL3221E, ICL3223E, ICL3243E
TRANSITION
DETECTOR
FIGURE 5. CIRCUIT TO PREVENT AUTO POWERDOWN FOR
100ms AFTER FORCED POWERUP
TO
ICL324XE
WAKE-UP
LOGIC
V
Automatic Powerdown
CC
R2
(ICL3221E, ICL3223E, ICL3243E Only)
OUTB
Even greater power savings is available by using the
devices which feature an automatic powerdown function.
When no valid RS-232 voltages (see Figure 6) are sensed
on any receiver input for 30µs, the charge pump and
transmitters powerdown, thereby reducing supply current to
1µA. Invalid receiver levels occur whenever the driving
peripheral’s outputs are shut off (powered down) or when the
RS-232 interface cable is disconnected. The ICL32XXE
powers back up whenever it detects a valid RS-232 voltage
level on any receiver input. This automatic powerdown
R
T
V
= HI-Z
X
OUT
R2
OUT
POWERED
DOWN
R2
IN
UART
T1
IN
X
T1
OUT
FORCEOFF = GND
OR SHDN = GND, EN = V
CC
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
FN4910.18
12
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
feature provides additional system power savings without
changes to the existing operating system.
Receiver ENABLE Control
(ICL3221E, ICL3222E, ICL3223E, ICL3241E Only)
Several devices also feature an EN input to control the
receiver outputs. Driving EN high disables all the inverting
(standard) receiver outputs placing them in a high
impedance state. This is useful to eliminate supply current,
due to a receiver output forward biasing the protection diode,
VALID RS-232 LEVEL - ICL32XXE IS ACTIVE
2.7V
INDETERMINATE - POWERDOWN MAY OR
MAY NOT OCCUR
0.3V
when driving the input of a powered down (V
= GND)
CC
INVALID LEVEL - POWERDOWN OCCURS AFTER 30µs
-0.3V
peripheral (see Figure 2). The enable input has no effect on
transmitter nor monitor (R ) outputs.
OUTB
INDETERMINATE - POWERDOWN MAY OR
MAY NOT OCCUR
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those listed
in Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and slightly
-2.7V
VALID RS-232 LEVEL - ICL32XXE IS ACTIVE
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
Automatic powerdown operates when the FORCEON input
is low, and the FORCEOFF input is high. Tying FORCEON
high disables automatic powerdown, but manual powerdown
is always available via the overriding FORCEOFF input.
Table 2 summarizes the automatic powerdown functionality.
reduces power consumption. C , C , and C can be
2
3
4
increased without increasing C ’s value, however, do not
1
increase C without also increasing C , C , and C to
1
2
3
4
maintain the proper ratios (C to the other capacitors).
1
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
Devices with the automatic powerdown feature include an
INVALID output signal, which switches low to indicate that
invalid levels have persisted on all of the receiver inputs for
more than 30µs (see Figure 7). INVALID switches high 1µs
after detecting a valid RS-232 level on a receiver input.
INVALID operates in all modes (forced or automatic
powerdown, or forced on), so it is also useful for systems
employing manual powerdown circuitry. When automatic
powerdown is utilized, INVALID = 0 indicates that the
ICL32XXE is in powerdown mode.
TABLE 3. REQUIRED CAPACITOR VALUES
V
C
C , C , C
CC
1
2
3
4
(V)
(µF)
0.1
(µF)
3.0 to 3.6
4.5 to 5.5
3.0 to 5.5
0.1
0.047
0.1
0.33
0.47
RECEIVER
INPUTS
INVALID
REGION
}
Power Supply Decoupling
TRANSMITTER
OUTPUTS
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple V
to ground with a
CC
V
CC
0
INVALID
OUTPUT
t
t
INVH
INVL
capacitor of the same value as the charge-pump capacitor C .
1
Connect the bypass capacitor as close as possible to the IC.
PWR UP
AUTOPWDN
V+
Operation Down to 2.7V
V
CC
0
ICL32XXE transmitter outputs meet RS-562 levels (±3.7V),
at full data rate, with V
as low as 2.7V. RS-562 levels
CC
typically ensure interoperability with RS-232 devices.
V-
Transmitter Outputs when Exiting
Powerdown
FIGURE 7. AUTOMATIC POWERDOWN AND INVALID
TIMING DIAGRAMS
Figure 8 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
The time to recover from automatic powerdown mode is
typically 100µs.
FN4910.18
March 8, 2005
13
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
loads in parallel with 1000pF, at 120kbps. Figure 12 shows
the loopback results for a single transmitter driving 1000pF
and an RS-232 load at 250kbps. The static transmitters were
also loaded with an RS-232 receiver.
5V/DIV
FORCEOFF
V
CC
+
T1
0.1µF
V
CC
V+
V-
+
C1+
+
C
1
2
C
3
4
2V/DIV
C1-
C2+
C2-
ICL32XXE
+
C
C
+
T2
T
T
IN
OUT
V
= +3.3V
CC
C1 - C4 = 0.1µF
1000pF
R
IN
R
OUT
TIME (20µs/DIV)
FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
EN
5K
SHDN OR
FORCEOFF
V
CC
Mouse Driveability
The ICL3241E and ICL3243E have been specifically
designed to power a serial mouse while operating from low
voltage supplies. Figure 9 shows the transmitter output
voltages under increasing load current. The on-chip
switching regulator ensures the transmitters will supply at
least ±5V during worst case conditions (15mA for paralleled
V+ transmitters, 7.3mA for single V- transmitter). The
Automatic Powerdown feature does not work with a mouse,
FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV
T1
IN
so FORCEOFF and FORCEON should be connected to V
.
T1
CC
OUT
6
5
4
3
V
+
OUT
R1
OUT
V
= +3.3V
V
= 3.0V
CC
C1 - C4 = 0.1µF
CC
2
1
0
T1
5µs/DIV
V
+
OUT
FIGURE 11. LOOPBACK TEST AT 120kbps
-1
-2
-3
-4
-5
-6
T2
T3
ICL3241E, ICL3243E
V
V
-
CC
1
OUT
5V/DIV
T1
V
-
OUT
IN
0
2
3
4
5
6
7
8
9
10
LOAD CURRENT PER TRANSMITTER (mA)
FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL V CURRENT)
T1
OUT
OUT+
High Data Rates
R1
OUT
The ICL32XXE maintain the RS-232 ±5V minimum
transmitter output voltages even at high data rates.
Figure 10 details a transmitter loopback test circuit, and
Figure 11 illustrates the loopback test result at 120kbps. For
V
= +3.3V
CC
C1 - C4 = 0.1µF
2µs/DIV
FIGURE 12. LOOPBACK TEST AT 250kbps
this test, all transmitters were simultaneously driving RS-232
FN4910.18
14
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an IC’s ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
Interconnection with 3V and 5V Logic
The ICL32XX directly interface with 5V CMOS and TTL logic
families. Nevertheless, with the ICL32XX at 3.3V, and the logic
supply at 5V, AC, HC, and CD4000 outputs can drive ICL32XX
inputs, but ICL32XX outputs do not reach the minimum V for
these logic families. See Table 4 for more information.
IH
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
IEC61000-4-2 Testing
SYSTEM POWER-
SUPPLYVOLTAGE V SUPPLY
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.
CC
(V)
VOLTAGE (V)
COMPATIBILITY
3.3
3.3
Compatible with all CMOS
families.
5
5
5
Compatible with all TTL and
CMOS logic families.
3.3
Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with
AC, HC, and CD4000 CMOS
inputs.
±15kV ESD Protection
All pins on ICL32XX devices include ESD protection
structures, but the ICL32XXE family incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to ±15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on the
exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that
might destroy unprotected ICs. These new ESD structures
protect the device whether or not it is powered up, protect
without allowing any latchup mechanism to activate, and
don’t interfere with RS-232 signals as large as ±25V.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
Typical Performance Curves V = 3.3V, T = 25°C
CC
A
25
20
6
V
+
OUT
4
2
1 TRANSMITTER AT 250kbps
1 OR 2 TRANSMITTERS AT 30kbps
15
0
-SLEW
-2
-4
+SLEW
10
V
-
OUT
5
-6
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 14. SLEW RATE vs LOAD CAPACITANCE
FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
FN4910.18
15
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Performance Curves V = 3.3V, T = 25°C (Continued)
CC
A
45
45
40
35
30
25
20
15
10
ICL3221E
ICL3222E, ICL3223E, ICL3232E
40
35
30
25
20
15
10
250kbps
250kbps
120kbps
20kbps
120kbps
20kbps
5
0
5
0
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 16. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 15. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
45
3.5
NO LOAD
ICL324XE
ALL OUTPUTS STATIC
40
3.0
250kbps
ICL3221E, ICL3222E, ICL3223E, ICL3232E
2.5
35
30
2.0
1.5
1.0
120kbps
25
20
20kbps
ICL324XE
15
0.5
ICL324XE
0
10
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
4000
5000
2000
3000
1000
0
SUPPLY VOLTAGE (V)
LOAD CAPACITANCE (pF)
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3221E: 286
ICL3222E: 338
ICL3223E: 357
ICL3232E: 296
ICL324XE: 464
PROCESS:
Si Gate CMOS
FN4910.18
16
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Dual-In-Line Plas tic Packages (PDIP)
E18.3 (JEDEC MS-001-BC ISSUE D)
N
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.845
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
21.47
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.880
-
4.95
0.558
1.77
0.355
22.35
-
-
A2
A
-C-
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
-
eA
A1
A
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
18
18
JEDEC seating plane gauge GS-3.
Rev. 2 11/03
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3
may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN4910.18
17
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INCHES
MIN
MILLIMETERS
INDEX
AREA
M
L
M
B
0.25(0.010)
H
SYMBOL
MAX
0.069
0.010
0.019
0.010
0.394
0.157
MIN
1.35
0.10
0.35
0.19
9.80
3.80
MAX
1.75
NOTES
E
A
A1
B
C
D
E
e
0.053
0.004
0.014
0.007
0.386
0.150
-
-B-
0.25
-
0.49
9
1
2
3
0.25
-
10.00
4.00
3
SEATING PLANE
A
4
-A-
o
D
h x 45
0.050 BSC
1.27 BSC
-
H
h
0.228
0.010
0.016
0.244
0.020
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
-C-
α
µ
5
e
A1
L
6
C
B
0.10(0.004)
N
α
16
16
7
M
M
S
B
o
o
o
o
0.25(0.010)
C
A
0
8
0
8
-
Rev. 1 02/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
FN4910.18
18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plas tic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
INCHES
MIN
-
MILLIMETERS
E1
-B-
GAUGE
PLANE
SYMBOL
MAX
0.043
0.006
0.037
0.012
0.008
0.201
0.177
MIN
-
MAX
1.10
0.15
0.95
0.30
0.20
5.10
4.50
NOTES
A
A1
A2
b
-
0.002
0.033
0.0075
0.0035
0.193
0.169
0.05
0.85
0.19
0.09
4.90
4.30
-
1
2
3
-
L
0.25
0.05(0.002)
SEATING PLANE
A
9
0.010
A2
-A-
c
-
D
D
3
-C-
E1
e
4
α
0.026 BSC
0.65 BSC
-
e
A1
c
E
0.246
0.256
6.25
6.50
-
b
0.10(0.004)
L
0.020
0.028
0.50
0.70
6
0.10(0.004) M
C
A M B S
N
16
16
7
o
o
o
o
0
8
0
8
-
α
NOTES:
Rev. 1 2/02
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
FN4910.18
19
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plas tic Packages (SSOP)
M16.209 (JEDEC MO-150-AC ISSUE B)
N
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MIN
-
MAX
0.078
-
MIN
-
MAX
2.00
-
NOTES
-B-
A
A1
A2
B
-
-
0.002
0.065
0.009
0.004
0.233
0.197
0.05
1.65
0.22
0.09
5.90
5.00
1
2
3
0.072
0.014
0.009
0.255
0.220
1.85
0.38
0.25
6.50
5.60
-
L
0.25
SEATING PLANE
A
9
-
0.010
A2
-A-
C
D
E
D
3
4
-
-C-
α
µ
e
0.026 BSC
0.65 BSC
e
A1
C
H
L
0.292
0.322
7.40
8.20
-
B
0.10(0.004)
0.022
0.037
0.55
0.95
6
7
-
0.25(0.010) M
C
A M B S
N
α
16
16
o
o
o
o
0
8
0
8
NOTES:
Rev. 2 3/95
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen-
sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910.18
20
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plas tic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
10.50
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.3977
0.2914
-
-A-
o
0.4133 10.10
3
h x 45
D
0.2992
7.40
4
-C-
0.050 BSC
1.27 BSC
-
α
µ
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C A M B S
N
α
16
16
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910.18
21
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plas tic Packages (SOIC)
M18.3 (JEDEC MS-013-AB ISSUE C)
N
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
11.35
7.40
MAX
2.65
0.30
0.51
0.32
11.75
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
0.4625
0.2992
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.4469
0.2914
-
-A-
o
3
h x 45
D
4
-C-
0.050 BSC
1.27 BSC
-
α
µ
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C A M B S
N
α
18
18
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Thelead width “B”, as measured 0.36mm(0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910.18
22
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plas tic Packages (TSSOP)
M20.173
N
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
GAUGE
PLANE
INCHES
MIN
-
MILLIMETERS
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.260
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
6.60
4.50
NOTES
A
A1
A2
b
-
1
2
3
0.002
0.031
0.0075
0.0035
0.252
0.169
0.05
0.80
0.19
0.09
6.40
4.30
-
L
0.25
0.05(0.002)
SEATING PLANE
A
-
0.010
A2
-A-
9
D
c
-
-C-
D
3
α
E1
e
4
e
A1
c
0.026 BSC
0.65 BSC
-
b
0.10(0.004)
E
0.246
0.256
6.25
6.50
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
0.45
0.75
6
N
20
20
7
NOTES:
o
o
o
o
0
8
0
8
-
α
1. These package dimensions are within allowable dimensions of
Rev. 1 6/98
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
FN4910.18
23
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Shrink Small Outline Plas tic Packages (SSOP)
M20.209 (JEDEC MO-150-AE ISSUE B)
N
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
M
M
B
0.25(0.010)
H
INCHES
MIN
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MAX
0.078
0.008’
0.070’
0.015
0.008
0.289
0.212
MIN
1.73
0.05
1.68
0.25
0.09
7.07
5.20’
MAX
1.99
0.21
1.78
0.38
0.20’
7.33
5.38
NOTES
-B-
A
A1
A2
B
0.068
0.002
0.066
0.010’
0.004
0.278
0.205
1
2
3
L
0.25
SEATING PLANE
A
9
0.010
A2
-A-
C
D
E
D
3
4
-C-
α
e
0.026 BSC
0.65 BSC
e
A1
C
H
L
0.301
0.311
7.65
7.90’
B
0.10(0.004)
0.025
0.037
0.63
0.95
6
7
M
M
S
B
0.25(0.010)
C
A
N
α
20
20
0 deg.
8 deg.
0 deg.
8 deg.
NOTES:
Rev. 3 11/02
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
FN4910.18
24
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plas tic Packages (TSSOP)
M28.173
N
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
-
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.386
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
9.80
4.50
NOTES
A
A1
A2
b
-
1
2
3
0.002
0.031
0.0075
0.0035
0.378
0.169
0.05
0.80
0.19
0.09
9.60
4.30
-
L
0.25
0.05(0.002)
-
SEATING PLANE
A
0.010
A2
9
-A-
D
c
-
D
3
-C-
α
E1
e
4
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
6.50
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
0.45
0.75
6
N
28
28
7
NOTES:
o
o
o
o
0
8
0
8
-
α
1. These package dimensions are within allowable dimensions of
Rev. 0 6/98
JEDEC MO-153-AE, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
FN4910.18
25
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Shrink Small Outline Plas tic Packages (SSOP)
M28.209 (JEDEC MO-150-AH ISSUE B)
N
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MIN
-
MAX
0.078
-
MIN
-
MAX
2.00
-
NOTES
-B-
A
A1
A2
B
-
0.002
0.065
0.009
0.004
0.390
0.197
0.05
1.65
0.22
0.09
9.90
5.00
-
1
2
3
0.072
0.014
0.009
0.413
0.220
1.85
0.38
0.25
10.50
5.60
-
L
0.25
SEATING PLANE
A
9
0.010
A2
-A-
C
D
E
-
D
3
-C-
4
α
µ
e
0.026 BSC
0.65 BSC
-
e
A1
C
H
L
0.292
0.322
7.40
8.20
-
B
0.10(0.004)
0.022
0.037
0.55
0.95
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
o
o
o
o
NOTES:
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
Rev. 1 3/95
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.20mm (0.0078 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual in-
dex feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dam-
bar protrusion shall be 0.13mm (0.005 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN4910.18
26
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plas tic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
0.7125 17.70
3
-A-
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
µ
H
h
0.394
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
0.01
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4910.18
27
March 8, 2005
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