ICL7660AIBAZA [INTERSIL]
CMOS Voltage Converters; CMOS电压转换器
| 型号： | ICL7660AIBAZA |
| 厂家： | 
Intersil |
| 描述： | CMOS Voltage Converters |
| 文件： | 总11页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICL7660, ICL7660A
®
Data Sheet
October 10, 2005
FN3072.7
CMOS Voltage Converters
Features
The Intersil ICL7660 and ICL7660A are monolithic CMOS
power supply circuits which offer unique performance
advantages over previously available devices. The ICL7660
performs supply voltage conversions from positive to
negative for an input range of +1.5V to +10.0V resulting in
complementary output voltages of -1.5V to -10.0V and the
ICL7660A does the same conversions with an input range of
+1.5V to +12.0V resulting in complementary output voltages
of -1.5V to -12.0V. Only 2 noncritical external capacitors are
needed for the charge pump and charge reservoir functions.
The ICL7660 and ICL7660A can also be connected to
function as voltage doublers and will generate output
voltages up to +18.6V with a +10V input.
• Simple Conversion of +5V Logic Supply to ±5V Supplies
• Simple Voltage Multiplication (V = (-) nV
)
IN
OUT
• Typical Open Circuit Voltage Conversion Efficiency 99.9%
• Typical Power Efficiency 98%
• Wide Operating Voltage Range
- ICL7660 . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 10.0V
- ICL7660A . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 12.0V
• ICL7660A 100% Tested at 3V
• Easy to Use - Requires Only 2 External Non-Critical
Passive Components
• No External Diode Over Full Temp. and Voltage Range
• Pb-Free Plus Anneal Available (RoHS Compliant)
Contained on the chip are a series DC supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. A unique logic element senses the most
negative voltage in the device and ensures that the output
N-Channel switch source-substrate junctions are not forward
biased. This assures latchup free operation.
Applications
• On Board Negative Supply for Dynamic RAMs
• Localized µProcessor (8080 Type) Negative Supplies
• Inexpensive Negative Supplies
The oscillator, when unloaded, oscillates at a nominal
frequency of 10kHz for an input supply voltage of 5.0V. This
frequency can be lowered by the addition of an external
capacitor to the “OSC” terminal, or the oscillator may be
overdriven by an external clock.
• Data Acquisition Systems
The “LV” terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV)
operation. At medium to high voltages (+3.5V to +10.0V for
the ICL7660 and +3.5V to +12.0V for the ICL7660A), the LV
pin is left floating to prevent device latchup.
Pinouts
ICL7660, ICL7660A
(8 LD PDIP, SOIC)
TOP VIEW
NC
CAP+
GND
1
2
3
4
8
7
6
5
V+
OSC
LV
CAP-
V
OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1999-2004, 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ICL7660, ICL7660A
Ordering Information
PART NUMBER
ICL7660CBA*
TEMP. RANGE (°C)
0 to 70
PACKAGE
8 Ld SOIC (N)
PKG. DWG. #
M8.15
7660CBA
ICL7660CBAZ* (See Note)
ICL7660CBAZA* (See Note)
ICL7660CPA
7660CBAZ
7660CBAZ
7660CPA
0 to 70
8 Ld SOIC (N) (Pb-free)
8 Ld SOIC (N) (Pb-free)
8 Ld PDIP
M8.15
M8.15
E8.3
0 to 70
0 to 70
ICL7660CPAZ ( See Note)
ICL7660ACBA*
7660CPAZ
7660ACBA
7660ACBAZ
7660ACPA
7660ACPAZ
7660AIBA
7660AIBAZ
0 to 70
8 Ld PDIP** (Pb-free)
8 Ld SOIC (N)
E8.3
0 to 70
M8.15
M8.15
E8.3
ICL7660ACBAZA* (See Note)
ICL7660ACPA
0 to 70
8 Ld SOIC (N) (Pb-free)
8 Ld PDIP
0 to 70
ICL7660ACPAZ (See Note)
ICL7660AIBA*
0 to 70
8 Ld PDIP** (Pb-free)
8 Ld SOIC (N)
E8.3
-40 to 85
-40 to 85
M8.15
M8.15
ICL7660AIBAZA* (See Note)
8 Ld SOIC (N) (Pb-free)
*Add “-T” suffix to part number for tape and reel packaging.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN3072.7
2
October 10, 2005
ICL7660, ICL7660A
C
Absolute Maximum Ratings
Supply Voltage
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
θ
(°C/W)
JC
JA
ICL7660 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10.5V
ICL7660A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V
LV and OSC Input Voltage. . . . . . -0.3V to (V+ +0.3V) for V+ < 5.5V
(Note 2) . . . . . . . . . . . . . . (V+ -5.5V) to (V+ +0.3V) for V+ > 5.5V
Current into LV (Note 2). . . . . . . . . . . . . . . . . . . 20µA for V+ > 3.5V
PDIP Package* . . . . . . . . . . . . . . . . . .
110
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
160
N/A
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Output Short Duration (V
≤ 5.5V) . . . . . . . . . . . .Continuous
SUPPLY
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Range
ICL7660C, ICL7660AC. . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL7660AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications ICL7660 and ICL7660A, V+ = 5V, T = 25°C, C
= 0, Test Circuit Figure 11
OSC
A
Unless Otherwise Specified
ICL7660
ICL7660A
PARAMETER
Supply Current
SYMBOL
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX UNITS
I+
R
= ∞
-
170 500
-
1.5
3
-
80
-
165
3.5
12
µA
V
L
Supply Voltage Range - Lo
Supply Voltage Range - Hi
Output Source Resistance
V +
MIN ≤ T ≤ MAX, R = 10kΩ, LV to GND
1.5
-
-
3.5
10.0
100
120
150
-
L
A
L
V +
MIN ≤ T ≤ MAX, R = 10kΩ, LV to Open
3.0
-
V
H
A
L
R
I
I
I
I
= 20mA, T = 25°C
-
-
-
-
-
55
-
60
-
100
120
-
Ω
Ω
Ω
Ω
Ω
OUT
OUT
OUT
OUT
A
= 20mA, 0°C ≤ T ≤ 70°C
-
A
= 20mA, -55°C ≤ T ≤ 125°C
-
-
-
A
= 20mA, -40°C ≤ T ≤ 85°C
-
-
-
120
300
OUT
+
A
V
= 2V, I
= 3mA, LV to GND
-
300
-
-
OUT
0°C ≤ T ≤ 70°C
A
V+ = 2V, I
= 3mA, LV to GND,
-55°C ≤ T ≤ 125°C
-
-
400
-
-
-
Ω
OUT
A
Oscillator Frequency
Power Efficiency
f
-
95
97
-
10
98
-
-
-
-
-
-
96
99
-
10
98
99.9
1
-
-
-
-
-
kHz
%
OSC
P
R = 5kΩ
L
EF
OUT EF
Voltage Conversion Efficiency
Oscillator Impedance
V
R = ∞
99.9
1.0
100
%
L
Z
V+ = 2V
V = 5V
MΩ
kΩ
OSC
-
-
-
ICL7660A, V+ = 3V, T = 25°C, OSC = Free running, Test Circuit Figure 11, Unless Otherwise Specified
A
Supply Current (Note 3)
I+
V+ = 3V, R = ∞, 25°C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
26
-
100
125
125
150
200
200
-
µA
µA
µA
Ω
L
0°C < T < 70°C
-
-
A
-40°C < T < 85°C
-
A
Output Source Resistance
Oscillator Frequency (Note 3)
R
V+ = 3V, I
= 10mA
0°C < T < 70°C
-
97
-
OUT
OUT
-
Ω
A
-40°C < T < 85°C
A
-
-
Ω
f
V+ = 3V (same as 5V conditions)
5.0
3.0
3.0
8
-
kHz
kHz
kHz
OSC
0°C < T < 70°C
-
A
-40°C < T < 85°C
-
-
A
FN3072.7
3
October 10, 2005
ICL7660, ICL7660A
Electrical Specifications ICL7660 and ICL7660A, V+ = 5V, T = 25°C, C
= 0, Test Circuit Figure 11
OSC
A
Unless Otherwise Specified (Continued)
ICL7660
ICL7660A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX UNITS
Voltage Conversion Efficiency
V
EFF V+ = 3V, R = ∞
-
-
-
-
-
-
-
-
-
-
-
-
99
99
96
95
-
-
-
-
-
-
-
-
%
%
%
%
OUT
L
T
< T < T
MAX
MIN
A
Power Efficiency
P
EFF
V+ = 3V, R = 5kΩ
L
T
< T < T
MAX
MIN
A
NOTES:
2. Connecting any input terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs
from sources operating from external supplies be applied prior to “power up” of the ICL7660, ICL7660A.
3. Derate linearly above 50°C by 5.5mW/°C.
4. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very
small but finite stray capacitance present, of the order of 5pF.
5. The Intersil ICL7660A can operate without an external diode over the full temperature and voltage range. This device will function in existing
designs which incorporate an external diode with no degradation in overall circuit performance.
Functional Block Diagram
V+
CAP+
VOLTAGE
RC
OSCILLATOR
LEVEL
÷2
TRANSLATOR
CAP-
V
OUT
OSC
LV
VOLTAGE
LOGIC
REGULATOR
NETWORK
Typical Performance Curves (Test Circuit of Figure 11)
10
10K
T
= 25°C
A
8
SUPPLY VOLTAGE RANGE
(NO DIODE REQUIRED)
6
1000
4
2
0
100
10
0
1
2
3
4
5
6
7
8
-55
-25
0
25
50
100
125
SUPPLY VOLTAGE (V+)
TEMPERATURE (°C)
FIGURE 1. OPERATING VOLTAGE AS A FUNCTION OF
TEMPERATURE
FIGURE 2. OUTPUT SOURCE RESISTANCE AS A FUNCTION
OF SUPPLY VOLTAGE
FN3072.7
4
October 10, 2005
ICL7660, ICL7660A
Typical Performance Curves (Test Circuit of Figure 11) (Continued)
350
300
250
200
150
100
100
98
96
94
92
90
88
86
84
82
80
T
= 25°C
I
= 1mA
A
OUT
I
= 1mA
OUT
I
= 15mA
OUT
V+ = +2V
50
0
V+ = 5V
V+ = +5V
100
1K
OSC. FREQUENCY f
10K
-55
-25
0
25
50
75
100
125
(Hz)
OSC
TEMPERATURE (°C)
FIGURE 3. OUTPUT SOURCE RESISTANCE AS A FUNCTION
OF TEMPERATURE
FIGURE 4. POWER CONVERSION EFFICIENCY AS A
FUNCTION OF OSC. FREQUENCY
10K
20
18
16
14
12
10
8
1K
100
V+ = 5V
A
V+ = +5V
T
= 25°C
6
-50
10
1.0
-25
0
25
50
75
100
125
10
100
(pF)
1000
10K
C
TEMPERATURE (°C)
OSC
FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION
OF EXTERNAL OSC. CAPACITANCE
FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A
FUNCTION OF TEMPERATURE
5
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
T
= 25°C
A
4
3
+
P
EFF
V+ = +5V
I
2
1
0
-1
-2
-3
-4
-5
T
= 25°C
= +5V
A
+
V
SLOPE 55Ω
20 30
LOAD CURRENT I (mA)
0
10
20
30
40
50
60
0
10
40
50
L
60
70
80
LOAD CURRENT I (mA)
L
FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT
CURRENT
FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD
CURRENT
FN3072.7
5
October 10, 2005
ICL7660, ICL7660A
Typical Performance Curves (Test Circuit of Figure 11) (Continued)
+2
+1
0
100
90
80
70
60
50
40
30
20
10
0
20.0
18.0
16.0
14.0
12.0
10.0
8.0
T
= 25°C
A
V+ = 2V
I+
P
EFF
6.0
-1
-2
4.0
T
= 25°C
SLOPE 150Ω
A
2.0
V+ = 2V
4.5 6.0
LOAD CURRENT I (mA)
0
0
1.5
3.0
7.5
9.0
0
1
2
3
4
5
6
7
8
LOAD CURRENT I (mA)
L
L
FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT
CURRENT
FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD
CURRENT
NOTE:
6. These curves include in the supply current that current fed directly into the load R from the V+ (See Figure 11). Thus, approximately half the
L
supply current goes directly to the positive side of the load, and the other half, through the ICL7660/ICL7660A, to the negative side of the load.
Ideally, V
∼ 2V , I ∼ 2I , so V x I ∼ V
x I .
OUT L
OUT
IN
S
L
IN
S
I
V+
S
(+5V)
1
8
7
6
5
2
3
4
I
ICL7660
L
C
10µF
+
1
ICL7660A
-
R
L
C
OSC
(NOTE)
-V
OUT
-
+
C
2
10µF
NOTE: For large values of C
(>1000pF) the values of C and C2 should be increased to 100µF.
OSC
1
FIGURE 11. ICL7660, ICL7660A TEST CIRCUIT
In the ICL7660 and ICL7660A, the 4 switches of Figure 12
are MOS power switches; S is a P-Channel device and S ,
Detailed Description
1
2
The ICL7660 and ICL7660A contain all the necessary
circuitry to complete a negative voltage converter, with the
exception of 2 external capacitors which may be inexpensive
10µF polarized electrolytic types. The mode of operation of
the device may be best understood by considering Figure
12, which shows an idealized negative voltage converter.
S and S are N-Channel devices. The main difficulty with
3
4
this approach is that in integrating the switches, the
substrates of S and S must always remain reverse biased
3
4
with respect to their sources, but not so much as to degrade
their “ON” resistances. In addition, at circuit start-up, and
under output short circuit conditions (V
= V+), the output
OUT
Capacitor C is charged to a voltage, V+, for the half cycle
1
voltage must be sensed and the substrate bias adjusted
accordingly. Failure to accomplish this would result in high
power losses and probable device latchup.
when switches S and S are closed. (Note: Switches S
1
3
2
and S are open during this half cycle.) During the second
4
half cycle of operation, switches S and S are closed, with
2
4
S and S open, thereby shifting capacitor C negatively by
This problem is eliminated in the ICL7660 and ICL7660A by a
1
3
1
V+ volts. Charge is then transferred from C to C such that
logic network which senses the output voltage (V
) together
1
2
OUT
the voltage on C is exactly V+, assuming ideal switches and
2
with the level translators, and switches the substrates of S and
3
no load on C . The ICL7660 approaches this ideal situation
2
S to the correct level to maintain necessary reverse bias.
4
more closely than existing non-mechanical circuits.
FN3072.7
6
October 10, 2005
ICL7660, ICL7660A
The voltage regulator portion of the ICL7660 and ICL7660A is
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
an integral part of the anti-latchup circuitry, however its inherent
voltage drop can degrade operation at low voltages. Therefore,
to improve low voltage operation the “LV” pin should be
connected to GROUND, disabling the regulator. For supply
voltages greater than 3.5V the LV terminal must be left open to
insure latchup proof operation, and prevent device damage.
1
2
2
E = / C (V - V )
2
2
1
1
where V and V are the voltages on C during the pump and
1
2
1
1
transfer cycles. If the impedances of C and C are relatively
2
high at the pump frequency (refer to Figure 12) compared to
the value of R , there will be a substantial difference in the
8
S
2
S
1
2
L
V
IN
voltages V and V . Therefore it is not only desirable to make
1
2
C
C as large as possible to eliminate output voltage ripple, but
1
2
3
3
5
also to employ a correspondingly large value for C in order to
1
achieve maximum efficiency of operation.
C
2
S
S
4
3
Do’s And Don’ts
1. Do not exceed maximum supply voltages.
V
= -V
IN
OUT
2. Do not connect LV terminal to GROUND for supply
7
voltages greater than 3.5V.
FIGURE 12. IDEALIZED NEGATIVE VOLTAGE CONVERTER
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5V for extended periods, however,
transient conditions including start-up are okay.
Theoretical Power Efficiency
Cons iderations
4. When using polarized capacitors, the + terminal of C
1
must be connected to pin 2 of the ICL7660 and ICL7660A
In theory a voltage converter can approach 100% efficiency
if certain conditions are met.
and the + terminal of C must be connected to GROUND.
2
5. If the voltage supply driving the ICL7660 and ICL7660A
has a large source impedance (25Ω - 30Ω), then a 2.2µF
capacitor from pin 8 to ground may be required to limit
rate of rise of input voltage to less than 2V/µs.
1. The driver circuitry consumes minimal power.
2. The output switches have extremely low ON resistance
and virtually no offset.
6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions. A 1N914 or similar diode placed
3. The impedances of the pump and reservoir capacitors
are negligible at the pump frequency.
The ICL7660 and ICL7660A approach these conditions for
negative voltage conversion if large values of C and C
in parallel with C will prevent the device from latching up
2
under these conditions. (Anode pin 5, Cathode pin 3).
1
2
are used.
V+
1
2
3
4
8
7
6
5
R
O
V
OUT
ICL7660
ICL7660A
+
10µF
-
-
V+
+
V
= -V+
OUT
-
10µF
+
FIGURE 13A. CONFIGURATION
FIGURE 13B. THEVENIN EQUIVALENT
FIGURE 13. SIMPLE NEGATIVE CONVERTER
FN3072.7
7
October 10, 2005
ICL7660, ICL7660A
t
t
1
2
B
0
V
A
-(V+)
FIGURE 14. OUTPUT RIPPLE
V+
1
2
3
4
8
7
6
ICL7660
ICL7660A
“1”
1
2
8
7
6
5
C
1
R
L
ICL7660
5
ICL7660A
“n”
C
3
4
1
-
+
C
2
FIGURE 15. PARALLELING DEVICES
V+
1
8
ICL7660
2
3
4
7
6
5
1
2
3
4
8
ICL7660A
“1”
+
10µF
-
7
6
5
ICL7660
ICL7660A
“n”
+
10µF
-
V
= -nV+
OUT
-
10µF
-
+
10µF
+
FIGURE 16. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE
2(R
R ≅
O
+ R
SW3
+ ESR ) +
C1
Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the ICL7660
and ICL7660A for generation of negative supply voltages.
Figure 13 shows typical connections to provide a negative
supply negative (GND) for supply voltages below 3.5V.
SW1
1
+ ESR
C2
(f
) (C1)
PUMP
f
OSC
(f
=
, R = MOSFET switch resistance)
SWX
PUMP
2
Combining the four R
terms as R , we see that:
SW
SWX
1
R
≅
2 (R ) +
+ 4 (ESR ) + ESR
C1 C2
SW
O
(f
) (C1)
PUMP
The output characteristics of the circuit in Figure 13A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 13B. The voltage source has
RSW, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance
a value of -V+. The output impedance (R ) is a function of
O
graphs), typically 23Ω at 25°C and 5V. Careful selection of
the ON resistance of the internal MOS switches (shown in
C and C will reduce the remaining terms, minimizing the
1
2
Figure 12), the switching frequency, the value of C and C ,
1
2
output impedance. High value capacitors will reduce the
1/(f • C ) component, and low ESR capacitors will
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for R is:
PUMP
1
O
lower the ESR term. Increasing the oscillator frequency will
reduce the 1/(f
• C1) term, but may have the side effect
2(R
2(R
+ R
+ R
+ ESR ) +
C1
+ ESR ) +
R
≅
PUMP
SW1
SW2
SW3
SW4
O
of a net increase in output impedance when C > 10µF and
1
C1
there is no longer enough time to fully charge the capacitors
FN3072.7
8
October 10, 2005
ICL7660, ICL7660A
every cycle. In a typical application where f
= 10kHz and
Cascading Devices
OSC
C = C = C = 10µF:
1
2
The ICL7660 and ICL7660A may be cascaded as shown to
produced larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
1
2 (23) +
≅
+ 4 (ESR ) + ESR
C1 C2
R
O
3
-5
(5 • 10 ) (10
)
R
≅ 46 + 20 + 5 (ESR )
C
O
V
= -n (V ),
IN
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
OUT
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660
potentially swamp out a low 1/(f
• C ) term, rendering an
PUMP
1
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10Ω.
and ICL7660A R
values.
OUT
1
Changing the ICL7660/ICL7660A Oscillator
Frequency
2 (23) +
≅
+ 4 (ESR ) + ESR
C1 C2
R
O
3
5
(5 • 10 ) (10- )
It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an
external clock, as shown in Figure 17. In order to prevent
possible device latchup, a 1kΩ resistor must be used in
series with the clock output. In a situation where the
designer has generated the external clock frequency using
TTL logic, the addition of a 10kΩ pullup resistor to V+ supply
R
≅ 46 + 20 + 5 (ESR )
C
O/
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f
• C ) term, rendering an
PUMP
1
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10Ω.
Output Ripple
is required. Note that the pump frequency with external
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 14. Segment A is the voltage drop across the ESR of
1
clocking, as with internal clocking, will be / of the clock
2
frequency. Output transitions occur on the positive-going
edge of the clock.
C at the instant it goes from being charged by C (current
2
1
flow into C ) to being discharged through the load (current
V+
V+
2
flowing out of C ). The magnitude of this current change is
2
1
2
3
4
8
7
6
5
2• I
, hence the total drop is 2• I
• eSR V. Segment
OUT
OUT
C2
1kΩ
CMOS
GATE
B is the voltage change across C during time t , the half of
2
2
ICL7660
+
ICL7660A
the cycle when C supplies current to the load. The drop at B
10µF
2
-
is l
• t2/C V. The peak-to-peak ripple voltage is the sum
2
OUT
V
OUT
-
of these voltage drops:
10µF
+
1
V
RIPPLE
≅
2 (f
) (C2)
PUMP
+ 2 (ESR
)
I
OUT
C2
FIGURE 17. EXTERNAL CLOCKING
[
]
Again, a low ESR capacitor will reset in a higher
performance output.
It is also possible to increase the conversion efficiency of the
ICL7660 and ICL7660A at low load levels by lowering the
oscillator frequency. This reduces the switching losses, and is
shown in Figure 18. However, lowering the oscillator
frequency will cause an undesirable increase in the
Paralleling Devices
Any number of ICL7660 and ICL7660A voltage converters
may be paralleled to reduce output resistance. The reservoir
impedance of the pump (C ) and reservoir (C ) capacitors;
1
2
capacitor, C , serves all devices while each device requires
2
this is overcome by increasing the values of C and C by the
1
2
its own pump capacitor, C . The resultant output resistance
1
same factor that the frequency has been reduced. For
example, the addition of a 100pF capacitor between pin 7
(OSC) and V+ will lower the oscillator frequency to 1kHz from
its nominal frequency of 10kHz (a multiple of 10), and thereby
would be approximately:
R
(of ICL7660/ICL7660A)
OUT
R
=
OUT
n (number of devices)
necessitate a corresponding increase in the value of C and
1
C (from 10µF to 100µF).
2
FN3072.7
9
October 10, 2005
ICL7660, ICL7660A
V+
V+
V
=
- O(nUVT - V
)
FDX
IN
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
C
OSC
-
+
ICL7660
ICL7660
C
3
D
+
-
1
ICL7660A
+
-
C
ICL7660A
1
C
1
V
OUT
-
+
V
= (2V+) -
C
OUT
FD1
2
D
2
(V
) - (V
)
FD2
+
-
+
C
C
4
2
FIGURE 18. LOWERING OSCILLATOR FREQUENCY
-
Positive Voltage Doubling
FIGURE 20. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER
The ICL7660 and ICL7660A may be employed to achieve
positive voltage doubling using the circuit shown in Figure
19. In this application, the pump inverter switches of the
Voltage Splitting
The bidirectional characteristics can also be used to split a
ICL7660 and ICL7660A are used to charge C to a voltage
1
higher supply in half, as shown in Figure 21. The combined
load will be evenly shared between the two sides. Because
the switches share the load in parallel, the output impedance
is much lower than in the standard circuits, and higher
currents can be drawn from the device. By using this circuit,
and then the circuit of Figure 16, +15V can be converted (via
+7.5, and -7.5) to a nominal -15V, although with rather high
series output resistance (~250Ω).
level of V+ -V (where V+ is the supply voltage and V is the
F
F
forward voltage drop of diode D ). On the transfer cycle, the
1
voltage on C plus the supply voltage (V+) is applied through
1
diode D to capacitor C . The voltage thus created on C
2
2
2
becomes (2V+) - (2VF) or twice the supply voltage minus the
combined forward voltage drops of diodes D and D .
1
2
The source impedance of the output (V
) will depend on
OUT
the output current, but for V+ = 5V and an output current of
10mA it will be approximately 60Ω.
V+
+
V+
50µF
R
L1
1
2
3
4
8
7
6
5
-
1
2
3
4
8
7
6
5
D
1
2
ICL7660
V+ - V-
2
V
=
OUT
ICL7660A
V
=
ICL7660
OUT
+
ICL7660A
D
(2V+) - (2V )
F
50µF
R
-
L2
+
-
+
-
+
C
C
2
1
50µF
-
V -
FIGURE 19. POSITIVE VOLT DOUBLER
FIGURE 21. SPLITTING A SUPPLY IN HALF
Combined Negative Voltage Conversion
and Positive Supply Doubling
Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7660 and
ICL7660A can be a problem, particularly if the load current
varies substantially. The circuit of Figure 22 can be used to
overcome this by controlling the input voltage, via an ICL7611
low-power CMOS op amp, in such a way as to maintain a
nearly constant output voltage. Direct feedback is inadvisable,
since the ICL7660s and ICL7660As output does not respond
instantaneously to change in input, but only after the switching
delay. The circuit shown supplies enough delay to
Figure 20 combines the functions shown in Figures 13 and
Figure 19 to provide negative voltage conversion and
positive voltage doubling simultaneously. This approach
would be, for example, suitable for generating +9V and -5V
from an existing +5V supply. In this instance capacitors C
1
and C perform the pump and reservoir functions
3
respectively for the generation of the negative voltage, while
capacitors C and C are pump and reservoir respectively
2
4
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will be
somewhat higher due to the finite impedance of the common
charge pump driver at pin 2 of the device.
accommodate the ICL7660 and ICL7660A, while maintaining
adequate feedback. An increase in pump and storage
capacitors is desirable, and the values shown provides an
output impedance of less than 5Ω to a load of 10mA.
FN3072.7
10
October 10, 2005
ICL7660, ICL7660A
Other Applications
50K
+8V
Further information on the operation and use of the ICL7660
and ICL7660A may be found in AN051 “Principals and
Applications of the ICL7660 and ICL7660A CMOS Voltage
Converter”.
56K
50K
+8V
-
+
100Ω
10µF
-
ICL7611
+
100K
1
2
3
4
8
7
6
5
ICL7660
+
ICL8069
ICL7660A
100µF
-
V
OUT
-
800K
250K
VOLTAGE
ADJUST
100µF
+
FIGURE 22. REGULATING THE OUTPUT VOLTAGE
+5V LOGIC SUPPLY
12
11
TTL DATA
INPUT
16
4
1
3
RS232
DATA
+5V
-5V
OUTPUT
15
1
2
3
4
8
7
6
5
IH5142
13
ICL7660
+
10µF
-
ICL7660A
14
-
+
10µF
FIGURE 23. RS232 LEVELS FROM A SINGLE 5V SUPPLY
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3072.7
11
October 10, 2005
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