ICL7660, ICL7660A
every cycle. In a typical application where f
OSC
= 10kHz and
Cascading Devices
C = C = C = 10µF:
1
2
The ICL7660 and ICL7660A may be cascaded as shown to
produced larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
1
3
2 (23) +
+ 4 (ESR ) + ESR
C1
R
C2
O
-5
(5 • 10 ) (10
)
R
46 + 20 + 5 (ESR )
C
O
V
= -n (V ),
IN
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
OUT
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660
potentially swamp out a low 1/(f
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10Ω.
• C ) term, rendering an
PUMP
1
and ICL7660A R
OUT
values.
1
Changing the ICL7660/ICL7660A Oscillator
Frequency
2 (23) +
+ 4 (ESR ) + ESR
C1
R
C2
O
3
5
(5 • 10 ) (10- )
It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an
external clock, as shown in Figure 17. In order to prevent
possible device latchup, a 1kΩ resistor must be used in
series with the clock output. In a situation where the
designer has generated the external clock frequency using
TTL logic, the addition of a 10kΩ pullup resistor to V+ supply
R
46 + 20 + 5 (ESR )
C
O/
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10Ω.
• C ) term, rendering an
PUMP
1
Output Ripple
is required. Note that the pump frequency with external
1
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 14. Segment A is the voltage drop across the ESR of
clocking, as with internal clocking, will be / of the clock
2
frequency. Output transitions occur on the positive-going
edge of the clock.
C at the instant it goes from being charged by C (current
2
1
flow into C ) to being discharged through the load (current
V+
V+
2
flowing out of C ). The magnitude of this current change is
2
1
2
3
4
8
7
6
5
2• I
, hence the total drop is 2• I
OUT
• eSR V. Segment
C2
OUT
B is the voltage change across C during time t , the half of
1kΩ
CMOS
GATE
2
2
ICL7660
ICL7660A
+
the cycle when C supplies current to the load. The drop at
10µF
2
-
B is l
• t2/C V. The peak-to-peak ripple voltage is the
OUT
2
V
OUT
-
sum of these voltage drops:
1
10µF
+
V
RIPPLE
2 (f
) (C2)
PUMP
+ 2 (ESR
)
I
OUT
C2
FIGURE 17. EXTERNAL CLOCKING
[
]
It is also possible to increase the conversion efficiency of the
ICL7660 and ICL7660A at low load levels by lowering the
oscillator frequency. This reduces the switching losses, and is
shown in Figure 18. However, lowering the oscillator
frequency will cause an undesirable increase in the
impedance of the pump (C ) and reservoir (C ) capacitors;
this is overcome by increasing the values of C and C by the
same factor that the frequency has been reduced. For
example, the addition of a 100pF capacitor between pin 7
(OSC) and V+ will lower the oscillator frequency to 1kHz from
its nominal frequency of 10kHz (a multiple of 10), and thereby
Again, a low ESR capacitor will reset in a higher
performance output.
Paralleling Devices
Any number of ICL7660 and ICL7660A voltage converters
may be paralleled to reduce output resistance. The reservoir
1
2
1
2
capacitor, C , serves all devices while each device requires
2
its own pump capacitor, C . The resultant output resistance
1
would be approximately:
R
(of ICL7660/ICL7660A)
OUT
R
=
OUT
necessitate a corresponding increase in the value of C and
C (from 10µF to 100µF).
1
n (number of devices)
2
3-33
意法半导体中国市场突围：双供应链战略铸就 “芯” 蓝图
小米首款 AI 眼镜正式亮相，芯片市场迎来哪些新机遇？
剖析汽车安全气囊控制单元：从拆解看核心技术
AI 时代算力困局待解，晶圆级芯片潜力无限
概述
数据手册
