ICM7211LPL_技术文档

ICM7211, ICM7212

4-Digit, ICM7211 (LCD) and

ICM7212 (LED) Display Drivers

August 1997

Features ICM7211 (LCD)

Description

• Four Digit Non-Multiplexed 7 Segment LCD Display The ICM7211 (LCD) and ICM7212 (LED) devices constitute

Outputs with Backplane Driver

a family of non-multiplexed four-digit seven-segment CMOS

display decoder-drivers.

• Complete Onboard RC Oscillator to Generate Backplane

Frequency

The ICM7211 devices are conﬁgured to drive conventional

LCD displays by providing a complete RC oscillator, divider

chain, backplane driver, and 28 segment outputs.

• Backplane Input/Output Allows Simple Synchronization

of Slave-Devices to a Master

The ICM7212 devices are conﬁgured to drive common-

anode LED displays, providing 28 current-controlled, low

leakage, open-drain N-Channel outputs. These devices

provide a brightness input, which may be used at normal

logic levels as a display enable, or with a potentiometer as a

continuous display brightness control.

• ICM7211 Devices Provide Separate Digit Select Inputs to

Accept Multiplexed BCD Input (Pinout and Functionally

Compatible with Siliconix DF411)

• ICM7211M Devices Provide Data and Digit Address

Latches Controlled by Chip Select Inputs to Provide a

Direct High Speed Processor Interface

These devices are available with multiplexed or microproces-

sor input conﬁgurations. The multiplexed versions provide four

data inputs and four Digit Select inputs. This conﬁguration is

suitable for interfacing with multiplexed BCD or binary output

devices, such as the ICM7217, ICM7226, and ICL7135. The

microprocessor versions provide data input latches and Digit

Address latches under control of high-speed Chip Select

inputs. These devices simplify the task of implementing a

cost-effective alphanumeric seven-segment display for micro-

processor systems, without requiring extensive ROM or CPU

time for decoding and display updating.

• ICM7211 Decodes Binary to Hexadecimal; ICM7211A

Decodes Binary to Code B (0-9, Dash, E, H, L, P, Blank)

• ICM7211A Available in Surface Mount Package

Features ICM7212AM (LED)

• 28 Current-Limited Segment Outputs Provide 4-Digit

Non-Multiplexed Direct LED Drive at >5mA Per Segment

• Brightness Input Allows Direct Control of LED

Segment Current with a Single Potentiometer or

Digitally as a Display Enable

The standard devices will provide two different decoder

conﬁgurations. The basic device will decode the four bit

binary inputs into a seven-segment alphanumeric hexadeci-

mal output. The “A” versions will provide the “Code B” output

code, i.e., 0-9, dash, E, H, L, P, blank. Either device will cor-

rectly decode true BCD to seven-segment decimal outputs.

• ICM7212AM Device Provides Same Input Conﬁguration

and Output Decoding Options as the ICM7211AM

Ordering Information

DISPLAY

TYPE

DISPLAY

DECODING

INPUT

INTERFACING

DISPLAY DRIVE

TYPE

TEMP.

RANGE ( C)

o

PART NUMBER

ICM7211lPL

PACKAGE

PKG. NO.

E40.6

LCD

LED

Hexadecimal

Code B

Multiplexed

Direct Drive

Common Anode

-40 to 85 40 Ld PDIP

-40 to 85 44 Ld MQFP

-40 to 85 40 Ld PDIP

ICM7211MlPL

ICM7211AlPL

Microprocessor

Multiplexed

E40.6

ICM7211AMlPL

ICM7211AlM44

ICM7211AMlM44

ICM7212AMlPL

Code B

Microprocessor

Multiplexed

E40.6

Code B

Q44.10x10

E40.6

Code B

Microprocessor

Code B

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3158.1

9-6

ICM7211, ICM7212

Pinouts

ICM7211, ICM7211A

(PDIP)

ICM7211M, ICM7211AM

(PDIP)

TOP VIEW

V

1

2

3

4

5

6

7

8

9

40 d1

V

1

2

3

4

5

6

7

8

9

40

39

38

37

d1

c1

b1

a1

DD

e1

g1

f1

39 c1

38 b1

37 a1

36 OSC

e1

g1

f1

BP

a2

b2

c2

d2

BP

a2

b2

c2

d2

36 OSC

35

V

SS

34 D4

33 D3

32 D2

31 D1

30 B3

29 B2

28 B1

27 B0

26 f4

34 CHIP SELECT 2

33 CHIP SELECT 1

32 DIGIT ADRESS BIT 2

31 DIGIT ADRESS BIT 1

30 B3

DIGIT

SELECT

INPUTS

e2 10

g2 11

f2 12

a3 13

b3 14

c3 15

d3 16

e3 17

g3 18

f3 19

a4 20

e2 10

g2 11

f2 12

a3 13

b3 14

c3 15

d3 16

e3 17

g3 18

f3 19

a4 20

29 B2

DATA

INPUTS

28 B1

27 B0

26 f4

25 g4

24 e4

23 d4

22 c4

21 b4

25 g4

24 e4

23 d4

22 c4

21 b4

ICM7212AM

(PDIP)

TOP VIEW

V

1

2

3

4

5

6

7

8

9

40

39

38

37

36

35

d1

c1

b1

a1

DD

e1

g1

f1

BRT

a2

V

SS

b2

34 CHIP SELECT 2

33 CHIP SELECT 1

32 DIGIT ADRESS BIT 2

31 DIGIT ADRESS BIT 1

30 B3

c2

d2

e2 10

g2 11

f2 12

a3 13

b3 14

c3 15

d3 16

e3 17

g3 18

f3 19

a4 20

29 B2

DATA

INPUTS

28 B1

27 B0

26 f4

25 g4

24 e4

23 d4

22 c4

21 b4

9-7

ICM7211, ICM7212

Pinouts (Continued)

ICM7211A

(MQFP)

TOP VIEW

44 43 42 41 40 39 38 37 36 35 34

33

1

V

SS

a2

b2

c2

d2

e2

NC

g2

f2

2

D4

D3

D2

D1

NC

B3

B2

B1

B0

f4

32

31

30

29

DIGIT

SELECT

INPUTS

3

4

5

6

7

8

9

28

27

26

25

24

23

DATA

INPUTS

d3

b3

c3

10

11

12 13 14 15 16 17 18 19 20 21 22

ICM7211AM

(MQFP)

TOP VIEW

44 43 42 41 40 39 38 37 36 35 34

V

a2

b2

c2

d2

e2

NC

g2

f2

1

SS

33

CHIP SELECT 2

CHIP SELECT 1

DIGITAL ADRESS BIT 2

DIGITAL ADRESS BIT 1

NC

2

32

31

30

29

3

4

5

6

7

8

9

28

27

26

25

24

23

B3

B2

DATA

INPUTS

B1

d3

b3

c3

10

11

B0

f4

12 13 14 15 16 17 18 19 20 21 22

9-8

ICM7211, ICM7212

Functional Block Diagrams

ICM7211A

D3

D4

D2

D1

SEGMENT OUTPUTS

7 WIDE DRIVER

7 WIDE LATCH EN

PROGRAMMABLE

4 TO 7 DECODER

PROGRAMMABLE

4 TO 7 DECODER

PROGRAMMABLE

4 TO 7 DECODER

PROGRAMMABLE

4 TO 7 DECODER

DATA

INPUTS

DIGIT

SELECT

INPUTS

BLACKPLANE

DRIVER

OSCILLATOR

19kHz

FREE-RUNNING

÷

128

OSCILLATOR

INPUT

BP INPUT/OUTPUT

ENABLE

DIRECTOR

ICM7211AM

D4

D3

D2

D1

SEGMENT OUTPUTS

7 WIDE DRIVER

7 WIDE LATCH EN

PROGRAMMABLE

4 TO 7 DECODER

PROGRAMMABLE

4 TO 7 DECODER

PROGRAMMABLE

4 TO 7 DECODER

PROGRAMMABLE

4 TO 7 DECODER

4-BIT

LATCH

DATA

INPUTS

ENABLE

2-BIT

DIGIT

ADRESS

INPUT

2-BIT

LATCH

2 TO 4

DECODER

ENABLE

CHIP

SELECT 1

CHIP

ONE

SHOT

BLACKPLANE

DRIVER

OSCILLATOR

19kHz

FREE-RUNNING

SELECT 2

÷

128

OSCILLATOR

INPUT

BP INPUT/OUTPUT

ENABLE

DIRECTOR

9-9

ICM7211, ICM7212

Functional Block Diagrams (Continued)

ICM7212AM

D4

D3

D2

D1

SEGMENT OUTPUTS

7 WIDE DRIVER

7 WIDE LATCH EN

PROGRAMMABLE

4 TO 7 DECODER

PROGRAMMABLE

4 TO 7 DECODER

PROGRAMMABLE

4 TO 7 DECODER

PROGRAMMABLE

4 TO 7 DECODER

4-BIT

LATCH

DATA

INPUTS

ENABLE

2-BIT

DIGIT

ADRESS

INPUT

2-BIT

LATCH

2 TO 4

DECODER

ENABLE

CHIP

SELECT 1

CHIP

ONE

SHOT

SELECT 2

9-10

ICM7211, ICM7212

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage (V

DD

- V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V

SS

Thermal Resistance (Typical, Note 2)

θ_JA( C/W)

Input Voltage (Any Terminal) (Note 1) . . V - 0.3V to V , + 0.3V

SS DD

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

60

80

o

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C

Operating Conditions

o

Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C

o

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C

o

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300 C

(MQFP - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTES:

1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than V

DD

or less than V

may

SS

cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same

power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7211

and ICM7212 be turned on ﬁrst.

2. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Electrical Speciﬁcations

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

o

ICM7211 CHARACTERISTICS (LCD) V

= 5V ±10%, T = 25 C, V = 0V Unless Otherwise Specified

A SS

DD

- V ), V

SUPPLY

Operating Supply Voltage Range (V

3

-

5

6

V

µA

µs

DD

SS

Operating Current, I

Test circuit, Display blank

Pin 36

10

50

DD

Oscillator Input Current, I

±2

±10

OSCI

Segment Rise/Fall Time, t , t

C

= 200pF

0.5

1.5

19

-

r

f

L

Backplane Rise/Fall Time, t , t

= 5000pF

µs

r

f

Oscillator Frequency, f

OSC

Pin 36 Floating

kHz

Hz

Backplane Frequency, f

150

BP

ICM7212 CHARACTERISTICS (Common Anode LED)

Operating Supply Voltage Range (V - V ), V

SUPPLY

4

-

5

10

6

50

-

V

DD

STBY

SS

Operating Current Display Off, I

Operating Current, I

Pin 5 (Brightness), Pins 27-34 V

µA

mA

µA

mA

SS

Pin 5 at V , Display all 8’s

DD

-

200

±0.01

8

DD

Segment Leakage Current, I

Segment Off

-

±1

-

SLK

Segment On Current, I

Segment On, V = +3V

O

5

SEG

INPUT CHARACTERISTICS (ICM7211 and ICM7212)

Logical “1” Input Voltage, V

Logical “0” Input Voltage, V

4

-

V

IH

IL

1

V

Input Leakage Current, I

ILK

Pins 27-34

-

±0.01

5

±1

µA

pF

µA

pF

Input Capacitance, C

lN

-

BP/Brightness Input Leakage, I

Measured at Pin 5 with Pin 36 at V

All Devices

-

±0.01

200

±1

BPLK

SS

BP/Brightness Input Capacitance, C

-

BPI

AC CHARACTERISTICS - MULTIPLEXED INPUT CONFIGURATION

Digit Select Active Pulse Width, t Refer to Timing Diagrams

1

-

µs

ns

µs

WH

Data Setup Time, t

500

200

2

DS

Data Hold Time, t

DH

Inter-Digit Select Time, t

IDS

AC CHARACTERISTICS - MICROPROCESSOR INTERFACE

Chip Select Active Pulse Width, t

Other Chip Select Either Held Active,

or Both Driven Together

200

-

ns

WL

Data Setup Time, t

100

10

2

-

0

-

ns

µs

DS

Data Hold Time, t

DH

Inter-Chip Select Time, t

ICS

9-11

ICM7211, ICM7212

Input Deﬁnitions In this table, V and V are considered to be normal operating input logic levels. Actual input low and high levels are

DD

SS

speciﬁed under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply.

INPUT

TERMINAL

CONDITIONS

FUNCTION

B0

B1

B2

B3

27

V

= Logical One

= Logical Zero

Ones (Least Significant)

Twos

DD

SS

28

29

30

36

V

= Logical One

= Logical Zero

DD

SS

Data Input Bits

V

= Logical One

= Logical Zero

Fours

DD

SS

V

= Logical One

= Logical Zero

Eights (Most Significant)

DD

SS

OSC (LCD Devices

Only)

Floating or with External Oscillator Input

Capacitor to V

DD

V

Disables BP output devices, allowing segments to be synchronized to

an external signal input at the BP terminal (Pin 5).

SS

ICM7211 Multiplexed-Binary Input Conﬁguration

INPUT

D1

TERMINAL

CONDITIONS

FUNCTION

D1 Digit Select (Least Significant)

D2 Digit Select

31

32

33

34

V

= Inactive

= Active

DD

SS

D2

D3

D3 Digit Select

D4

D4 Digit Select (Most Significant)

ICM7211M/ICM7212M Microprocessor Interface Input Conﬁguration

INPUT

DESCRIPTION

TERMINAL

CONDITIONS

FUNCTION

DA1

Digit Address

Bit 1 (LSB)

31

V

= Logical One

= Logical Zero

DA1 and DA2 serve as a 2-bit Digit Address Input

DA2, DA1 = 00 selects D4

DD

SS

DA2, DA1 = 01 selects D3

DA2, DA1 = 10 selects D2

DA2, DA1 = 11 selects D1

DA2

Digit Address

Bit 2 (MSB)

32

V

= Logical One

= Logical Zero

DD

SS

CS1

CS2

Chip Select 1

Chip Select 2

33

34

V

= Inactive

= Active

When both CS1 and CS2 are taken low, the data at the Data

and Digit Select code inputs are written into the input latches.

On the rising edge of either Chip Select, the data is decoded

and written into the output latches.

DD

SS

V

= Inactive

= Active

DD

SS

Timing Diagrams

t

IDS

WH

DIGIT SELECT

D

N-1

t

DH

DIGIT SELECT

D

N

DATA VALID

D

N-1

N

t

DS

FIGURE 1. MULTIPLEXED INPUT

CS1

(CS2)

t

ICS

WI

CS2

(CS1)

t

DH

t

DS

DATA AND

DIGIT

ADDRESS

= DON’T CARE

FIGURE 2. MICROPROCESSOR INTERFACE INPUT

9-12

ICM7211, ICM7212

Typical Performance Curves

30

180

150

120

90

o

LCD DEVICES, T = 25 C

LCD DEVICES, TEST CIRCUIT

A

DISPLAY BLANK, PIN 36 OPEN

25

C

= 0pF

OSC

(PIN 36 OPEN)

o

T

= -20 C

A

20

15

10

5

o

T

= 25 C

C

= 22pF

A

OSC

60

o

= 70 C

T

A

C

= 220pF

OSC

30

0

1

2

3

4

5

6

1

2

3

4

5

6

7

V

(V)

V

(V)

SUPP

FIGURE 3. ICM7211 OPERATING SUPPLY CURRENT AS A

FUNCTION OF SUPPLY VOLTAGE

FIGURE 4. ICM7211 BACKPLANE FREQUENCY AS A

FUNCTION OF SUPPLY VOLTAGE

15

12

o

PIN 5 AT V , T = 25 C

SEGMENT OUTPUT AT +3V

o

DD

A

T

= 25 C

A

10

8

V

= 6V

SUPP

= 5V

10

5

V

SUPP

6

V

= 4V

4

SUPP

2

0

1

2

3

4

5

6

0

1

2

3

4

5

6

V

(V)

VOLTAGE ON BRT PIN 5 (V)

O

FIGURE 5. ICM7212 LED SEGMENT CURRENT AS A

FUNCTION OF OUTPUT VOLTAGE

FIGURE 6. ICM7212 LED SEGMENT CURRENT AS A

FUNCTION OF BRIGHTNESS CONTROL VOLTAGE

1800

LED DEVICES, DISPLAY ALL EIGHTS

LED FORWARD VOLTAGE DROP

o

1500

1200

900

600

300

0

V

= 1.7V, PIN 5 AT V , T = 25 C

FLED

DD

A

4

5

6

V

(V)

SUPP

FIGURE 7. ICM7212 OPERATING POWER (LED DISPLAY) AS A FUNCTION OF SUPPLY VOLTAGE

9-13

ICM7211, ICM7212

Description Of Operation

OSCILLATOR

FREQUENCY

LCD Devices

128 CYCLES

BACKPLANE

INPUT/OUTPUT

The LCD devices in the family (ICM7211, ICM7211A,

ICM7211M, ICM7211AM) provide outputs suitable for driving

conventional four-digit, seven-segment LCD displays. These

devices include 28 individual segment drivers, backplane

driver, and a self-contained oscillator and divider chain to

generate the backplane frequency.

64 CYCLES

OFF

SEGMENTS

ON

SEGMENTS

The segment and backplane drivers each consist of a

CMOS inverter, with the N-Channel and P-Channel devices

ratioed to provide identical on resistances, and thus equal

rise and fall times. This eliminates any DC component, which

could arise from differing rise and fall times, and ensures

maximum display life.

FIGURE 8. DISPLAY WAVEFORMS

LED Devices

The LED device in the family (ICM7212AM) provides outputs

suitable for directly driving four-digit, seven-segment

common-anode LED displays. These devices include 28

individual segment drivers, each consisting of a low-leakage,

current-controlled, open-drain, N-Channel transistor.

The backplane output devices can be disabled by connect-

ing the OSCillator input (pin 36) to V . This allows the 28

SS

segment outputs to be synchronized directly to a signal input

at the BP terminal (pin 5). In this manner, several slave

devices may be cascaded to the backplane output of one

master device, or the backplane may be derived from an

external source. This allows the use of displays with charac-

ters in multiples of four and a single backplane. A slave

device represents a load of approximately 200pF (compara-

ble to one additional segment). Thus the limitation of the

number of devices that can be slaved to one master device

backplane driver is the additional load represented by the

larger backplane of displays of more than four digits. A good

rule of thumb to observe in order to minimize power con-

sumption is to keep the backplane rise and fall times less

than about 5µs. The backplane output driver should handle

the backplane to a display of 16 one-half inch characters. It

is recommended, if more than four devices are to be slaved

together, the backplane signal be derived externally and all

the ICM7211 devices be slaved to it. This external signal

should be capable of driving very large capacitive loads with

short (1 - 2µs) rise and fall times. The maximum frequency

for a backplane signal should be about 150Hz although this

may be too fast for optimum display response at lower dis-

play temperatures, depending on the display type.

The drain current of these transistors can be controlled by

varying the voltage at the BRtrighTness input (pin 5). The volt-

age at this pin is transferred to the gates of the output devices

for “on” segments, and thus directly modulates the transistor’s

“on” resistance. A brightness control can be easily imple-

mented with a single potentiometer controlling the voltage at

pin 5, connected as in Figure 9. The potentiometer should be

a high value (100kΩ to 1MΩ) to minimize power consumption,

which can be signiﬁcant when the display is off.

V

(LED ANODES)

DD

BRIGHTNESS

PIN 5

100kΩ TO 1MΩ

FIGURE 9. BRIGHTNESS CONTROL

The brightness input may also be operated digitally as a dis-

play enable; when high, the display is fully on, and low fully

off. The display brightness may also be controlled by varying

the duty cycle of a signal swinging between the two voltages

at the brightness input.

The onboard oscillator is designed to free run at approxi-

mately 19kHz at microampere current levels. The oscillator

frequency is divided by 128 to provide the backplane fre-

quency, which will be approximately 150Hz with the oscillator

free-running; the oscillator frequency may be reduced by Note that the LED device has two connections for V ; both

SS

connecting an external capacitor between the OSCillator ter- of these pins should be connected. The double connection is

minal and V

.

necessary to minimize effects of bond wire resistance with

the large total display currents possible.

DD

The oscillator may also be overdriven if desired, although care

must be taken to ensure that the backplane driver is not dis-

abled during the negative portion of the overdriving signal

(which could cause a DC component to the display). This can

be done by driving the OSCillator input between the positive

supply and a level out of the range where the backplane disable

When operating LED devices at higher temperatures and/or

higher supply voltages, the device power dissipation may

need to be reduced to prevent excessive chip temperatures.

o

The maximum power dissipation is 1W at 25 C, derated lin-

o

early above 35 C to 500mW at 70 C (-15mW/ C above

o

35 C). Power dissipation for the device is given by:

is sensed (about one ﬁfth of the supply voltage above V ).

SS

Another technique for overdriving the oscillator (with a signal

swinging the full supply) is to skew the duty cycle of the over-

driving signal such that the negative portion has a duration

shorter than about one microsecond. The backplane disable

sensing circuit will not respond to signals of this duration.

P = (V

SUPP

- V )

)(l

)(n

FLED SEG SEG

where V

FLED

is the LED forward voltage drop, I is

is the number of “on” segments.

SEG

segment current, and n

SEG

It is recommended that if the device is to be operated at

9-14

ICM7211, ICM7212

elevated temperatures the segment current be limited by use These devices are actually mask-programmable to provide

of the brightness input to keep power dissipation within the any 16 combinations of the seven segment outputs decoded

limits described above.

from the four input bits. For large quantity orders custom

decoder options can be arranged. Contact the factory for

details.

Input Conﬁgurations and Output Codes

The standard devices in the ICM7211 and ICM7212 family

accept a four-bit true binary (i.e., positive level = logical one)

input at pins 27 thru 30, least signiﬁcant bit at pin 27 ascend-

ing to the most signiﬁcant bit at pin 30. The ICM7211 and

ICM7211M devices decode this binary input into a seven-

segment alphanumeric hexadecimal output, while the

ICM7211A, ICM7211AM, and ICM7212AM decode the

binary input into seven-segment alphanumeric “Code B” out-

put, i.e., 0-9, dash, E, H, L, P, blank. These codes are shown

explicitly in Table 1. Either decoder option will correctly

decode true BCD to a seven-segment decimal output.

The ICM7211 and ICM7211A devices are designed to accept

multiplexed binary or BCD input. These devices provide four

separate digit lines (least signiﬁcant digit at pin 31 ascending

to most signiﬁcant digit at pin 34), each of which when taken

to a positive level decodes and stores in the output latches of

its respective digit the character corresponding to the data at

the input port, pins 27 through 30.

The ICM7211M, ICM7211AM, and ICM7212AM devices are

intended to accept data from a data bus under processor

control.

In these devices, the four data input bits and the two-bit digit

address (DA1 pin 31, DA2 pin 32) are written into input buffer

latches when both chip select inputs (CS1 pin 33, CS2 pin

34) are taken low. On the rising edge of either chip select

input, the content of the data input latches is decoded and

stored in the output latches of the digit selected by the con-

tents of the digit address latches.

TABLE 1. OUTPUT CODES

BlNARY

HEXADECIMAL

ICM7211

CODE B

ICM7211A

ICM7212AM

B3

0

1

B2

0

1

0

1

B1 BO

ICM7211M

An address of 00 writes into D4, DA2 = 0, DA1 = 1 writes into

D3, DA2 = 1, DA1 = 0 writes into D2, and 11 writes into D1.

The timing relationships for inputting data are shown in

Figure 2, and the chip select pulse widths and data setup and

hold times are speciﬁed under Operating Characteristics.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

a

f

b

g

e

c

d

FIGURE 10. SEGMENT ASSIGNMENT

BLANK

9-15

ICM7211, ICM7212

Test Circuit

V

SS

DD

+

-

1

2

V

40

39

38

37

DD

ICM7211AM

3

4

5

BP

OSC 36

6

V

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

SS

7

MICROPROCESSOR

VERSION

V

DD

8

DIGIT/CHIP

SELECT

INPUTS

9

EACH SEGMENT

OUTPUT TO

BACKPLANE

WITH A 200pF

CAPACITOR

MULTIPLEXED

VERSION

V

SS

10

11

12

13

14

15

16

17

18

19

20

DATA

INPUTS

V

DD

FIGURE 11.

Typical Applications

D8

D7

D6

D5

D4

D3

D2

D1

BACKPLANE

8-DIGIT

LCD DISPLAY

BACKPLANE

SLAVE

BACKPLANE

MASTER

28

+5V

V

DD

SS

DD

SS

SEGMENTS

HIGH ORDER

ICM7211A

SEGMENTS

LOW ORDER

ICM7211A

OSC

B3-B0

OSC

B3-B0

D4 D3 D2 D1 BP

4

BCD/BINARY

DATA

4

D8

D7

D6

D5

DIGIT

SELECTS

D4

D3

D2

D1

FIGURE 12. GANGED ICM7211’s DRIVING 8-DIGIT LCD DISPLAY

9-16

ICM7211, ICM7212

Typical Applications (Continued)

8 DIGIT

LCD DISPLAY

ICM7211M

HIGH ORDER DIGITS

ICM7211M

LOW ORDER DIGITS

+5V

2, 3, 4

6-26

+5V

1 V

DD

1 V

+5V

2, 3, 4

SEGMENTS 6-26

40 26

20

DD

35 V

P10 27

28

SEGMENTS

V

BP 5

DATA

B0-B3

CC DD

SS

36 OSC

DS1 DS2 CS1 CS2

27 28 29 30 31 32 33 34

35 V

SS

37-40

DATA

B0-B3

29

36 OSC

2 XTAL1

30

DS1 DS2 CS1 CS2

27 28 29 30 31 32 33 34

I/O

31

32

3 XTAL2

4 RESET

7 EA

33

P17 34

P20 21

22

23

24

35

NC

5 SS

80C48

µCOMPUTER

36

37

I/O

P27 38

DB0 12

13

1 TO

39 T1

6 INT

INPUT

14

15

16

17

18

DB7 19

ALE PSEN PROG WR RD

11 25 10

9

8

FIGURE 13. 80C48 MICROPROCESSOR INTERFACE

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

9-17


型号：	ICM7211LPL
厂家：	Intersil
描述：	4-Digit, ICM7211 (LCD) and ICM7212 (LED) Display Drivers 4位， ICM7211 （ LCD）和ICM7212 （ LED）显示驱动器显示驱动器信息通信管理 CD
文件：	总12页 (文件大小：86K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICM7211LPL [INTERSIL]

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