ID82C89 [INTERSIL]
CMOS Bus Arbiter; CMOS总线仲裁器
| 型号： | ID82C89 |
| 厂家： | 
Intersil |
| 描述： | CMOS Bus Arbiter |
| 文件： | 总15页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
82C89
CMOS Bus Arbiter
March 1997
Features
Description
• Pin Compatible with Bipolar 8289
The Intersil 82C89 Bus Arbiter is manufactured using a self-
aligned silicon gate CMOS process (Scaled SAJI IV). This cir-
cuit, along with the 82C88 bus controller, provides full bus arbi-
tration and control for multi-processor systems. The 82C89 is
typically used in medium to large 80C86 or 80C88 systems
where access to the bus by several processors must be coordi-
nated. The 82C89 also provides high output current and capac-
itive drive to eliminate the need for additional bus buffering.
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
• Provides Multi-Master System Bus Control and
Arbitration
• Provides Simple Interface with 82C88/8288 Bus
Controller
Static CMOS circuit design insures low operating power. The
advanced Intersil SAJI CMOS process results in perfor-
mance equal to or greater than existing equivalent products
at a significant power savings.
• Synchronizes 80C86/8086, 80C88/8088 Processors
with Multi-Master Bus
• Bipolar Drive Capability
• Four Operating Modes for Flexible System Configura- Ordering Information
tion
TEMPERATURE
RANGE
PKG.
NO.
• Low Power Operation
PART NUMBER
CP82C89
PACKAGE
o
o
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .1mA/MHz (Max)
20 Ld PDIP
0 C to +70 C
E20.3
o
o
IP82C89
-40 C to +85 C E20.3
o
o
CS82C89
20 Ld PLCC
0 C to +70 C
N20.35
• Operating Temperature Ranges
o
o
o
o
IS82C89
-40 C to +85 C N20.35
- C82C89 . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to +70 C
o
o
o
o
CD82C89
20 Ld
CERDIP
0 C to +70 C
F20.3
- I82C89 . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
o
o
o
o
ID82C89
-40 C to +85 C F20.3
- M82C89 . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
o
o
MD82C89/B
5962-8552801RA
MR82C89/B
-55 C to +125 C F20.3
SMD#
F20.3
o
o
20 Pad
CLCC
-55 C to +125 C J20.A
5962-85528012A
SMD#
J20.A
Pinouts
82C89 (CERDIP)
82C89 (PLCC, CLCC)
TOP VIEW
TOP VIEW
1
2
20
19
18
17
16
15
14
13
12
S2
IOB
V
CC
S1
3
2
1
20 19
3
SYSB/RESB
RESB
S0
18
S0
4
5
6
7
8
RESB
BCLK
INIT
4
CLK
17 CLK
5
BCLK
LOCK
CRQLCK
ANYRQST
AEN
16 LOCK
6
INIT
15
14
CRQLCK
BREQ
BPRO
7
BREQ
BPRO
ANYRQST
8
9
10 11 12 13
9
CBRQ
BPRN
10
11 BUSY
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2980.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19949-343
82C89
Functional Diagram
INIT
ARBITRATION
BCLK
BREQ
BPRN
BPRO
TM
MULTIBUS
MULTIBUS
INTERFACE
COMMAND
SIGNALS
S
S
S
2
1
0
80C86/
80C88
STATUS
STATUS
BUSY
CBRQ
DECODER
LOCK
CLK
CONTROL/
STRAPPING
OPTIONS
CRQLCK
RESB
ANYRQST
CONTROL
LOCAL
BUS
AEN
INTERFACE
SYSTEM
SIGNALS
IOB
SYSB/
RESB
+5V
GND
TM
MULTIBUS
IS AN INTEL CORP. TRADEMARK
Pin Description
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
V
20
V
: The +5V Power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for
CC
CC
decoupling.
GND
10
GROUND.
S0, S1, S2
1, 18-19
I
I
I
I
I
STATUS INPUT PINS: The status input pins from an 80C86, 80C88 or 8089 processor. The
82C89 decodes these pins to initiate bus request and surrender actions. (See Table 1).
CLK
LOCK
17
16
15
4
CLOCK: From the 82C84A or 82C85 clock chip and serves to establish when bus arbiter actions
are initiated.
LOCK: A processor generated signal which when activated (low) prevents the arbiter from surren-
dering the multi-master system bus to any other bus arbiter, regardless of its priority.
CRQLCK
RESB
COMMON REQUEST LOCK: An active low signal which prevents the arbiter from surrendering the
multi-master system bus to any other bus arbiter requesting the bus through the CBRQ input pin.
RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a
multi-master system bus and a Resident Bus. Strapped high, the multi-master system bus is re-
quested or surrendered as a function of the SYSB/RESB input pin. Strapped low, the SYSB/RESB
input is ignored.
ANYRQST
14
I
ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered
to a lower priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter
requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible).
When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Informa-
tion. If ANYRQST is strapped high and CBRQ is activated, the bus is surrendered at the end of
the present bus cycle. Strapping CBRQ low and ANYRQST high forces the 82C89 arbiter to sur-
render the multi-master system bus after each transfer cycle. Note that when surrender occurs
BREQ is driven false (high).
4-344
82C89
Pin Description (Continued)
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
IOB
2
I
IO BUS: A strapping option which configures the 82C89 Arbiter to operate in systems having both
an IO Bus (Peripheral Bus) and a multi-master system bus. The arbiter requests and surrenders
the use of the multi-master system bus as a function of the status line, S2. The multi-master sys-
tem bus is permitted to be surrendered while the processor is performing IO commands and is
requested whenever the processor performs a memory command. Interrupt cycles are assumed
as coming from the peripheral bus and are treated as an IO command.
AEN
INIT
13
6
O
I
ADDRESS ENABLE: The output of the 82C89 Arbiter to the processor’s address latches, to the
82C88 Bus Controller and 82C84A or 82C85 Clock Generator. AEN serves to instruct the Bus
Controller and address latches when to three-state their output drivers.
INITIALIZE: An active low multi-master system bus input signal used to reset all the bus arbiters
on the multi-master system bus. After initialization, no arbiters have the use of the multi-master
system bus.
SYSB/RESB
3
I
SYSTEM BUS/RESIDENT BUS: An input signal when the arbiter is configured in the System/Res-
ident Mode (RESB is strapped high) which determines when the multi-master system bus is re-
quested and multi-master system bus surrendering is permitted. The signal is intended to originate
from a form of address-mapping circuitry, such as a decoder or PROM attached to the resident
address bus. Signal transitions and glitches are permitted on this pin from θ1 of T4 to θ1 of T2 of
the processor cycle. During the period from θ1 of T2 to θ1 of T4, only clean transitions are permit-
ted on this pin (no glitches). If a glitch occurs, the arbiter may capture or miss it, and the multi-mas-
ter system bus may be requested or surrendered, depending upon the state of the glitch. The
arbiter requests the multi-master system bus in the System/Resident Mode when the state of the
SYSB/RESB pin is high and permits the bus to be surrendered when this pin is low.
CBRQ
12
I/O
COMMON BUS REQUEST: An input signal which instructs the arbiter if there are any other arbi-
ters of lower priority requesting the use of the multi-master system bus.
The CBRQ pins (open-drain output) of all the 82C89 Bus Arbiters which surrender to the multi-
master system bus upon request are connected together.
The Bus Arbiter running the current transfer cycle will not itself pull the CBRQ line low. Any other
arbiter connected to the CDRQ line can request the multi-master system bus. The arbiter presently
running the current transfer cycle drops its BREQ signal and surrenders the bus whenever the
proper surrender conditions exist. Strapping CBRQ low and ANYRQST high allows the multi-mas-
ter system bus to be surrendered after each transfer cycle. See the pin definition of ANYRQST.
BCLK
BREQ
BPRN
5
7
9
I
O
I
BUS CLOCK: The multi-master system bus clock to which all multi-master system bus interface
signals are synchronized.
BUS REQUEST: An active low output signal in the Parallel Priority Resolving Scheme which the
arbiter activates to request the use of the multi-master system bus.
BUS PRIORITY IN: The active low signal returned to the arbiter to instruct it that it may acquire the
multi-master system bus on the next falling edge of BCLK. BPRN active indicates to the arbiter that
it is the highest priority requesting arbiter presently on the bus. The loss of BPRN instructs the ar-
biter that it has lost priority to a higher priority arbiter.
BPRO
BUSY
8
O
BUS PRIORITY OUT: An active low output signal used in the serial priority resolving scheme
where BPRO is daisy-chained to BPRN of the next lower priority arbiter.
11
I/O
BUSY: An active low open-drain multi-master system bus interface signal used to instruct all the
arbiters on the bus when the multi-master system bus is available. When the multi-master system
bus is available the highest requesting arbiter (determined by BPRN) seizes the bus and pulls
BUSY low to keep other arbiters off of the bus. When the arbiter is done with the bus, it releases
the BUSY signal, permitting it to go high and thereby allowing another arbiter to acquire the multi-
master system bus.
4-345
82C89
Functional Description
The 82C89 Bus Arbiter operates in conjunction with the decoded by a decoder to select the corresponding BPRN
82C88 Bus Controller to interface 80C86, 80C88 processors (Bus Priority In) line to be returned to the highest priority
to a multi-master system bus (both the 80C86 and 80C88 requesting arbiter. The arbiter receiving priority (BPRN true)
are configured in their max mode). The processor is then allows its associated bus master onto the multi-master
unaware of the arbiter’s existence and issues commands as system bus as soon as it becomes available (i.e., the bus is
though it has exclusive use of the system bus. If the proces- no longer busy). When one bus arbiter gains priority over
sor does not have the use of the multi-master system bus, another arbiter it cannot immediately seize the bus, it must
the arbiter prevents the Bus Controller (82C88), the data wait until the present bus transaction is complete. Upon
transceivers and the address latches from accessing the completing its transaction the present bus occupant recog-
system bus (e.g. all bus driver outputs are forced into the nizes that it no longer has priority and surrenders the bus by
high impedance state). Since the command sequence was releasing BUSY. BUSY is an active low “OR” tied signal line
not issued by the 82C88, the system bus will appear as “Not which goes to every bus arbiter on the system bus. When
Ready” and the processor will enter wait states. The proces- BUSY goes inactive (high), the arbiter which presently has
sor will remain in Wait until the Bus Arbiter acquires the use bus priority (BPRN true) then seizes the bus and pulls BUSY
of the multi-master system bus whereupon the arbiter will low to keep other arbiters off of the bus. See waveform tim-
allow the bus controller, the data transceivers, and the ing diagram, Figure 2. Note that all multimaster system bus
address latches to access the system. Typically, once the transactions are synchronized to the bus clock (BCLK). This
command has been issued and a data transfer has taken allows the parallel priority resolving circuitry or any other pri-
place, a transfer acknowledge (XACK) is returned to the pro- ority resolving scheme employed to settle.
cessor to indicate “READY” from the accessed slave device.
BREQ
The processor then completes its transfer cycle. Thus the
arbiter serves to multiplex a processor (or bus master) onto
a multi-master system bus and avoid contention problems
between bus masters.
BUS
ARBITER
1
BPRN
BREQ
BPRN
BUS
ARBITER
2
74HC148
PRIORITY
ENCODER
74HC138
3 TO 8
ENCODER
Arbitration Between Bus Masters
• •
• •
• •
• •
BREQ
In general, higher priority masters obtain the bus when a
lower priority master completes its present transfer cycle.
Lower priority bus masters obtain the bus when a higher pri-
ority master is not accessing the system bus. A strapping
option (ANYRQST) is provided to allow the arbiter to surren-
der the bus to a lower priority master as though it were a
master of higher priority. If there are no other bus masters
requesting the bus, the arbiter maintains the bus so long as
its processor has not entered the HALT State. The arbiter will
not voluntarily surrender the system bus and has to be forced
off by another master’s bus request, the HALT State being
the only exception. Additional strapping options permit other
modes of operation wherein the multi-master system bus is
surrendered or requested under different sets of conditions.
BUS
ARBITER
3
BPRN
BREQ
BUS
ARBITER
4
BPRN
•
•
•
•
FIGURE 1. PARALLEL PRIORITY RESOLVING TECHNIQUE
BCLK
Priority Resolving Techniques
Since there can be many bus masters on a multi-master sys-
tem bus, some means of resolving priority between bus
masters simultaneously requesting the bus must be pro-
vided. The 82C89 Bus Arbiter provides several resolving
techniques. All the techniques are based on a priority con-
cept that at a given time one bus master will have priority
above all the rest. There are provisions for using parallel pri-
ority resolving techniques, serial priority resolving tech-
niques, and rotating priority techniques.
BREQ
1
BPRN
2
4
3
BUSY
FIGURE 2. HIGHER PRIORITY ARBITER OBTAINING THE BUS
FROM A LOWER PRIORITY ARBITER
NOTES:
Parallel Priority Resolving
1. Higher priority bus arbiter requests the Multi-Master system bus.
2. Attains priority.
The parallel priority resolving technique uses a separate bus
request line BREQ for each arbiter on the multi-master sys-
tem bus, see Figure 1. Each BREQ line enters into a priority
encoder which generates the binary address of the highest
priority BREQ line which is active. The binary address is
3. Lower priority bus arbiter releases BUSY.
4. Higher priority bus arbiter then acquires the bus and pulls BUSY
down.
4-346
82C89
Serial Priority Resolving
techniques. It allows for many arbiters to be present on the
bus while not requiring too much logic to implement.
The serial priority resolving technique eliminates the need
for the priority encoder-decoder arrangement by daisychain- 82C89 Modes Of Operation
ing the bus arbiters together, connecting the higher priority
bus arbiter’s BPRO (Bus Priority Out) output to the BPRN of
the next lower priority. See Figure 3.
There are two types of processors for which the 82C89 will
provide support: An Input/Output processor (i.e. an NMOS
8089 IOP) and the 80C86, 80C88. Consequently, there are
two basic operating modes in the 82C89 bus arbiter. One,
the IOB (I/O Peripheral Bus) mode, permits the processor
access to both an I/O Peripheral Bus and a multi-master sys-
tem bus. The second, the RESB (Resident Bus mode), per-
mits the processor to communicate over both a Resident
Bus and a multi-master system bus. An I/O Peripheral Bus is
a bus where all devices on that bus, including memory, are
treated as I/O devices and are addressed by I/O commands.
All memory commands are directed to another bus, the
multi-master system bus. A Resident Bus can issue both
memory and I/O commands, but it is a distinct and separate
bus from the multi-master system bus. The distinction is that
the Resident Bus has only one master, providing full avail-
ability and being dedicated to that one master.
BPRN
BUS
ARBITER
BPRO
1
BPRN
BUS
ARBITER
BPRO
2
BPRN
BUS
ARBITER
3
BPRO
BPRN
BUS
ARBITER
4
BPRO
The IOB strapping option configures the 82C89 Bus Arbiter
into the IOB mode and the strapping option RESB config-
ures it into the RESB mode. It might be noted at this point
that if both strapping options are strapped false, the arbiter
interfaces the processor to a multi-master system bus only
(see Figure 4). With both options strapped true, the arbiter
interfaces the processor to a multi-master system bus, a
Resident Bus, and an I/O Bus.
•
•
•
•
•
•
CBRQ BUSY
FIGURE 3. SERIAL PRIORITY RESOLVING
NOTE: The number of arbiters that may be daisy-chained together
in the serial priority resolving scheme is a function of BCLK and the
propagation delay from arbiter to arbiter. Normally, at 10MHz only 3
arbiters may be daisychained.
In the IOB mode, the processor communicates and controls
a host of peripherals over the Peripheral Bus. When the I/O
Processor needs to communicate with system memory, it
does so over the system memory bus. Figure 5 shows a pos-
sible I/O Processor system configuration.
Rotating Priority Resolving
The rotating priority resolving technique is similar to that of
the parallel priority resolving technique except that priority is
dynamically re-assigned. The priority encoder is replaced by
a more complex circuit which rotates priority between
requesting arbiters thus allowing each arbiter an equal
chance to use the multi-master system bus, over time.
The 80C86 and 80C88 processors can communicate with a
Resident Bus and a multi-master system bus. Two bus con-
trollers and only one Bus Arbiter would be needed in such a
configuration as shown in Figure 6. In such a system config-
uration the processor would have access to memory and
peripherals of both busses. Memory mapping techniques are
applied to select which bus is to be accessed. The
SYSB/RESB input on the arbiter serves to instruct the arbi-
ter as to whether or not the system bus is to be accessed.
The signal connected to SYSB/RESB also enables or dis-
ables commands from one of the bus controllers. A sum-
mary of the modes that the 82C89 has, along with its
response to its status lines inputs, is shown in Table 1.
Which Priority Resolving Technique To Use
There are advantages and disadvantages for each of the
techniques described above. The rotating priority resolving
technique requires substantial external logic to implement
while the serial technique uses no external logic but can
accommodate only a limited number of bus arbiters before the
daisy-chain propagation delay exceeds the multimaster’s sys-
tem bus clock (BCLK). The parallel priority resolving tech-
nique is in general a good compromise between the other two
4-347
82C89
X1
RDY2
82C84A/85
CLOCK
X2
V
CC
GENERATOR
AEN2
XACK MULTI-MASTER
SYSTEM BUS
RDY1
AEN1
READY
CLK
82C89
MULTI-MASTER
CONTROL BUS
BUS
ARBITER
ANYRQST
READY
CLK
V
CLK
CC
IOB
S0-S2 RESB
AEN
80C86
CPU
S0
S1
AEN
STATUS (S0, S1, S2)
AD0-AD15
A16-A19 S2
82C88
BUS
MULTI-MASTER SYSTEM
COMMAND BUS
CONTROLLER
CLK
ALE
IOB
DT/R
DEN
OE
STB
ADDRESS
LATCH
82C82/
PROCESSOR
LOCAL BUS
MULTI-MASTER SYSTEM
ADDRESS BUS
82C83H
(2 OR 3)
XCVR
DISABLE
OE
DT/R
TRANSCEIVER
82C86H/
82C87H
(2)
MULTI-MASTER SYSTEM
DATA BUS
FIGURE 4. TYPICAL MEDIUM COMPLEXITY CPU SYSTEM
4-348
82C89
AEN1
82C84A/85
CLOCK
XACK
MULTI-MASTER
SYSTEM BUS
XACK(I/O BUS)
RDY1
RDY2
82C89
BUS
ARBITER
READY
CLK
AEN2
MULTI-MASTER
CONTROL BUS
CLK
READY
CLK
S0-S2
IOB
RESB
ANYRQST
AEN
8089
IOP
V
CC
S0
AD0-AD15
STATUS (S0, S1, S2)
AEN
A16-A19 S2
82C88
BUS
I/O
MULTI-MASTER
SYSTEM
COMMAND BUS
CONTROLLER
COMMAND
BUS
PROCESSOR
LOCAL BUS
CLK
ALE
PDEN DEN DT/R
V
CC
IOB
OE
STB
OE
STB
ADDRESS
LATCH
ADDRESS
LATCH
MULTI-MASTER
SYSTEM
ADDRESS BUS
I/O
ADDRESS
BUS
82C82/
82C82/
82C83H
(2 OR 3)
82C83H
(2 OR 3)
XCVR
DISABLE
OE
T
OE
T
I/O
DATA
BUS
MULTI-MASTER
SYSTEM
DATA BUS
TRANSCEIVER
82C86H/
82C87H
(2)
TRANSCEIVER
82C86H/
82C87H
(2)
FIGURE 5. TYPICAL MEDIUM COMPLEXITY IOB SYSTEM
4-349
82C89
AEN2 AEN1
82C84A/85
CLOCK
XACK
RESIDENT BUS
XACK MULTI MASTER
SYSTEM BUS
RDY2 RDY1
CLK
READY
82C89
BUS
READY CLK
S0-S2
STATUS
S0
S1
S2
MULTI MASTER
SYSTEM BUS CONTROL
ARBITER
80C86
CPU
RESB
V
IOB
ANYRQST
CC
CLK
AEN
AD0-AD15
A16-A19
SYSB/
RESB
CEN
AEN
CEN
AEN
S0-S2
82C88
S0-S2
82C88
RESIDENT
COMMAND BUS
MULTI MASTER
SYSTEM COMMAND BUS
CLK
DT/R
DEN
CLK
DT/R
DEN
IOB
ALE
STB
ALE
PROM
OR
DECODER
OR
CMOS HPL
(NOTE)
OE
OE
STB
ADDR
LATCH
82C82/
82C83H
(2 OR 3)
ADDR
LATCH
82C82/
82C83H
(2 OR 3)
MULTI MASTER
SYSTEM ADDRESS BUS
RESIDENT
ADDRESS BUS
T
OE
OE
T
TRANSCEIVER
82C86H/
82C87H
(2)
TRANSCEIVER
82C86H/
82C87H
(2)
RESIDENT
DATA BUS
MULTI MASTER
SYSTEM DATA BUS
FIGURE 6. 82C89 BUS ARBITER SHOWN IN SYSTEM - RESIDENT BUS CONFIGURATION
NOTE: By adding another 82C89 arbiter and connecting its AEN to the 82C88 whose AEN is presently grounded, the processor could have
access to two multi-master buses.
4-350
82C89
TABLE 1. SUMMARY OF 82C89 MODES, REQUESTING AND RELINQUISHING THE MULTI-MASTER SYSTEM BUS
SINGLE LINES FROM
80C86 OR 80C88 OR 8088
RESB MODE ONLY
IOB = HIGH, RESB = HIGH
IOB MODE RESB MODE
IOB = LOW, RESB = HIGH
IOB MODE
ONLY
SINGLE BUS
MODE
IOB = LOW
RESB = LOW
SYSB/RESB =
HIGH
SYSB/RESB =
LOW
SYSB/RESB =
HIGH
SYSB/RESB =
LOW
IOB = HIGH
RESB = LOW
S2
S1
S0
I/O
Commands
0
0
0
0
0
1
0
1
0
X
X
X
†
†
†
X
X
X
X
X
X
X
X
X
†
†
†
Halt
0
1
1
X
X
X
X
X
X
Memory
Commands
1
1
1
0
0
1
0
1
0†
†
†
†
†
†
†
X
X
X
†
†
†
X
X
X
†
†
†
Idle
1
1
1
X
X
X
X
X
X
NOTES:
1. X = Multi-Master System Bus is allowed to be Surrendered.
2. † = Multi-Master System Bus is Requested.
MULTI-MASTER SYSTEM BUS
REQUESTED** SURRENDERED*
PIN
STRAPPING
MODE
Single Bus Multi-Master Mode
RESB Mode Only
IOB = High
RESB = Low
Whenever the processor’s status lines
go active
HLT + TI • CBRQ + HPBRQ ‡
IOB = High
RESB = High
SYSB/RESB + High •
ACTIVE STATUS
(SYSB/RESB = Low + TI) •
CBRQ + HLT + HPBRQ
IOB Mode Only
IOB = Low
RESB = Low
Memory Commands
(I/O Status + TI) • CBRQ + HLT +
HPBRQ
IOB Mode RESB Mode
IOB = Low
RESB = High
(Memory Command) •
(SYSB/RESB = High)
(I/O Status Commands) +
SYSB/RESB = Low) • CBRQ +
HPBRQ + HLT
NOTES:
*
LOCK prevents surrender of Bus to any other arbiter, CRQLCK prevents surrender of Bus to any lower priority arbiter.
** Except for HALT and Passive or IDLE Status.
‡ HPBRQ, Higher priority Bus request or BPRN = 1.
1. IOB Active Low.
2. RESB Active High.
3. + is read as “OR” and • as “AND”
4. TI = Processor Idle Status S2, S1, S0 = 111
5. HLT = Processor Halt Status S2, S1, S0 = 011
4-351
82C89
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance
Thermal Information
o
o
θ
( C/W)
θ
( C/W)
JA
JC
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
+0.5V
CC
CERDIP Package . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
PLCC Package . . . . . . . . . . . . . . . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300 C
(PLCC - Lead Tips Only)
80
90
75
75
20
24
N/A
N/A
Operating Conditions
o
o
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
o
o
o
C82C89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C
o
o
o
I82C89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
o
o
o
M82C89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
= 5.0V ± 10%;
CC
= 0 C to +70 C (C82C89);
o
o
T
A
o
o
T
= -40 C to +85 C (I82C89);
A
o
o
T
= -55 C to +125 C (M82C89)
A
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
C82C89, I82C89
V
Logical One Input Voltage
2.0
2.2
-
-
V
V
IH
M82C89, Note 1
V
Logical Zero Input Voltage
-
0.8
-
V
V
V
Note 1
IL
VIHC
VILC
CLK Logical One Input Voltage
CLK Logical Zero Input Voltage
0.7 VCC
-
0.2 VCC
V
Output Low Voltage
BUSY, CBRQ
AEN
OL
-
-
-
0.45
0.45
0.45
V
V
V
I
I
I
= 20mA
= 16mA
= 8mA
OL
OL
OL
BPRO, BREQ
VOH1
VOH2
Output High Voltage
BUSY, CBRQ
Open-Drain
Output High Voltage
All Other Outputs
3.0
-0.4
-
V
V
I
I
= -2.5mA
= -100µA
OH
OH
V
CC
II
Input Leakage Current
I/O Leakage
-1.0
1.0
10.0
10
µA
µA
V
= GND or V , DIP Pins 1-6, 9, 14-19
CC
IN
IO
-10.0
V
= GND or V , DIP Pins 11-12
CC
O
ICCSB
ICCOP
Standby Power Supply
Operating Power Supply Current
-
-
µA
V
= 5.5V, V = V
IN
or GND, Outputs Open
CC
CC
CC
1
mA/MHz
V
= 5.5V, Outputs Open, Note 2
NOTES:
1. Does not apply to IOB, RESB, or ANYRQST. These are strap options and should be held to VCC or GND.
2. Maximum current defined by CLK or BCLK, whichever has the highest operating frequency
o
Capacitance
SYMBOL
CIN
T
= +25 C
A
PARAMETER
TYPICAL
UNITS
pF
TEST CONDITIONS
Input Capacitance
Output Capacitance
I/O Capacitance
10
10
15
FREQ = 1MHz, all measurements are
referenced to device GND
COUT
pF
CIO
pF
4-352
82C89
AC Electrical Specifications
V
= 5.0V ± 10%; GND = 0V:
CC
= 0 C to +70 C (C82C89);
o
o
T
A
o
o
T
= -40 C to +85 C (I82C89);
A
o
o
T
= -55 C to +125 C (M82C89)
A
SYMBOL
PARAMETER
CLK Cycle Period
MIN
125
55
MAX
UNIT
ns
TEST CONDITIONS
Note 3
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
TCLCL
TCLCH
TCHCL
TSVCH
TSHCL
THVCH
THVCL
TBYSBL
TCBSBL
-
CLK Low Time
-
ns
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
CLK High Time
35
-
ns
Status Active Setup
Status Inactive Setup
Status Inactive Hold
Status Active Hold
BUSY↓↑ Setup to BCLK↓
CBRQ↓↑ Setup to BCLK↓
BCLK Cycle Time
65
TCLCL-10
ns
50
TCLCL-10
ns
10
-
-
-
-
-
ns
10
ns
20
ns
20
ns
(10) TBLBL
(11) TBHCL
100
30
ns
BCLK High Time
0.65
ns
(TBLBL)
(12) TCLLL1
(13) TCLLL2
(14) TPNBL
(15) TCLSR1
(16) TCLSR2
(17) TIVIH
LOCK Inactive Hold
LOCK Active Setup
BPRN↓↑ to BCLK Setup Time
SYSB/RESB Setup
SYSB/RESB Hold
10
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 3
40
-
Note 3
20
-
Note 3
0
-
Note 3
30
-
Note 3
Initialization Pulse Width
BCLK to BREQ Delay↓↑
BCLK to BPRO↓↑
675
-
Note 3
(18) TBLBRL
(19) TBLPOH
(20) TPNPO
(21) TBLBYL
(22) TBLBYH
(23) TCLAEH
(24) TBLAEL
(25) TBLCBL
(26) TBLCBH
(27) TOLOH
(28) TOHOL
(29) TILIH
-
-
-
-
-
-
-
-
-
-
-
-
-
35
35
22
60
35
65
40
60
40
20
12
20
20
Note 3
Note 1 and 3
Note 1 and 3
Note 3
BPRN↓↑ to BPRO↓↑ Delay
BCLK to BUSY Low
BCLK to BUSY Float
CLK to AEN High
Note 2 and 3
Note 3
BCLK to AEN Low
Note 3
BCLK to CBRQ Low
BCLK to CBRQ Float
Output Rise Time
Note 3
Note 2 and 3
From 0.8V to 2.0V, Note 4
From 2.0V to 0.8V, Note 4
From 0.8V to 2.0V
From 2.0V to 0.8V
Output Fall Time
Input Rise Time
(30) TIHIL
Input Fall Time
NOTES:
1. BCLK generates the first BPRO wherein subsequent BPRO changes lower in the chain are generated through BPRON.
2. Measured at 0.5V above GND.
3. All AC parameters tested as per AC test load circuits. Input rise and fall times are driven at 1ns/V.
4. Except BUSY and CBRQ
4-353
82C89
AC Test Load Circuits
BUSY, CBRQ LOAD CIRCUIT
2.5V
AEN LOAD CIRCUIT
2.9V
BPRO, BREQ LOAD CIRCUIT
2.9V
102Ω
157.2Ω
249.6Ω
OUTPUT FROM
DEVICE
UNDER TEST
OUTPUT FROM
DEVICE
UNDER TEST
TEST
POINT
OUTPUT FROM
DEVICE
UNDER TEST
TEST
POINT
TEST
POINT
100pF
(NOTE)
100pF
(NOTE)
100pF
(NOTE)
NOTE: Includes Stray and Jig Capacitance
AC Testing Input, Output Waveform
INPUT
OUTPUT
V
+0.4V
-0.4V
V
AC Testing: Inputs are driven at V +0.4V for a logic “1” and V
IH IL
IH
OH
-0.4V for a logic “0”. The clock is driven at V
-0.4V and 0.4V. Tim-
CC
ing measurements are made at 1.5V for both a logic “1” and “0”.
1.5V
1.5V
V
V
OL
IL
4-354
82C89
Timing Waveform
STATE
CLK
T4
T1
T2
T3
T4
(1)
TCLCL
TCLCH
(2)
(6)
THVCH
TSHCL (5)
TCHCL
(3)
TSVCH
(4)
THVCL
(7)
S2, S1, S0
(12)
TCLLL1
TCLL2
(13)
LOCK
(SEE NOTE 1)
(SEE
NOTE 2)
(SEE NOTE 2)
TCLSR1 (15)
SYSB/RESB
(16)
TCLSR2
AEN
(SEE NOTE 3)
(24)
TBLAEL
(23)
TCLAEH
PROCESSOR CLK RELATED
BUS CLK RELATED
TBLBL
(10)
(11)
TBHCL
BCLK
(18) TBLBRL
BREQ #2
TBLPOH (19)
BPRN #2
(14)
TPNBL
(BPRO #1)
BPRO #2
(20)
TPnPO
(BPRN #3)
TBYSBL (8)
BUSY
TBLBYL (21)
(25) TBLCBL
CBRQ
TBLBYH
(22)
TCBSBL (9)
(26) TBLCBH
NOTES:
1. LOCK active can occur during any state, as long as the relationships shown above with respect to the CLK are maintained. LOCK inactive
has no critical time and can be asynchronous. CRQLCK has no critical timing and is considered an asynchronous input signal.
2. Glitching of SYSB/RESB is permitted during this time. After θ2 of T1, and before θ1 of T4, SYSB/RESB should be stable to maintain sys-
tem efficiency.
3. AEN leading edge is related to BCLK, trailing edge to CLK. The trailing edge of AEN occurs after bus priority is lost.
ADDITIONAL NOTES:
The signals related to CLK are typical processor signals, and do not relate to the depicted sequence of events of the signals referenced to
BCLK. The signals shown related to the BCLK represent a hypothetical sequence of events for illustration. Assume 3 bus arbiters of priori-
ties 1, 2 and 3 configured in serial priority resolving scheme (as shown in Figure 3). Assume arbiter 1 has the bus and is holding BUSY low.
Arbiter #2 detects its processor wants the bus and pulls low BREQ #2. If BPRN #2 is high (as shown), arbiter #2 will pull low CBRQ line.
CBRQ signals to the higher priority arbiter #1 that a lower priority arbiter wants the bus. [A higher priority arbiter would be granted BPRN
when it makes the bus request rather than having to wait for another arbiter to release the bus through CBRQ]. *Arbiter #1 will relinquish the
multi-master system bus when it enters a state not requiring it (see Table 1), by lowering its BPRO #1 (tied to BPRN #2) and releasing BUSY.
Arbiter #2 now sees that is has priority from BPRN #2 being low and releases CBRQ. As soon as BUSY signifies the bus is available (high),
arbiter #2 pulls BUSY low on next falling edge of BCLK. Note that if arbiter #2 didn’t want the bus at the time it received priority, it would pass
priority to the next lower priority arbiter by lowering its BPRO #2 [TPNPO].
Note that even a higher priority arbiter which is acquiring the bus through BPRN will momentarily drop CBRQ until it has acquired the bus.
4-355
82C89
Burn-In Circuits
MD82C89 CERDIP
V
CC
C1
R2
R2
R2
R2
R2
R1
R1
R1
R2
20
1
2
3
4
5
6
F7
F13
F14
F12
F0
R2
19
18
17
16
15
14
13
F6
R2
R2
R2
R2
R2
R1
F5
F0
F9
V
F10
F11
CC
7
8
V
CC/2
R1
R1
V
CC/2
9
F8
12
11
10
MR82C89 CLCC
V
CC
C1
F14 F13 F7
F6
R
R
R
R
2
2
2
2
3
2
1
20 19
R2
R2
R2
R1
R1
F5
F0
F9
18
F12
F0
4
5
6
7
8
R2
R2
R2
17
16
15
14
V
CC
F10
F11
V
CC/ 2
R2
R1
9
10 11 12 13
R
R
R
R
1 1
1
2
F8
V
CC/ 2
NOTES:
1. V
= 5.5V ± 0.5V, GND = 0V
CC
2. V = 4.5V ± 10%, V = -0.2V to +0.4V
IH IL
3. Components Values:
R1 = 1.2kΩ, 1/4W, 5%
R2 = 47kΩ, 1/4W, 5%
C1 = 0.01µF minimum
F0 = 100kHz ± 10%
F1 = F0/2
F2 = F1/2. . . .
F14 = F13/2
4-356
82C89
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
92.9 x 95.7 x 19 ± 1mils
Type: Nitrox
Thickness: 10kÅ ± 2kÅ
METALLIZATION:
Type: Si - Al
WORST CASE CURRENT DENSITY:
5
2
Thickness: 11kÅ ± 2kÅ
1.8 x 10 A/cm
Metallization Mask Layout
82C89
RESB
CLK
BCLK
INIT
ANYRQST
LOCK
CRQLCK
ANYRQST
BREQ
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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4-357
相关型号：
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