IS82C37A [INTERSIL]
CMOS High Performance Programmable DMA Controller; CMOS高性能可编程DMA控制器
| 型号： | IS82C37A |
| 厂家： | 
Intersil |
| 描述： | CMOS High Performance Programmable DMA Controller |
| 文件： | 总23页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
82C37A
CMOS High Performance
Programmable DMA Controller
March 1997
Features
Description
• Compatible with the NMOS 8237A
The 82C37A is an enhanced version of the industry standard
8237A Direct Memory Access (DMA) controller, fabricated
using Intersil’s advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased functionality, improved performance, and
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.
• Four Independent Maskable Channels with Autoinitial-
ization Capability
• Cascadable to any Number of Channels
• High Speed Data Transfers:
- Up to 4MBytes/sec with 8MHz Clock
- Up to 6.25MBytes/sec with 12.5MHz Clock
The 82C37A controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
- ICCSB = 10µA Maximum
- ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
The 82C37A is designed to be used with an external
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
• Internal Registers may be Read from Software
Ordering Information
PART NUMBER
TEMPERATURE
5MHz
CP82C37A-5
8MHz
CP82C37A
12.5MHz
CP82C37A-12
IP82C37A-12
PACKAGE
40 Ld PDIP
RANGE
PKG. NO.
E40.6
o
o
0 C to +70 C
o
o
IP82C37A-5
IP82C37A
-40 C to +85 C
E40.6
o
o
CS82C37A-5
CS82C37A
CS82C37A-12
IS82C37A-12
44 Ld PLCC
0 C to +70 C
N44.65
N44.65
F40.6
o
o
IS82C37A-5
IS82C37A
-40 C to +85 C
o
o
CD82C37A-5
CD82C37A
CD82C37A-12
ID82C37A-12
40 Ld CERDIP
0 C to +70 C
o
o
ID82C37A-5
ID82C37A
-40 C to +85 C
F40.6
o
o
MD82C37A-5/B
5962-9054301MQA
MR82C37A-5/B
5962-9054301MXA
MD82C37A/B
5962-9054302MQA
MR82C37A/B
5962-9054302MXA
MD82C37A-12/B
5962-9054303MQA
MR82C37A-12/B
5962-9054303MXA
-55 C to +125 C
F40.6
SMD#
F40.6
o
o
44 Pad CLCC
SMD#
-55 C to +125 C
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2967.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19949-192
82C37A
Pinouts
82C37A (PDIP/CERDIP)
82C37A (CLCC/PLCC)
TOP VIEW
TOP VIEW
IOR
IOW
1
40 A7
2
3
4
5
6
7
8
9
39 A6
44
43 42 41 40
6
5
4
3
2
1
MEMR
MEMW
NC
38 A5
7
39
38
NC
NC
A3
A2
37 A4
8
36 EOP
35 A3
HLDA
9
37 A1
READY
HLDA
ADSTB
AEN
10
11
12
A0
ADSTB
AEN
36
35
34
33
32
31
30
29
34 A2
VCC
DB0
DB1
DB2
DB3
DB4
NC
33 A1
HRQ
CS 13
32 A0
CLK
14
15
HRQ 10
CS 11
31 VCC
30 DB0
29 DB1
28 DB2
27 DB3
26 DB4
25 DACK0
24 DACK1
23 DB5
22 DB6
21 DB7
RESET
DACK2 16
NC
CLK 12
17
RESET 13
DACK2 14
DACK3 15
DREQ3 16
DREQ2 17
DREQ1 18
DREQ0 19
(GND) VSS 20
18 19 20 21 22 23 24 25 26 27 28
Block Diagram
IO
BUFFER
EOP
RESET
CS
DECREMENTOR
INC/DECREMENTOR
A0 - A3
TEMP WORD
COUNT REG (16)
TEMP ADDRESS
REG (16)
READY
CLK
16-BIT BUS
TIMING
AND
CONTROL
16-BIT BUS
READ WRITE BUFFER
AEN
OUTPUT
BUFFER
A4 - A7
READ BUFFER
ADSTB
MEMR
MEMW
IOR
BASE
CURRENT
WORD
COUNT
(16)
BASE
ADDRESS
(16)
CURRENT
ADDRESS
(16)
WORD
COUNT
(16)
IOW
COMMAND
CONTROL
WRITE
BUFFER
READ
BUFFER
D0 - D1
4
4
DREQ0 -
DREQ3
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
COMMAND
(8)
IO
BUFFER
INTERNAL DATA BUS
HLDA
HRQ
MASK
(4)
DACK0 -
DACK3
REQUEST
(4)
STATUS
(8)
TEMPORARY
(8)
MODE
(4 x 6)
4-193
82C37A
Pin Description
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
V
31
V
: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for
CC
CC
decoupling.
GND
CLK
20
12
Ground
I
CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A
operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for
the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for
standby operation.
CS
11
13
I
I
CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for
CPU communications.
RESET
RESET: This is an active high input which clears the Command, Status, Request, and Temporary
registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore
requests. Following a Reset, the controller is in an idle cycle.
READY
HLDA
6
7
I
I
READY: This signal can be used to extend the memory read and write pulses from the 82C37A to
accommodate slow memories or I/O devices. READY must not make transitions during its specified
set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode.
HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has
relinquished control of the system busses. HLDA is a synchronous input and must not transition
during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising
edge of CLK, during which time HLDA must not transition.
DREQ0-
DREQ3
16-19
I
DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request
inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest
priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a
channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is
programmable. RESET initializes these lines to active high. DREQ must be maintained until the
corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused
DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set.
DB0-DB7
21-23
26-30
I/O
DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data
bus. The outputs are enabled in the Program condition during the I/O Read to output the contents
of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle
when the CPU is programming the 82C37A control registers. During DMA cycles, the most signifi-
cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB.
In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during
the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write
the data into the new memory location.
IOR
1
2
I/O
I/O
I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control
signal used by the 82C37A to access data from the peripheral during a DMA Write transfer.
IOW
I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output
control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.
4-194
82C37A
Pin Description (Continued)
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
EOP
36
I/O
END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information
concerning the completion of DMA services is available at the bidirectional EOP pin.
The 82C37A allows an external signal to terminate an active DMA service by pulling the EOP pin
low. A pulse is generated by the 82C37A when terminal count (TC) for any channel is reached,
except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will
be output when the TC for channel 1 occurs.
The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor
to V
.
CC
When an EOP pulse occurs, whether internally or externally generated, the 82C37A will terminate
the service, and if autoinitialize is enabled, the base registers will be written to the current registers
of that channel. The mask bit and TC bit in the status word will be set for the currently active channel
by EOP unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear.
A0-A3
32-35
I/O
ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle
cycle, they are inputs and are used by the 82C37A to address the control register to be loaded or
read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address.
A4-A7
HRQ
37-40
10
O
O
ADDRESS: The four most significant address lines are three-state outputs and provide 4-bits of
address. These lines are enabled only during the DMA service.
HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus.
When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made,
the 82C37A issues HRQ. The HLDA signal then informs the controller when access to the system
busses is permitted. For stand-alone operation where the 82C37A always controls the busses, HRQ
may be tied to HLDA. This will result in one S0 state before the transfer.
DACK0-
DACK3
14, 15
24, 25
O
O
O
DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one
has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them
to active low.
AEN
9
8
ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits
onto the system address bus. AEN can also be used to disable other system bus drivers during DMA
transfers. AEN is active high.
ADSTB
ADDRESS STROBE: This is an active high signal used to control latching of the upper address
byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82.
During block operations, ADSTB will only be issued when the upper address byte must be updated,
thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling
edge of the 82C37A clock.
MEMR
MEMW
NC
3
4
5
O
O
MEMORY READ: The Memory Read signal is an active low three-state output used to access data
from the selected memory location during a DMA Read or a memory-to-memory transfer.
MEMORY WRITE: The Memory Write signal is an active low three-state output used to write data
to the selected memory location during a DMA Write or a memory-to-memory transfer.
NO CONNECT: Pin 5 is open and should not be tested for continuity.
4-195
82C37A
Functional Description
The 82C37A direct memory access controller is designed to For example, if a block of data is to be transferred from RAM
improve the data transfer rate in systems which must to an I/O device, the starting address of the data is loaded
transfer data from an I/O device to memory, or move a block into the 82C37A Current and Base Address registers for a
of memory to an I/O device. It will also perform memory-to- particular channel, and the length of the block is loaded into
memory block moves, or fill a block of memory with data the channel’s Word Count register. The corresponding Mode
from a single location. Operating modes are provided to register is programmed for a memory-to-I/O operation (read
handle single byte transfers as well as discontinuous data transfer), and various options are selected by the Command
streams, which allows the 82C37A to control data movement register and the other Mode register bits. The channel’s
with software transparency.
mask bit is cleared to enable recognition of a DMA request
(DREQ). The DREQ can either be a hardware signal or a
software command.
The DMA controller is a state-driven address and control
signal generator, which permits data to be transferred
directly from an I/O device to memory or vice versa without Once initiated, the block DMA transfer will proceed as the
ever being stored in a temporary register. This can greatly controller outputs the data address, simultaneous MEMR
increase the data transfer rate for sequential operations, and IOW pulses, and selects an I/O device via the DMA
compared with processor move or repeated string acknowledge (DACK) outputs. The data byte flows directly
instructions.
Memory-to-memory
operations
require from the RAM to the I/O device. After each byte is
temporary internal storage of the data byte between transferred, the address is automatically incremented (or
generation of the source and destination addresses, so decremented) and the word count is decremented. The
memory-to-memory transfers take place at less than half the operation is then repeated for the next byte. The controller
rate of I/O operations, but still much faster than with central stops transferring data when the Word Count register
processor techniques. The maximum data transfer rates underflows, or an external EOP is applied.
obtainable with the 82C37A are shown in Figure 1.
NAME
Base Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Temporary Address Register
Temporary Word Count Register
Status Register
SIZE
16-Bits
16-Bits
16-Bits
16-Bits
16-Bits
16-Bits
8-Bits
NUMBER
The block diagram of the 82C37A is shown on page 2. The
timing and control block, priority block, and internal registers
are the main components. Figure 2 lists the name and size
of the internal registers. The timing and control block derives
internal timing from clock input, and generates external
control signals. The Priority Encoder block resolves priority
contention between DMA channels requesting service
simultaneously.
4
4
4
4
1
1
1
1
1
4
1
1
82C37A
TRANSFER
TYPE
Compressed
Normal I/O
5MHz
2.50
1.67
0.63
8MHz
4.00
2.67
1.00
12.5MHz
6.25
UNIT
MByte/sec
MByte/sec
MByte/sec
Command Register
8-Bits
4.17
Temporary Register
8-Bits
Memory-to-
Memory
1.56
Mode Registers
6-Bits
FIGURE 1. DMA TRANSFER RATES
Mask Register
4-Bits
DMA Operation
Request Register
4-Bits
In a system, the 82C37A address and control outputs and
data bus pins are basically connected in parallel with the
system busses. An external latch is required for the upper
address byte. While inactive, the controller’s outputs are in a
high impedance state. When activated by a DMA request
and bus control is relinquished by the host, the 82C37A
drives the busses and generates the control signals to
perform the data transfer. The operation performed by
activating one of the four DMA request inputs has previously
been programmed into the controller via the Command,
Mode, Address, and Word Count registers.
FIGURE 2. 82C37A INTERNAL REGISTERS
To further understand 82C37A operation, the states
generated by each clock cycle must be considered. The
DMA controller operates in two major cycles, active and idle.
After being programmed, the controller is normally idle until
a DMA request occurs on an unmasked channel, or a
software request is given. The 82C37A will then request
control of the system busses and enter the active cycle. The
active cycle is composed of several internal states,
depending on what options have been selected and what
type of operation has been requested.
4-196
82C37A
The 82C37A can assume seven separate states, each Special software commands can be executed by the
composed of one full clock period. State I (SI) is the idle 82C37A in the Program Condition. These commands are
state. It is entered when the 82C37A has no valid DMA decoded as sets of addresses with CS, IOR, and IOW. The
requests pending, at the end of a transfer sequence, or commands do not make use of the data bus. Instructions
when a Reset or Master Clear has occurred. While in SI, the include Set and Clear First/Last Flip-Flop, Master Clear,
DMA controller is inactive but may be in the Program Clear Mode Register Counter, and Clear Mask Register.
Condition (being programmed by the processor).
Active Cycle
State 0 (S0) is the first state of a DMA service. The 82C37A
has requested a hold but the processor has not yet returned
When the 82C37A is in the Idle cycle, and a software
an acknowledge. The 82C37A may still be programmed until
request or an unmasked channel requests a DMA service,
it has received HLDA from the CPU. An acknowledge from
the device will issue HRQ to the microprocessor and enter
the CPU will signal the DMA transfer may begin. S1, S2, S3,
the Active cycle. It is in this cycle that the DMA service will
and S4 are the working state of the DMA service. If more
take place, in one of four modes:
time is needed to complete a transfer than is available with
Single Transfer Mode - In Single Transfer mode, the device
is programmed to make one transfer only. The word count
will be decremented and the address decremented or
incremented following each transfer. When the word count
“rolls over” from zero to FFFFH, a terminal count bit in the
status register is set, an EOP pulse is generated, and the
channel will autoinitialize if this option has been selected. If
not programmed to autoinitialize, the mask bit will be set,
along with the TC bit and EOP pulse.
normal timing, wait states (SW) can be inserted between S3
and S4 in normal transfers by the use of the Ready line on
the 82C37A. For compressed transfers, wait states can be
inserted between S2 and S4. See timing Figures 14 and 15.
Note that the data is transferred directly from the I/O device
to memory (or vice versa) with IOR and MEMW (or MEMR
and IOW) being active at the same time. The data is not read
into or driven out of the 82C37A in I/O-to-memory or
memory-to-I/O DMA transfers.
DREQ must be held active until DACK becomes active. If
DREQ is held active throughout the single transfer, HRQ will
go inactive and release the bus to the system. It will again go
active and, upon receipt of a new HLDA, another single
transfer will be performed, unless a higher priority channel
takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this
will ensure one full machine cycle execution between DMA
transfers. Details of timing between the 82C37A and other
bus control protocols will depend upon the characteristics of
the microprocessor involved.
Memory-to-memory transfers require a read-from and a write-
to memory to complete each transfer. The states, which
resemble the normal working states, use two-digit numbers
for identification. Eight states are required for a single transfer.
The first four states (S11, S12, S13, S14) are used for the
read-from-memory half and the last four state (S21, S22, S23,
S24) for the write-to-memory half of the transfer.
Idle Cycle
When no channel is requesting service, the 82C37A will Block Transfer Mode - In Block Transfer mode, the device
enter the idle cycle and perform “SI” states. In this cycle, the is activated by DREQ or software request and continues
82C37A will sample the DREQ lines on the falling edge of making transfers during the service until a TC, caused by
every clock cycle to determine if any channel is requesting a word count going to FFFFH, or an external End of Process
DMA service.
(EOP) is encountered. DREQ need only be held active until
DACK becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been
programmed for that option.
Note that for standby operation where the clock has been
stopped, DMA requests will be ignored. The device will
respond to CS (chip select), in case of an attempt by the
microprocessor to write or read the internal registers of the Demand Transfer Mode - In Demand Transfer mode the
82C37A. When CS is low and HLDA is low, the 82C37A device continues making transfers until a TC or external EOP is
enters the Program Condition. The CPU can now establish, encountered, or until DREQ goes inactive. Thus, transfer may
change or inspect the internal definition of the part by read- continue until the I/O device has exhausted its data capacity.
ing from or writing to the internal registers.
After the I/O device has had a chance to catch up, the DMA
service is reestablished by means of a DREQ. During the time
between services when the microprocessor is allowed to oper-
ate, the intermediate values of address and word count are
stored in the 82C37A Current Address and Current Word
Count registers. Higher priority channels may intervene in the
demand process, once DREQ has gone inactive. Only an EOP
can cause an Autoinitialization at the end of service. EOP is
generated either by TC or by an external signal.
The 82C37A may be programmed with the clock stopped, pro-
vided that HLDA is low and at least one rising clock edge has
occurred after HLDA was driven low, so the controller is in an SI
state. Address lines A0-A3 are inputs to the device and select
which registers will be read or written. The IOR and IOW lines
are used to select and time the read or write operations. Due to
the number and size of the internal registers, an internal flip-flop
called the First/Last Flip-Flop is used to generate an additional
bit of address. The bit is used to determine the upper or lower Cascade Mode - This mode is used to cascade more than
byte of the 16-bit Address and Work Count registers. The flip- one 82C37A for simple system expansion. The HRQ and
flop is reset by Master Clear or RESET. Separate software HLDA signals from the additional 82C37A are connected to
commands can also set or reset this flip-flop.
the DREQ and DACK signals respectively of a channel for
4-197
82C37A
the initial 82C37A.This allows the DMA requests of the Autoinitialize - By setting bit 4 in the Mode register, a
additional device to propagate through the priority network channel may be set up as an Autoinitialize channel. During
circuitry of the preceding device. The priority chain is Autoinitialization, the original values of the Current Address
preserved and the new device must wait for its turn to and Current Word Count registers are automatically restored
acknowledge requests. Since the cascade channel of the from the Base Address and Base Word Count registers of
initial 82C37A is used only for prioritizing the additional the channel following EOP. The base registers are loaded
device, it does not output an address or control signals of its simultaneously with the current registers by the micropro-
own. These could conflict with the outputs of the active chan- cessor and remain unchanged throughout the DMA service.
nel in the added device. The initial 82C37A will respond to The mask bit is not set when the channel is in Autoinitialize
DREQ and generate DACK but all other outputs except HRQ mode. Following Autoinitialization, the channel is ready to
will be disabled. An external EOP will be ignored by the initial perform another DMA service, without CPU intervention, as
device, but will have the usual effect on the added device.
soon as a valid DREQ is detected, or software request
made.
Figure 3 shows two additional devices cascaded with an
initial device using two of the initial device’s channels. This Memory-to-Memory - To perform block moves of data from
forms a two-level DMA system. More 82C37As could be one memory address space to another with minimum of
added at the second level by using the remaining channels program effort and time, the 82C37A includes a memory-to-
of the first level. Additional devices can also be added by memory transfer feature. Setting bit 0 in the Command
cascading into the channels of the second level devices, register selects channels 0 and 1 to operate as memory-to-
forming a third level.
memory transfer channels.
The transfer is initiated by setting the software or hardware
DREQ for channel 0. The 82C37A requests a DMA service
in the normal manner. After HLDA is true, the device, using
four-state transfers in Block Transfer mode, reads data from
the memory. The channel 0 Current Address register is the
source for the address used and is decremented or
incremented in the normal manner. The data byte read from
the memory is stored in the 82C37A internal Temporary reg-
ister. Another four-state transfer moves the data to memory
using the address in channel one’s Current Address register
and incrementing or decrementing it in the normal manner.
The channel 1 Current Word Count is decremented.
2ND LEVEL
80C86/88
MICRO-
PROCESSOR
82C37A
1ST LEVEL
HRQ
HLDA
HRQ
HLDA
DREQ
DACK
82C37A
HRQ
HLDA
DREQ
DACK
82C37A
INITIAL DEVICE
When the word count of channel 1 decrements to FFFFH, a
TC is generated causing an EOP output, terminating the
service, and setting the channel 1 TC bit in the Status
register. The channel 1 mask bit will also be set, unless the
channel 1 mode register is programmed for autoinitialization.
Channel 0 word count decrementing to FFFFH will not set
the channel 0 TC bit in the status register nor generate an
EOP, nor set the channel 0 mask bit in this mode. It will
cause an autoinitialization of channel 0, if that option has
been selected.
ADDITIONAL
DEVICES
FIGURE 3. CASCADED 82C37As
When programming cascaded controllers, start with the first
level device (closest to the microprocessor). After RESET,
the DACK outputs are programmed to be active low and are
held in the high state. If they are used to drive HLDA directly,
the second level device(s) cannot be programmed until
DACK polarity is selected as active high on the initial device.
Also, the initial device’s mask bits function normally on
cascaded channels, so they may be used to inhibit second-
level services.
If full Autoinitialization for a memory-to-memory operation is
desired, the channel 0 and channel 1 word counts must be
set to equal values before the transfer begins. Otherwise, if
channel 0 underflows before channel 1, it will autoinitialize
and set the data source address back to the beginning of the
block. If the channel 1 word count underflows before channel
0, the memory-to-memory DMA service will terminate, and
channel 1 will autoinitialize but channel 0 will not.
Transfer Types
Each of the three active transfer modes can perform three dif-
ferent types of transfers. These are Read, Write and Verify.
Write transfers move data from an I/O device to the memory
by activating MEMW and IOR. Read transfers move data from
memory to an I/O device by activating MEMR and IOW.
In memory-to-memory mode, Channel
0
may be
programmed to retain the same address for all transfers.
This allows a single byte to be written to a block of memory.
This channel 0 address hold feature is selected by setting bit
1 in the Command register.
Verify transfers are pseudo-transfers. The 82C37A operates
as in Read or Write transfers generating addresses and
responding to EOP, etc., however the memory and I/O
control lines all remain inactive. Verify mode is not permitted
for memory-to-memory operation. READY is ignored during
Verify transfers.
The 82C37A will respond to external EOP signals during
memory-to-memory transfers, but will only relinquish the
system busses after the transfer is complete (i.e. after an
4-198
82C37A
S24 state). It should be noted that an external EOP cannot address bits to an external latch from which they may be
cause the channel 0 Address and Word Count registers to placed on the address bus. The falling edge of Address
autoinitialize, even if the Mode register is programmed for Strobe (ADSTB) is used to load these bits from the data
autoinitialization. An external EOP will autoinitialize the lines to the latch. Address Enable (AEN) is used to enable
channel 1 registers, if so programmed. Data comparators in the bits onto the address bus through a three-state enable.
block search schemes may use the EOP input to terminate The lower order address bits are output by the 82C37A
the service when a match is found. The timing of memory-to- directly. Lines A0-A7 should be connected to the address
memory transfers is found in Figure 13. Memory-to-memory bus. Figure 12 shows the time relationships between CLK,
operations can be detected as an active AEN with no DACK AEN, ADSTB, DB0-DB7 and A0-A7.
outputs.
During Block and Demand Transfer mode service, which
Priority - The 82C37A has two types of priority encoding include multiple transfers, the addresses generated will be
available as software selectable options. The first is Fixed sequential. For many transfers the data held in the external
Priority which fixes the channels in priority order based upon address latch will remain the same. This data need only
the descending value of their numbers. The channel with the change when a carry or borrow from A7 to A8 takes place in
lowest priority is 3 followed by 2, 1 and the highest priority the normal sequence of addresses. To save time and speed
channel, 0. After the recognition of any one channel for ser- transfers, the 82C37A executes S1 states only when
vice, the other channels are prevented from interfering with updating of A8-A15 in the latch is necessary. This means for
the service until it is completed.
long services, S1 states and Address Strobes may occur
only once every 256 transfers, a savings of 255 clock cycles
for each 256 transfers.
The second scheme is Rotating Priority. The last channel to
get service becomes the lowest priority channel with the
others rotating accordingly. The next lower channel from the
channel serviced has highest priority on the following
request. Priority rotates every time control of the system
busses is returned to the processor.
Programming
The 82C37A will accept programming from the host
processor anytime that HLDA is inactive, and at least one
rising clock edge has occurred after HLDA went low. It is the
responsibility of the host to assure that programming and
HLDA are mutually exclusive.
Rotating Priority
1st
2nd
3rd
SERVICE
SERVICE
SERVICE
Note that a problem can occur if a DMA request occurs on
an unmasked channel while the 82C37A is being pro-
grammed. For instance, the CPU may be starting to repro-
gram the two byte Address register of channel 1 when
channel 1 receives a DMA request. If the 82C37A is enabled
(bit 2 in the Command register is 0), and channel 1 is
unmasked, a DMA service will occur after only one byte of
the Address register has been reprogrammed. This condi-
tion can be avoided by disabling the controller (setting bit 2
in the Command register) or masking the channel before
programming any of its registers. Once the programming is
complete, the controller can be enabled/unmasked.
Highest
0
1
2
3
2
3
0
1
Service
3
0
1
2
Service
Service
Request
Lowest
With Rotating Priority in a single chip DMA system, any
device requesting service is guaranteed to be recognized
after no more than three higher priority services have
occurred. This prevents any one channel from monopolizing
the system.
Regardless of which priority scheme is chosen, priority is
evaluated every time a HLDA is returned to the 82C37A.
After power-up it is suggested that all internal locations be
loaded with some known value, even if some channels are
unused. This will aid in debugging.
Compressed Timing - In order to achieve even greater
throughput where system characteristics permit, the 82C37A
can compress the transfer time to two clock cycles. From
Figure 12 it can be seen that state S3 is used to extend the
access time of the read pulse. By removing state S3, the
read pulse width is made equal to the write pulse width and
a transfer consists only of state S2 to change the address
and state S4 to perform the read/write. S1 states will still
occur when A8-A15 need updating (see Address
Generation). Timing for compressed transfers is found in
Figure 15. EOP will output in S2 if compressed timing is
selected. Compressed timing is not allowed for memory-to-
memory transfers.
Register Description
Current Address Register - Each channel has a 16-bit
Current Address register. This register holds the value of the
address used during DMA transfers. The address is auto-
matically incremented or decremented by one after each
transfer and the values of the address are stored in the Cur-
rent Address register during the transfer. This register is writ-
ten or read by the microprocessor in successive 8-bit bytes.
See Figure 6 for programming information. It may also be
reinitialized by an Autoinitialize back to its original value.
Autoinitialize takes place only after an EOP. In memory-to-
memory mode, the channel 0 Current Address register can
be prevented from incrementing or decrementing by setting
the address hold bit in the Command register.
Address Generation - In order to reduce pin count, the
82C37A multiplexes the eight higher order address bits on
the data lines. State S1 is used to output the higher order
4-199
82C37A
Current Word Count Register - Each channel has a 16-bit Mode Register - Each channel has a 6-bit Mode register
Current Word Count register. This register determines the associated with it. When the register is being written to by
number of transfers to be performed. The actual number of the microprocessor in the Program condition, bits 0 and 1
transfers will be one more than the number programmed in determine which channel Mode register is to be written.
the Current Word Count register (i.e., programming a count When the processor reads a Mode register, bits 0 and 1 will
of 100 will result in 101 transfers). The word count is both be ones. See the following diagram and Figure 4 for
decremented after each transfer. When the value in the Mode register functions and addresses.
register goes from zero to FFFFH, a TC will be generated.
This register is loaded or read in successive 8-bit bytes by
Mode Register
the microprocessor in the Program Condition. See Figure 6
for programming information. Following the end of a DMA
service it may also be reinitialized by an Autoinitialization
back to its original value. Autoinitialization can occur only
when an EOP occurs. If it is not Autoinitialized, this register
will have a count of FFFFH after TC.
7
6
5
4
3
2
1
0
BIT NUMBER
00 Channel 0 select
01 Channel 1 select
10 Channel 2 select
11 Channel 3 select
XX Readback
Base Address and Base Word Count Registers - Each
channel has a pair of Base Address and Base Word Count
registers. These 16-bit registers store the original value of
their associated current registers. During Autoinitialize these
values are used to restore the current registers to their
original values. The base registers are written simulta-
neously with their corresponding current register in 8-bit
bytes in the Program Condition by the microprocessor. See
Figure 6 for programming information. These registers can-
not be read by the microprocessor.
00 Verify transfer
01 Write transfer
10 Read transfer
11 Illegal
XX If bits 6 and 7 = 11
0
1
Autoinitialization disable
Autoinitialization enable
0
1
Address increment select
Address decrement select
Command Register - This 8-bit register controls the opera-
tion of the 82C37A. It is programmed by the microprocessor
and is cleared by RESET or a Master Clear instruction. The
following diagram lists the function of the Command register
bits. See Figure 4 for Read and Write addresses.
00 Demand mode select
01 Single mode select
10 Block mode select
11 Cascade mode select
Command Register
Request Register - The 82C37A can respond to requests
for DMA service which are initiated by software as well as by
a DREQ. Each channel has a request bit associated with it in
the 4-bit Request register. These are non-maskable and
subject to prioritization by the Priority Encoder network.
Each register bit is set or reset separately under software
control. The entire register is cleared by a Reset or Master
Clear instruction. To set or reset a bit, the software loads the
proper form of the data word. See Figure 4 for register
address coding, and the following diagram for Request
register format. A software request for DMA operation can
be made in block or single modes. For memory-to-memory
transfers, the software request for channel 0 should be set.
When reading the Request register, bits 4-7 will always read
as ones, and bits 0-3 will display the request bits of channels
0-3 respectively.
7
6
5
4
3
2
1
0
BIT NUMBER
0
1
Memory-to-memory disable
Memory-to-memory enable
0
1
X
Channel 0 address hold disable
Channel 0 address hold enable
If bit 0 = 0
0
1
Controller enable
Controller disable
0
1
X
Normal timing
Compressed timing
If bit 0 = 1
0
1
Fixed priority
Rotating priority
Request Register
7
6
5
4
3
2
1
0
BIT NUMBER
0
1
X
Late write selection
Extended write selection
If bit 3 = 1
00 Select Channel 0
01 Select Channel 1
10 Select Channel 2
11 Select Channel 3
Don’t Care,
Write
Bits 4-7
All Ones,
Read
0
1
DREQ sense active high
DREQ sense active low
0
1
Reset request bit
Set request bit
0
1
DACK sense active low
DACK sense active high
4-200
82C37A
Mask Register - Each channel has associated with it a mask Status Register - The Status register is available to be read
bit which can be set to disable an incoming DREQ. Each out of the 82C37A by the microprocessor. It contains
mask bit is set when its associated channel produces an EOP information about the status of the devices at this point. This
if the channel is not programmed to Autoinitialize. Each bit of information includes which channels have reached a terminal
the 4-bit Mask register may also be set or cleared separately count and which channels have pending DMA requests. Bits
or simultaneously under software control. The entire register 0-3 are set every time a TC is reached by that channel or an
is also set by a Reset or Master clear. This disables all hard- external EOP is applied. These bits are cleared upon RESET,
ware DMA requests until a Clear Mask Register instruction Master Clear, and on each Status Read. Bits 4-7 are set
allows them to occur. The instruction to separately set or clear whenever their corresponding channel is requesting service,
the mask bits is similar in form to that used with the Request regardless of the mask bit state. If the mask bits are set, soft-
register. Refer to the following diagram and Figure 4 for ware can poll the Status register to determine which channels
details. When reading the Mask register, bits 4-7 will always have DREQs, and selectively clear a mask bit, thus allowing
read as logical ones, and bits 0-3 will display the mask bits of user defined service priority. Status bits 4-7 are updated while
channels 0-3, respectively. The 4 bits of the Mask register the clock is high, and latched on the falling edge. Status Bits
may be cleared simultaneously by using the Clear Mask Reg- 4-7 are cleared upon RESET or Master Clear.
ister command (see software commands section).
Status Register
Mask Register
7
6
5
4
3
2
1
0
BIT NUMBER
7
6
5
4
3
2
1
0
BIT NUMBER
1
1
1
1
1
1
1
1
Channel 0 has reached TC
Channel 1 has reached TC
Channel 2 has reached TC
Channel 3 has reached TC
Channel 0 request
00 Select Channel 0 mask bit
01 Select Channel 1 mask bit
10 Select Channel 2 mask bit
11 Select Channel 3 mask bit
Don’t Care
0
1
Clear mask bit
Set mask bit
All four bits of the Mask register may also be written with a
single command.
Channel 1 request
7
6
5
4
3
2
1
0
BIT NUMBER
Channel 2 request
0
1
Clear Channel 0 mask bit
Set Channel 0 mask bit
Channel 3 request
Don’t Care,
Write
All Ones,
Read
0
1
Clear Channel 1 mask bit
Set Channel 1 mask bit
Temporary Register - The Temporary register is used to
hold data during memory-to-memory transfers. Following the
completion of the transfers, the last byte moved can be read
by the microprocessor. The Temporary register always
contains the last byte transferred in the previous memory-to-
memory operation, unless cleared by a Reset or Master
Clear.
0
1
Clear Channel 2 mask bit
Set Channel 2 mask bit
0
1
Clear Channel 3 mask bit
Set Channel 3 mask bit
OPERATION
A3
A2
A1
A0
IOR
IOW
Read Status Register
Write Command Register
Read Request Register
Write Request Register
Read Command Register
Write Single Mask Bit
Read Mode Register
Write Mode Register
Set First/Last F/F
Clear First/Last F/F
Read Temporary Register
Master Clear
Clear Mode Reg. Counter
Clear Mask Register
Read All Mask Bits
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Write All Mask Bits
FIGURE 4. SOFTWARE COMMAND CODES AND REGISTER CODES
4-201
82C37A
Software Commands
There are special software commands which can be Clear Mode Register Counter - Since only one address
executed by reading or writing to the 82C37A. These com- location is available for reading the Mode registers, an inter-
mands do not depend on the specific data pattern on the nal two-bit counter has been included to select Mode regis-
data bus, but are activated by the I/O operation itself. On ters during read operation. To read the Mode registers, first
read type commands, the data value is not guaranteed. execute the Clear Mode Register Counter command, then
These commands are:
do consecutive reads until the desired channel is read. Read
order is channel 0 first, channel 3 last. The lower two bits on
all Mode registers will read as ones.
Clear First/Last Flip-Flop - This command is executed
prior to writing or reading new address or word count infor-
mation to the 82C37A. This command initializes the flip-flop
to a known state (low byte first) so that subsequent accesses
to register contents by the microprocessor will address
upper and lower bytes in the correct sequence.
External EOP Operation
The EOP pin is a bidirectional, open drain pin which may be
driven by external signals to terminate DMA operation.
Because EOP is an open drain pin an external pull-up resis-
Set First/Last Flip-Flop - This command will set the flip-flop
to select the high byte first on read and write operations to
address and word count registers.
tor to V
is required. The value of the external pull-up
CC
resistor used should guarantee a rise time of less than
125ns. It is important to note that the 82C37A will not accept
external EOP signals when it is in a SI (Idle) state. The
controller must be active to latch EXT EOP. Once latched,
the EXT EOP will be acted upon during the next S2 state,
unless the 82C37A enters an idle state first. In the latter
case, the latched EOP is cleared. External EOP pulses
occurring between active DMA transfers in demand mode
will not be recognized, since the 82C37A is in an SI state.
Master Clear - This software instruction has the same effect
as the hardware Reset. The Command, Status, Request,
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. The 82C37A will enter the idle cycle.
Clear Mask Register - This command clears the mask bits
of all four channels, enabling them to accept DMA requests.
SIGNALS
FIRST/LAST
FLIP-FLOP
STATE
DATA
BUS
DB0-DB7
CHANNEL
REGISTER
OPERATION
CS IOR IOW A3
A2
A1
A0
0
Base and Current Address
Write
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
Current Address
Read
Write
Read
Base and Current Word
Count
Current Word Count
1
2
3
Base and Current Address
Current Address
Write
Read
Write
Read
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
Base and Current Word
Count
Current Word Count
Base and Current Address
Current Address
Write
Read
Write
Read
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
Base and Current Word
Count
Current Word Count
Base and Current Address
Current Address
Write
Read
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
A0-A7
A8-A15
A0-A7
A8-A15
W0-W7
W8-W15
W0-W7
W8-W15
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
0
1
Base and Current Word
Count
Current Word Count
Write
Read
FIGURE 5. WORD COUNT AND ADDRESS REGISTER COMMAND CODES
4-202
82C37A
address. Hold Acknowledge (HLDA) and Address Enable
(AEN) are “ORed” together to insure that the DMA controller
does not have bus contention with the microprocessor.
Application Information
Figure 6 shows an application for a DMA system utilizing the
82C37A DMA controller and the 80C88 Microprocessor. In
this application, the 82C37A DMA controller is used to Operation
improve system performance by allowing an I/O device to
transfer data directly to or from system memory.
A DMA request (DREQ) is generated by the I/O device. After
receiving the DMA request, the DMA controller will issue a
Hold request (HRQ) to the processor. The system busses
are not released to the DMA controller until a Hold Acknowl-
edge signal is returned to the DMA controller from the
80C88 processor. After the Hold Acknowledge has been
received, addresses and control signals are generated by
the DMA controller to accomplish the DMA transfers. Data is
transferred directly from the I/O device to memory (or vice
versa) with IOR and MEMW (or MEMR and IOW) being
active. Note that data is not read into or driven out of the
DMA controller in I/O-to-memory or memory-to-I/O data
transfers.
Components
The system clock is generated by the 82C84A clock driver
and is inverted to meet the clock high and low times required
by the 82C37A DMA controller. The four OR gates are used
to support the 80C88 Microprocessor in minimum mode by
producing the control signals used by the processor to
access memory or I/O. A decoder is used to generate chip
select for the DMA controller and memory. The most signifi-
cant bits of the address are output on the address/data bus.
Therefore, the 82C82 octal latch is used to demultiplex the
V
CC
MEMCS
HLDA
DECODER
82C37A
ADDRESS BUS
82C84A
OR
CLK
CS
EOP
AX
HLDA
HRQ
82C85
HLDA
ALE
AD0
STB
OE
ADSTB
IOR
IOW
CLK
AEN
OE
82C82
STB
82C82
V
MEMR
MEMW
HRQ
CC
AD7
M/IO
RD
A0-7
DATA BUS
ADDRESS BUS
DATA BUS
DB0-7 DREQ0
V
WR MN/MX
80C88
DACK
CC
47kΩ
MEMR
CS
DREQ
MEMW
IOR
MEMORY
I/O
DEVICE
MEMCS
MEMR
MEMW
IOR
IOW
IOW
NOTE: The address lines need pull-up resistors.
FIGURE 6. APPLICATION FOR DMA SYSTEM
4-203
82C37A
Figure 7 shows an application for a DMA system using the for A8-A15 from the DMA controller’s data bus is on the local
82C37A DMA controller and the 80C286 Microprocessor.
80C286 address bus so that memory chip selects may still
be generated during DMA transfers. The transceiver on A0-
A7 is controlled by AEN and is not necessary, but may be
used to drive a heavily loaded system address bus during
transfers. The data bus transceivers simply isolate the DMA
controller from the local microprocessor bus and allow pro-
gramming on the upper or lower half of the data bus.
In this application, the system clock comes from the 82C284
clock generator PCLK signal which is inverted to provide
proper READY setup and hold times to the DMA controller in
an 80C286 system. The Read and Write signals from the
DMA controller may be wired directly to the Read/Write con-
trol signals from the 82C288 Bus Controller. The octal latch
CHIP SELECT
TO MEMORY/
PERIPHERALS
LATCH
DECODE
80C286
A0-A23
A0 - A23
MEMR
MEMW
MEMORY
SYSTEM
BUS
TRANSCEIVER
MEMCS
D0-D15
D0 - D15
READY
IOR
IOW
HLD
I/O
DEVICE
HLDA
CLK
DREQ
CS
LATCH
STB
TRANSCEIVER
TRANS-
CEIVER
TRANS-
CEIVER
DACK
T/R
OE
82C288
OE
IORC
IOWC
IOR
IOW
AEN
MRDC
MWTC
MEMR
MEMW
D0-D7
V
CC
CLK
82C284
CLK
AEN
ADSTB
HRQ
HLDA
CLK
EOP D0-D7
82C37A
A0-A7
IOR
IOW
MEMR
MEMW
IOR
IOW
MEMR
MEMW
TO CORRESPONDING
82C288 SIGNALS AND
MEMORY/PERIPHERALS
PCLK
READY
DREQ 0-3
DACK 0-3
READY
FIGURE 7. 80C286 DMA APPLICATION
4-204
82C37A
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance (Typical)
θJA ( C/W) θJC ( C/W)
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
+0.5V
CC
CERDIP Package . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
PLCC Package . . . . . . . . . . . . . . . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature Ceramic Package . . . . . . . +175 C
Maximum Junction Temperature Plastic Package. . . . . . . . . +150 C
Maximum Lead Temperature Package
(Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 C
(PLCC - Lead Tips Only)
50
65
50
46
10
14
N/A
N/A
Operating Conditions
o
o
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
o
o
o
o
C82C37A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C
o
o
I82C37A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
o
o
o
M82C37A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2325 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
o
DC Electrical Specifications
V
= +5.0 ±10%, T = 0 C to +70 C (C82C37A)
CC A
o
o
T = -40 C to +85 C (I82C37A)
A
o
o
T = -55 C to +125 C (M82C37A)
A
SYMBOL
PARAMETER
MIN
2
MAX
UNITS
TEST CONDITIONS
C82C37A, I82C37A
VIH
Logical One Input Voltage
-
-
v
2.2
-
V
V
V
V
V
V
V
M82C37A
VIL
Logical Zero Input Voltage
0.8
-
VIHC
VILC
VOH
CLK Input Logical One Voltage
CLK Input Logical Zero Voltage
Output HIGH Voltage
V
V
-0.8
CC
-
0.8
-
3.0
IOH = -2.5mA
-0.4
-
IOH = -100µA
CC
VOL
Output LOW Voltage
-
0.4
IOL = +2.5mA all output except EOP,
IOL = +3.2mA for EOP pin 36 only.
II
Input Leakage Current
Output Leakage Current
-1
+1
µA
µA
VIN = GND or V , Pins 6, 7, 11-13, 16-19
CC
IO
-10
+10
VOUT = GND or V , Pins 1-4, 21-23, 26-30,
CC
32-40
ICCSB
ICCOP
Standby Power Supply
Current
-
-
10
2
µA
V
= 5.5V, VIN = V
or GND, Outputs
CC
CC
Open
Operating Power Supply
Current
mA/MHz
V
= 5.5V, CLK FREQ = Maximum,
CC
VIN = V
or GND, Outputs Open
CC
o
Capacitance T = +25 C
A
SYMBOL
CIN
PARAMETER
TYP
UNITS
TEST CONDITIONS
Input Capacitance
Output Capacitance
I/O Capacitance
25
40
25
pF
pF
pF
FREQ = 1MHz, All measurements are
referenced to device GND
COUT
CI/O
4-205
82C37A
o
o
AC Electrical Specifications
V
= +5.0V ±10%, GND = 0V, T = 0 C to +70 C (C82C37A),
A
CC
o
o
T = -40 C to +85 C (I82C37A),
A
o
o
T = -55 C to +125 C (M82C37A)
A
82C37A-5
82C37A
82C37A-12
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
DMA (MASTER) MODE
(1)TAEL
(2)TAET
(3)TAFAB
(4)TAFC
(5)TAFDB
AEN HIGH from CLK LOW (S1) Delay
Time
-
-
-
-
-
175
130
90
-
-
-
-
-
105
80
-
-
-
-
-
50
50
55
50
90
ns
ns
ns
ns
ns
AEN LOW from CLK HIGH (SI) Delay
Time
ADR Active to Float Delay from CLK
HIGH
55
READ or WRITE Float Delay from
CLK HIGH
120
170
75
DB Active to Float Delay from CLK
HIGH
135
(6)TAHR
(7)TAHS
(8)TAHW
(9)TAK
ADR from READ HIGH Hold Time
DB from ADSTB LOW Hold Time
ADR from WRITE HIGH Hold Time
TCY-100
TCL-18
TCY-65
-
-
TCY-75
TCL-18
TCY-65
-
-
TCY-65
TCL-18
TCY-50
-
-
-
ns
ns
ns
ns
-
-
-
-
-
DACK Valid from CLK LOW
Delay Time
170
105
69
EOP HIGH from CLK HIGH
Delay Time
-
-
170
100
-
-
105
60
-
-
90
35
ns
ns
EOP LOW from CLK HIGH
Delay Time
(10)TASM
(11)TASS
(12)TCH
(13)TCL
ADR Stable from CLK HIGH
DB to ADSTB LOW Setup Time
CLK HIGH Time (Transitions 10ns)
CLK LOW Time (Transitions 10ns)
CLK Cycle Time
-
TCH-20
70
110
-
TCH-20
55
60
-
50
ns
ns
ns
ns
ns
ns
-
-
TCH-20
-
-
-
30
30
80
-
-
50
-
-
43
-
-
-
-
(14)TCY
(15)TDCL
200
-
125
-
CLK HIGH to READ or WRITE LOW
Delay
190
130
120
(16)TDCTR
(17)TDCTW
(18)TDQ
READ HIGH from CLK HIGH (S4)
Delay Time
-
-
-
190
130
120
-
-
-
115
80
-
-
-
80
70
30
ns
ns
ns
WRITE HIGH from CLK HIGH (S4)
Delay Time
HRQ Valid from CLK HIGH
Delay Time
75
(19)TEPH
(20)TEPS
EOP Hold Time from CLK LOW (S2)
EOP LOW to CLK LOW Setup Time
90
40
-
-
90
25
-
-
50
0
-
-
ns
ns
4-206
82C37A
o
o
AC Electrical Specifications
V
= +5.0V ±10%, GND = 0V, T = 0 C to +70 C (C82C37A),
A
CC
o
o
T = -40 C to +85 C (I82C37A),
A
o
o
T = -55 C to +125 C (M82C37A) (Continued)
A
82C37A-5
82C37A
82C37A-12
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
(21)TEPW
EOP Pulse Width
220
-
135
-
50
-
-
ns
(22)TFAAB
(23)TFAC
ADR Valid Delay from CLK HIGH
-
-
110
150
-
-
60
90
50
50
ns
ns
READ or WRITE Active from
CLK HIGH
-
(24)TFADB
(25)THS
DB Valid Delay from CLK HIGH
-
110
-
60
-
-
45
-
ns
ns
ns
HLDA Valid to CLK HIGH Setup Time
75
0
-
-
45
0
10
0
(26)TIDH
Input Data from MEMR HIGH
Hold Time
-
-
(27)TIDS
Input Data to MEMR HIGH
Setup Time
155
15
-
-
90
15
-
-
45
-
-
ns
ns
(28)TODH
Output Data from MEMW HIGH
Hold Time
TCY-50
(29)TODV
(30)TQS
Output Data Valid to MEMW HIGH
TCY-35
0
-
-
TCY-35
0
-
-
TCY-10
0
-
-
ns
ns
DREQ to CLK LOW (SI, S4)
Setup Time
(31)TRH
CLK to READY LOW Hold Time
READY to CLK LOW Setup Time
20
60
-
-
-
20
35
-
-
-
10
15
-
-
-
ns
ns
ns
(32)TRS
(33)TCLSH
ADSTB HIGH from CLK LOW
Delay Time
80
70
70
(34)TCLSL
ADSTB LOW from CLK LOW
Delay Time
-
120
-
120
-
60
ns
(35)TWRRD
(36)TRLRH
(37)TSHSL
READ HIGH Delay from WRITE HIGH
READ Pulse Width, Normal Timing
ADSTB Pulse Width
0
2TCY-60
TCY-80
2TCY-100
TCY-100
TCY-60
17
-
-
-
-
-
-
-
-
-
-
-
-
0
2TCY-60
TCY-50
2TCY-85
TCY-85
TCY-60
17
-
-
-
-
-
-
-
-
-
-
-
-
5
2TCY-55
TCY-35
2TCY-80
TCY-80
TCY-55
17
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(38)TWLWHA Extended WRITE Pulse Width
(39)TWLWH
(40)TRLRHC
(56)TAVRL
(57)TAVWL
(58)TRHAL
(59)TRHSH
(60)TWHSH
(61)TDVRL
WRITE Pulse Width
READ Pulse Width, Compressed
ADR Valid to READ LOW
ADR Valid to WRITE LOW
READ HIGH to AEN LOW
READ HIGH to ADSTB HIGH
WRITE HIGH to ADSTB HIGH
DACK Valid to READ LOW
7
7
7
15
15
15
13
13
13
15
15
15
25
25
25
4-207
82C37A
o
o
AC Electrical Specifications
V
= +5.0V ±10%, GND = 0V, T = 0 C to +70 C (C82C37A),
A
CC
o
o
T = -40 C to +85 C (I82C37A),
A
o
o
T = -55 C to +125 C (M82C37A) (Continued)
A
82C37A-5
82C37A
82C37A-12
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
(62)TDVWL
DACK Valid to WRITE LOW
READ HIGH to DACK Inactive
ADR Float to READ LOW
25
-
25
12
-
25
12
-
ns
(63)TRHDI
(64)TAZRL
12
-
-
-
-
-
-
ns
ns
-2.5
-2.5
-2.5
PERIPHERAL (SLAVE) MODE
(41)TAR
ADR Valid or CS LOW to READ LOW
10
0
-
10
0
-
0
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
(42)TAWL
(43)TCWL
(44)TDW
(45)TRA
ADR Valid to WRITE LOW Setup Time
CS LOW to WRITE LOW Setup Time
Data Valid to WRITE HIGH Setup Time
ADR or CS Hold from READ HIGH
Data Access from READ
-
-
0
-
-
0
-
-
0
-
150
0
100
0
60
0
-
-
-
-
(46)TRDE
(47)TRDF
(48)TRSTD
-
140
85
-
-
120
85
-
-
80
55
-
DB Float Delay from READ HIGH
5
5
5
Power Supply HIGH to RESET LOW
Setup Time
500
500
500
(49)TRSTS
(50)TRSTW
(51)TRW
RESET to First IOR or IOW
RESET Pulse Width
2TCY
300
200
0
-
-
-
-
-
2TCY
300
155
0
-
-
-
-
-
2TCY
300
85
-
-
-
-
-
ns
ns
ns
ns
ns
READ Pulse Width
(52)TWA
ADR from WRITE HIGH Hold Time
0
(53)TWC
CS HIGH from WRITE HIGH
Hold Time
0
0
0
(54)TWD
Data from WRITE HIGH Hold Time
WRITE Pulse Width
10
-
-
10
-
-
10
45
-
-
ns
ns
(55)TWWS
150
100
4-208
82C37A
Timing Waveforms
CS
TCWL
(43)
TWC (53)
IOW
TWWS
(55)
TAWL
(42)
TWA (52)
TWD (54)
A0 - A3
INPUT VALID
TDW
(44)
DB0 - DB7
INPUT VALID
FIGURE 8. SLAVE MODE WRITE
NOTE: Successive WRITE accesses to the 82C37A must allow at least TCY as recovery time between accesses. A TCY recovery time must
be allowed before executing a WRITE access after a READ access.
CS
A0 - A3
IOR
ADDRESS MUST BE VALID
TAR
(41)
TRA (45)
TRW
(51)
TRDE
(46)
TRDF
(47)
DB0 -DB7
DATA OUT VALID
FIGURE 9. SLAVE MODE READ
NOTE: Successive READ accesses to the 82C37A must allow at least TCY as recovery time between accesses. A TCY recovery time must
be allowed before executing a READ access after a WRITE access.
4-209
82C37A
Timing Waveforms (Continued)
SI
SI
S0
S0
S1
S2
S3
S4
S2
S3
S4
SI
SI
SI
CLK
TCY
(14)
TCL (13)
TQS
(30)
TQS
(30)
TCH
(12)
DREQ
TDQ
(18)
TDQ
(18)
HRQ
THS
(25)
HLDA
TAET
(2)
TAEL
(1)
TEPS
AEN
(20)
TCLSL
(34)
TRHAL
(58)
TEPH
(19)
TCLSH
(33)
TSHSL
(37)
ADSTB
TASS
(11)
TAK (9)
TFADB
(24)
TAHS
(7)
DB0-DB7
TASM
(10)
TAHW
(8)
A8-A15
TAFDB
(5)
TAFAB (3)
TAHW (8)
TFAAB
(22)
A0-A7
ADDRESS VALID
ADDRESS VALID
TAHR (6)
TAHR
(6)
(64)
TAZRL
TAK
(9)
TRHDI (63)
TDCTR
TAVRL
(56)
TDCL
(15)
TRLRH
(36)
DACK
READ
TDCL
(15)
(16)
TAFC (4)
TDCTR (16)
TFAC
(23)
TWRRD
(35)
TDCTW
(17)
TAVWL
(57)
TDVAL (61)
TDCL (15)
TDCTW (17)
TWLWH (39)
WRITE
(FOR EXTENDED WRITE)
TAK (9)
TAK (9)
TDVWL TWLWHA
(62) (38)
TDCL
(15)
INT EOP
(FOR EXTENDED WRITE)
TEPW (21)
EXT EOP
FIGURE 10. DMA TRANSFER
4-210
82C37A
Timing Waveforms (Continued)
S0
S11
S12
S13
S14
S21
S22
S23
S24
S11/SI
CLK
TCLSH
(33)
(34)
TCLSL
(33)
TCLSH
(34)
TCLSL
(33)
TCLSH
TWHSH
(60)
ADSTB
A0-A7
(7)
TAHS
(59) TRHSH
TAHS
(7)
TAFAB
(3)
TFAAB (22)
TASS (11)
ADDRESS VALID
ADDRESS VALID
TAFDB
(5)
(5) TAFDB
TASS
(11)
TFADB (24)
DB0-DB7
MEMR
A8-A15
IN
A8-A15
OUT
(24)
TODH (28)
TDCL
(15)
(16) TDCTR
TAZRL
TFADB
TOVD
(29)
TAFC
(4)
TIDH (26)
TFAC (23)
TIDS
(27)
(64)
TDCTW (17)
TDCL
(15)
TDCL
(15)
TAFC
(4)
TFAC (23)
MEMW
EOP
TAK
(9)
EXTENDED WRITE
(19) TEPH
TAK
(9)
TEPS (20)
TEPW
(21)
EXT EOP
FIGURE 11. MEMORY-TO-MEMORY TRANSFER
S2
S3
SW
SW
S4
CLK
(16)
TDCTR
(15)
TDCL
READ
(15)
TDCL
(17)
TDCTW
(15)TDCL
WRITE
READY
EXTENDED WRITE
(31)TRH
(32)TRS
(32)TRS
(31)
TRH
FIGURE 12. READY
NOTE: READY must not transition during the specified setup and hold times.
4-211
82C37A
Timing Waveforms (Continued)
S2
S4
S2
S4
CLK
A0-A7
READ
(10)
(10)
TASM
TASM
VALID
TDCTR
VALID
(15)
TDCL
TDCL
(15)
TDCTR
(16)
(16)
TRLRHC
(40)
TDCTW
(17)
TDCTW
(17)
WRITE
READY
TRH (31)
TRH (31)
TRS (32)
TRS (32)
FIGURE 13. COMPRESSED TRANSFER
(48) TRSTD
(50) TRSTW
V
CC
RESET
(49) TRSTS
IOR OR IOW
FIGURE 14. RESET
AC Test Circuits
AC Testing Input, Output Waveforms
V1
R1
VIH + 0.4V
VOH
INPUT
OUTPUT
1.5V
1.5V
VIL - 0.4V
VOL
OUTPUT FROM
DEVICE UNDER
TEST
TEST POINT
C1 (NOTE)
Z → L OR H
L OR H → Z
VOH
VOL
VOH
VO -0.45
0.45
2.0V
0.8V
OUTPUT
OUTPUT
VOL
NOTE: Includes STRAY and FIXTURE Capacitance
TEST CONDITION DEFINITION TABLE
NOTE: AC Testing: All AC Parameters tested as per test circuits.
Input RISE and FALL times are driven at Ins/V. CLK input
must switch between VIHC +0.4V and VILC -0.4V
PINS
All Outputs Except EOP
EOP
V1
R1
C1
1.7V
520Ω
1.6kΩ
100pF
50pF
V
CC
4-212
82C37A
Burn-In Circuits
MD82C37A CERDIP
R1
R2
R1
R1
R1
R1
R3
R1
R1
R1
R2
R2
R2
R2
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R2
R1
R2
VCC
DO5
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC/2
VCC/2
VCC/2
VCC/2
3
VCC/2
VCC/2
A
VCC/2
A
4
5
VCC
6
7
DO5
DO1
VCC
VCC/2
8
VCC/2
VCC/2
DO5
9
DO0
B
10
11
12
13
14
15
16
17
18
19
20
R2
R2
R2
R2
R2
R1
R1
R2
R2
R2
DO2
DO3
DO4
F10
F1
DO6
VCC/2
VCC/2
F12
F9
VCC/2
F13
VCC/2
F8
F14
F15
DO4
F7
GND
MR82C37A CLCC
V
V
CC
CC
D1
C1
A
B
44
43 42 41 40
6
5
4
3
2
1
C1
OPEN
OPEN
DO5
7
39
38
37
36
35
34
33
32
31
30
29
V
8
CC
9
DO1
10
11
12
13
14
15
16
17
VCC/2
VCC/2
V
CC
B
VCC/2
DO2
DO5
F1
DO3
DO4
F10
D06
VCC/2
OPEN
F9
OPEN
18 19 20 21 22 23 24 25 26 27 28
NOTES:
1. V
= 5.5V ± 0.5V
7. C1 = 0.01µF minimum
8. C2 = 0.1µF minimum
9. D1 = 1N4002
CC
2. VIH = 4.5V ± 10%
3. VIL = -0.2V to 0.4V
4. GND = 0V
10. F0 = 100kHz ±10%
5. R1 = 1.2kΩ ±5%
6. R2 = 47kΩ ±5%
11. F1 = F0/2, F2 = F1/2,..., F15 = F14/2
12. DO0 - DO6 are outputs from the 82C82 Octal Latching Bus Driver
4-213
82C37A
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
Type: Nitrox
Thickness: 10kÅ ± 3kÅ
148 x 159 x 19 ±1mils
(3760- x 4040 x 525µm)
WORST CASE CURRENT DENSITY:
0.6 x 10 A/cm
5
2
METALLIZATION:
Type: SiAlCu
Thickness: Metal 1: 8kÅ ± 0.75kÅ
Thickness: Metal 2: 12kÅ ± 1.0kÅ
Metallization Mask Layout
82C37A
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-214
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