ISL12022MIBZ_技术文档

Low Power RTC with Battery Backed SRAM,

Integrated ±5ppm Temperature Compensation and

Auto Daylight Saving

ISL12022M

Features

• Embedded 32.768kHz Quartz Crystal in the Package

The ISL12022M device is a low power real time clock

(RTC) with an embedded temperature sensor and

crystal. Device functions include oscillator compensation,

clock/calendar, power fail and low battery monitors,

brownout indicator, one-time, periodic or polled alarms,

intelligent battery backup switching, Battery Reseal™

function and 128 bytes of battery-backed user SRAM.

The device is offered in a 20 Ld SOIC module that

contains the RTC and an embedded 32.768kHz quartz

crystal. The calibrated oscillator provides less than

±5ppm drift over the full -40°C to +85°C temperature

range.

• 20 Ld SOIC Package (for DFN version, refer to the

ISL12020M)

• Calendar

• On-chip Oscillator Temperature Compensation

• 10-bit Digital Temperature Sensor Output

• 15 Selectable Frequency Outputs

• Interrupt for Alarm or 15 Selectable Frequency

Outputs

• Automatic Backup to Battery or Supercapacitor

• VDD and Battery Status Monitors

The RTC tracks time with separate registers for hours,

minutes, and seconds. The calendar registers track date,

month, year and day of the week and are accurate

through 2099, with automatic leap year correction.

• Battery Reseal™ Function to Extend Battery Shelf

Life

• Power Status Brownout Monitor

• Time Stamp for Battery Switchover

• 128 Bytes Battery-Backed User SRAM

Daylight Savings time adjustment is done automatically,

using parameters entered by the user. Power fail and

battery monitors offer user-selectable trip levels. The

time stamp function records the time and date of

2

• I C-Bus™

• RoHS Compliant

switchover from V

to V

power, and also from V

DD

BAT

to V

DD

power.

Applications*(see page 30)

• Utility Meters

Related Literature*(see page 30)

• See AN1549 “Addressing Power Issues in Real Time

Clock Applications”

• POS Equipment

• Printers and Copiers

• Digital Cameras

Typical Application Circuit

Performance Curve

OSCILLATOR ERROR vs TEMPERATURE

5

1

20

19

18

17

16

15

14

13

12

11

NC

4

3

2

1

2

NC

3

NC

4

3.3V

NC

5

NC

C1

0.1µF

SCHOTTKY DIODE

BAT54

6

R1

R2

R3

V = 5.5V

BAT

GND

VBAT

GND

VDD

10k 10k 10k

0

-1

-2

-3

-4

-5

7

BATTERY

3.0V

C2

8

V

= 2.7V

DD

60

GND IRQ/FOUT

VDD

SCL

0.1µF

9

MCU

NC

SCL

INTERFACE

10

V

= 3.3V

SDA

GND

DD

ISL12022M

IRQ/FOUT

-40

-20

0

20

40

80

TEMPERATURE (°C)

June 4, 2010

FN6668.7

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

2

I C Bus is a registered trademark owned by NXP Semiconductors Netherlands, B.V.

All other trademarks mentioned are the property of their respective owners.

ISL12022M

Block Diagram

SDA

SCL

SECONDS

MINUTES

HOURS

BUFFER

2

I C

CONTROL

LOGIC

REGISTERS

INTERFACE

SCL

BUFFER

DAY OF WEEK

DATE

CRYSTAL

OSCILLATOR

RTC

DIVIDER

MONTH

V

DD

YEAR

POR

FREQUENCY

OUT

ALARM

CONTROL

REGISTERS

V

TRIP

+

-

USER

SRAM

SWITCH

INTERNAL

SUPPLY

V

BAT

IRQ/F

OUT

FREQUENCY

CONTROL

TEMPERATURE

SENSOR

GND

Pin Configuration

ISL12022M

(20 LD SOIC)

TOP VIEW

NC

1

20

19

18

17

16

15

14

13

12

11

NC

GND

NC

2

3

4

NC

5

NC

6

GND

V

7

V

BAT

GND

NC

DD

8

IRQ/F

OUT

9

SCL

10

NC

SDA

Pin Descriptions

NUMBER

SYMBOL

DESCRIPTION

No Connection. Do not connect to a signal or supply voltage.

1, 2, 3, 4, 5,

9, 10, 16,

17, 18, 19,

20

NC

7

V

Backup Supply. This input provides a backup supply voltage to the device. VBAT supplies power to

the device in the event that the VDD supply fails. This pin can be connected to a battery, a

supercapacitor or tied to ground if not used. See the Battery Monitor parameter in the “DC Operating

Characteristics-RTC” table on page 4. This pin should be tied to ground if not used.

BAT

11

SDA

Serial Data. SDA is a bi-directional pin used to transfer data into and out of the device. It has an

open drain output and may be OR’ed with other open drain or open collector outputs. The input buffer

is always active (not gated) in normal mode.

An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time

of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz

2

I C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated.

FN6668.7

June 4, 2010

2

ISL12022M

Pin Descriptions(Continued)

NUMBER

SYMBOL

DESCRIPTION

Serial Clock. The SCL input is used to clock all serial data into and out of the device. The input buffer

12

SCL

on this pin is always active (not gated). It is disabled when the backup power supply on the V

is activated to minimize power consumption.

BAT

13

IRQ/F

OUT

Interrupt Output/Frequency Output (Default 32.768kHz frequency output). This dual function pin

can be used as an interrupt or frequency output pin. The IRQ/FOUT mode is selected via the frequency

out control bits of the control/status register. Interrupt Mode. The pin provides an interrupt signal

output. This signal notifies a host processor that an alarm has occurred and requests action. It is an

open drain active low output. Frequency Output Mode. The pin outputs a clock signal, which is

2

related to the crystal frequency. The frequency output is user selectable and enabled via the I C bus.

It is an open drain output. The output is open drain and requires a pull-up resistor.

14

6, 8, 15

V

Power Supply. Chip power supply and ground pins. The device will operate with a power supply from

DD

GND

VDD = 2.7V to 5.5VDC. A 0.1µF capacitor is recommended on the V pin to ground.

DD

Ordering Information

PART NUMBER

(Note 3)

PART

MARKING

V

RANGE

(V)

TEMP RANGE

(°C)

PACKAGE

(RoHS COMPLIANT)

PKG.

DWG. #

DD

ISL12022MIBZ (Note 2)

ISL12022MIBZ

2.7 to 5.5

-40 to +85

20 Ld SOIC

M20.3

ISL12022MIBZ-T (Notes 1, 2) ISL12022MIBZ

20 Ld SOIC (Tape and Reel) M20.3

1. Please refer to TB347 for details on reel specifications.

2. These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus

anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by exemption 7 (lead in high melt

temp solder for internal connections) and exemption 5 (lead in piezoelectric elements). These Intersil RoHS compliant

products are compatible with both SnPb and Pb-free soldering operations. These Intersil RoHS compliant products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12022M. For more information on MSL please

see techbrief TB363.

FN6668.7

June 4, 2010

3

ISL12022M

Addresses [07h to 0Fh].................................. 15

Table of Contents

Interrupt Control Register (INT) ...................... 16

Power Supply Control Register (PWR_VDD)....... 17

Battery Voltage Trip Voltage Register (PWR_VBAT)..... 17

Initial AT and DT Setting Register (ITRO).......... 17

ALPHA Register (ALPHA)................................. 19

BETA Register (BETA) ................................... 19

Final Analog Trimming Register (FATR)............. 20

Final Digital Trimming Register (FDTR) ............. 20

ALARM Registers (10h to 15h)......................... 20

Time Stamp VDD to Battery Registers (TSV2B)......... 21

Time Stamp Battery to VDD Registers (TSB2V)......... 21

DST Control Registers (DSTCR) ....................... 22

TEMP Registers (TEMP)................................... 23

NPPM Registers (NPPM).................................. 23

XT0 Registers (XT0)....................................... 23

ALPHA Hot Register (ALPHAH)......................... 24

Typical Application Circuit ................................. 1

Performance Curve............................................ 1

Block Diagram ................................................... 2

Pin Descriptions ................................................ 2

Absolute Maximum Ratings .............................. 5

Thermal Information ........................................ 5

Electrical Specifications .................................... 5

2

I C Interface Specifications .............................. 6

SDA vs SCL Timing............................................. 8

Symbol Table..................................................... 8

Typical Performance Curves ............................. 9

General Description......................................... 10

User Registers (Accessed by Using Slave Address

1010111x) ................................................... 24

Addresses [00h to 7Fh].................................. 24

2

Functional Description..................................... 11

I C Serial Interface......................................... 24

Power Control Operation ................................. 11

Protocol Conventions ...................................... 24

Device Addressing........................................... 25

Write Operation .............................................. 26

Read Operation ............................................... 26

Application Section ......................................... 26

Normal Mode (V ) to Battery Backup Mode (V

)... 11

DD BAT

Battery Backup Mode (V

) to Normal Mode (V )... 11

BAT DD

Power Failure Detection .................................. 11

Brownout Detection........................................ 11

Battery Level Monitor...................................... 11

Real Time Clock Operation............................... 12

Single Event and Interrupt .............................. 12

Frequency Output Mode .................................. 12

General Purpose User SRAM ............................ 12

I C Serial Interface ........................................ 12

Oscillator Compensation.................................. 12

Battery Backup Details................................... 26

Layout Considerations.................................... 26

Measuring Oscillator Accuracy ......................... 27

Temperature Compensation Operation.............. 27

Daylight Savings Time (DST) Example.............. 28

2

Register Descriptions ...................................... 12

Revision History.............................................. 29

Products.......................................................... 30

M20.3 ............................................................. 31

Real Time Clock Registers ............................... 14

Addresses [00h to 06h]................................... 14

Control and Status Registers (CSR)................. 15

FN6668.7

June 4, 2010

4

ISL12022M

Absolute Maximum Ratings

Thermal Information

Voltage on V , V

DD

(Respect to Ground) . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on SCL and SDA pins

(Respect to Ground) . . . . . . . . . . . -0.3V to V

ESD Rating

Human Body Model

and IRQ/F

OUT

pins

Thermal Resistance (Typical)

20 Lead SOIC (Notes 4, 5)

θ

(°C/W)

70

θ

JC

(°C/W)

35

BAT

JA

Storage Temperature . . . . . . . . . . . . . . . -40°C to +85°C

Pb-Free Reflow Profile (Note 6) . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

+ 0.3V

DD

(Per MIL-STD-883 Method 3014) . . . . . . . . . . . >3kV

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . .>300V

Charged Device Model . . . . . . . . . . . . . . . . . . .>2200V

Latch-up . . . . . . . . . . . . . . . . . . . . . . . . Class II Level A,

passed at +85°C ambient with the Level A latch-up

criteria of 100mA or 1.5*V

input

MAX

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief

JA

TB379 for details.

5. For θ , the “case temp” location is on top of the package and measured in the center of the package between pins 6 and 15.

JC

6. The ISL12022M Oscillator Initial Accuracy can change after solder reflow attachment. The amount of change will depend on

the reflow temperature and length of exposure. A general rule is to use only one reflow cycle and keep the temperature and

time as short as possible. Changes on the order of ±1ppm to ±3ppm can be expected with typical reflow profiles.

DC Operating Characteristics RTC Test Conditions: V

= +2.7 to +5.5V, T = -40°C to +85°C, unless otherwise

A

DD

stated. Boldface limits apply over the operating temperature range,

-40°C to +85°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

Main Power Supply

CONDITIONS

(Note 15)

(Note 7) (Note 8) (Note 7) UNITS NOTES

V

2.7

1.8

5.5

7

V

DD

V

Battery Supply Voltage

9

BAT

2

I

Supply Current. (I C Not Active,

V

= 5V

= 3V

4.1

3.5

µA

10, 11

DD1

DD

Temperature Conversion Not

6

Active, F

Not Active)

OUT

2

Supply Current. (I C Active,

Temperature Conversion Not

V

= 5V

200

500

400

1.6

µA

10, 11

DD2

DD3

DD

Active, F

Not Active)

out

2

Supply Current. (I C Not Active,

Temperature Conversion Active,

= 5V

120

10, 11

F

Not Active)

OUT

I

Battery Supply Current

= 0V, V

= 3V,

= 3V

1.0

10

BAT

T = +25°C

A

V

= 0V, V

5.0

100

1.0

µA

nA

DD

BAT

I

Battery Input Leakage

= 5.5V, V = 1.8V

BAT

BATLKG

DD

I

Input Leakage Current on SCL

I/O Leakage Current on SDA

Battery Level Monitor Threshold

Brownout Level Monitor Threshold

= 0V, V = V

IH

-1.0

-100

2.0

±0.1

µA

LI

IL

DD

I

= 0V, V = V

IH

1.0

µA

LO

V

+100

2.4

mV

V

BATM

V

PBM

TRIP

V

Mode Threshold

Hysteresis

(Note 15)

2.2

30

50

BAT

TRIP

BAT

V

mV

ppm

°C

13

6

TRIPHYS

V

Hysteresis

BATHYS

ΔFout

Oscillator Stability vs Temperature

Oscillator Stability vs Voltage

Oscillator Initial Accuracy

V

= 3.3V

-5

-3

+5

+3

T

DD

2.7V ≤ V

ΔFout

≤ 5.5V

V

DD

= 3.3V

ΔFout

V

6

I

DD

Temp

Temperature Sensor Accuracy

= V

= 3.3V

±2

13

DD

BAT

FN6668.7

June 4, 2010

5

ISL12022M

DC Operating Characteristics RTC Test Conditions: V

= +2.7 to +5.5V, T = -40°C to +85°C, unless otherwise

A

DD

stated. Boldface limits apply over the operating temperature range,

-40°C to +85°C. (Continued)

MIN

TYP

MAX

SYMBOL

IRQ/F

PARAMETER

CONDITIONS

(Note 7) (Note 8) (Note 7) UNITS NOTES

(OPEN DRAIN OUTPUT)

OUT

V

Output Low Voltage

V

= 5V, I

OL

= 3mA

= 1mA

0.4

V

OL

DD

= 2.7V, I

OL

DD

Power-Down Timing

Test Conditions: V

stated.

= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise

DD

MIN

TYP

MAX

SYMBOL

PARAMETER

Negative Slew Rate

DD

CONDITIONS

(Note 7) (Note 8) (Note 7) UNITS NOTES

V

10 V/ms 12

DDSR-

2

I C Interface Specifications Test Conditions: V

= +2.7 to +5.5V, Temperature = -40°C to +85°C,

unless otherwise specified. Boldface limits apply over the operating temperature

DD

range, -40°C to +85°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 7) (Note8) (Note 7) UNITS NOTES

V

SDA and SCL Input Buffer

LOW Voltage

-0.3

0.3 x

V

IL

V

DD

V

SDA and SCL Input Buffer

HIGH Voltage

0.7 x V

V

+

0.3

IH

DD

Hysteresis

SDA and SCL Input Buffer

Hysteresis

0.05 x

V

13, 14

V

DD

V

SDA Output Buffer LOW

Voltage, Sinking 3mA

V

= 5V, I

DD OL

= 3mA

0

0.02

0.4

10

V

OL

C

SDA and SCL Pin Capacitance T = +25°C, f = 1MHz,

pF

A

V

= 5V, V = 0V,

= 0V

DD

IN

OUT

f

SCL Frequency

400

50

kHz

ns

SCL

t

Pulse Width Suppression

Any pulse narrower than

IN

Time at SDA and SCL Inputs the max spec is

suppressed.

t

SCL Falling Edge to SDA

Output Data Valid

SCLfallingedgecrossing

900

ns

AA

30% of V , until SDA

DD

exits the 30% to 70% of

V

window.

DD

SDA crossing 70% of

during a STOP

t

Time the Bus Must be Free

Before the Start of a New

Transmission

1300

BUF

V

DD

condition, to SDA

crossing 70% of V

DD

during the following

START condition.

t

Clock LOW Time

Clock HIGH Time

Measured at the 30% of

1300

600

ns

LOW

V

crossing.

DD

Measured at the 70% of

crossing.

t

HIGH

V

DD

t

START Condition Setup Time SCL rising edge to SDA

falling edge. Both

600

SU:STA

crossing 70% of V

.

DD

FN6668.7

June 4, 2010

6

ISL12022M

2

I C Interface Specifications Test Conditions: V

= +2.7 to +5.5V, Temperature = -40°C to +85°C,

unless otherwise specified. Boldface limits apply over the operating temperature

DD

range, -40°C to +85°C. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 7) (Note8) (Note 7) UNITS NOTES

t

START Condition Hold Time

From SDA falling edge

600

100

ns

HD:STA

crossing 30% of V

to

DD

SCLfallingedgecrossing

70% of V

.

DD

From SDA exiting the

30% to 70% of V

t

Input Data Setup Time

SU:DAT

DD

window, to SCL rising

edge crossing 30% of

V

DD.

From SCL falling edge

crossing 30% of V to

t

Input Data Hold Time

20

900

ns

HD:DAT

DD

SDA entering the 30% to

70% of V window.

DD

From SCL rising edge

t

STOP Condition Setup Time

600

SU:STO

HD:STO

crossing 70% of V , to

DD

SDA rising edge crossing

30% of V

.

DD

t

STOP Condition Hold Time

Output Data Hold Time

From SDA rising edge to

SCL falling edge. Both

600

0

ns

crossing 70% of V

.

DD

t

From SCL falling edge

DH

crossing 30% of V

,

DD

until SDA enters the

30% to 70% of V

window.

DD

t

SDA and SCL Rise Time

SDA and SCL Fall Time

From 30% to 70% of

20 + 0.1 x

Cb

300

400

ns

pF

kΩ

13, 14

R

V

DD.

t

From 70% to 30% of

20 + 0.1 x

Cb

F

V

DD.

Cb

Capacitive Loading of SDA or Total on-chip and

SCL

10

off-chip

R

SDA and SCL Bus Pull-up

Resistor Off-chip

Maximum is determined

1

PU

by t and t .

R

F

For Cb = 400pF, max is

about 2kΩ~2.5kΩ.

For Cb = 40pF, max is

about 15kΩ~20kΩ

NOTES:

7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits

established by characterization and are not production tested.

8. Specified at +25°C.

9. Temperature Conversion is inactive below V

= 2.7V. Device operation is not guaranteed at V <1.8V.

BAT

10. IRQ/F

inactive.

OUT

> V

11. V

+V

BATHYS

DD

BAT

12. In order to ensure proper timekeeping, the V

specification must be followed.

DD SR-

13. Limits should be considered typical and are not production tested.

2

14. These are I C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate

specification.

15. Minimum V

and/or V

of 1V to sustain the SRAM. The value is based on characterization and it is not tested.

DD

BAT

FN6668.7

June 4, 2010

7

ISL12022M

SDA vs SCL Timing

t

R

F

HIGH

LOW

SCL

t

SU:DAT

t

HD:DAT

t

SU:STA

SU:STO

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

DH

t

AA

SDA

(OUTPUT TIMING)

Symbol Table

EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V

5.0V

= 5V

DD

WAVEFORM

INPUTS

OUTPUTS

Must be steady

Will be steady

FOR V = 0.4V

OL

1533Ω

AND I

= 3mA

OL

SDA

AND

OUT

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

IRQ/F

100pF

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING

THE DEVICE WITH V

= 5.0V

DD

Don’t Care:

Changes Allowed

Changing:

State Not Known

N/A

Center Line is

High Impedance

FN6668.7

June 4, 2010

8

ISL12022M

Typical Performance Curves Temperature is +25°C unless otherwise specified.

1600

1400

1200

1000

800

1050

1000

950

V

= 5.5V

BAT

900

V

= 3.0V

BAT

850

V

= 1.8V

60

BAT

600

800

-40

-20

0

20

40

80

1.8

2.3

2.8

3.3

3.8

4.3

4.8

5.3

V

VOLTAGE (V)

TEMPERATURE (°C)

BAT

FIGURE 2. I

vs V

(V

= 0V)

FIGURE 3. I

vs TEMPERATURE (V

= 0V)

DD

BAT

DD

BAT

4.4

4.2

4.0

3.8

3.6

3.4

3.2

3.0

6

5

4

3

V

= 5.5V

DD

V

= 2.7V

DD

V

= 3.3V

DD

2

2.7

3.2

3.7

4.2

(V)

4.7

5.2

-40

-20

0

20

40

60

80

V

TEMPERATURE (°C)

DD

FIGURE 4. I

vs TEMPERATURE

FIGURE 5. I

vs V

DD

DD1

5

4

6

5

4

3

2

3

V

= 5.5V

BAT

2

1

V

= 3.3V

DD

V

= 5.5V

BAT

0

-1

-2

-3

-4

-5

V

= 2.7V

DD

60

V

= 2.7V

10

DD

V

= 3.3V

DD

-40

-20

0

20

40

80

0.01

0.1

1

100

1k

10k

1M

TEMPERATURE (°C)

FREQUENCY OUTPUT (Hz)

FIGURE 6. OSCILLATOR ERROR vs TEMPERATURE

FIGURE 7. F

vs I

OUT DD

FN6668.7

June 4, 2010

9

ISL12022M

Typical Performance Curves Temperature is +25°C unless otherwise specified. (Continued)

110

100

90

5.5

5.0

4.5

4.0

3.5

3.0

2.5

V

= 5.5V

BAT

F

= 32kHz

OUT

80

70

60

50

F

= 64Hz

V

= 3.0V

DD

OUT

40

F

= 1Hz

OUT

V

= 1.8V

20

DD

30

20

-40

-20

0

40

60

80

-40

-20

0

20

40

60

80

TEMPERATURE (°C)

FIGURE 8. I

vs TEMPERATURE, 3 DIFFERENT F

OUT

FIGURE 9. I

WITH TSE = 1, BTSE = 1 vs

BAT

DD

TEMPERATURE

110

100

90

80

60

V

= 5.5V

BAT

32ppm

0ppm

40

62.5ppm

20

V

= 3.3V

80

DD

0

70

-20

-40

-60

-80

60

V

= 2.7V

0

DD

-61.5ppm

-31ppm

40

50

40

-40

-20

20

40

60

80

-40

-20

0

20

60

80

TEMPERATURE (°C)

FIGURE 10. I

WITH TSE = 1 vs TEMPERATURE

FIGURE 11. OSCILLATOR CHANGE vs TEMPERATURE

AT DIFFERENT AGING SETTINGS (IATR)

(BETA SET FOR 1ppm STEPS)

DD

available by checking the Status Register, or the device

can be configured to provide a hardware interrupt via the

General Description

The ISL12022M device is a low power real time clock

(RTC) with embedded temperature sensor and crystal.

It contains crystal frequency compensation circuitry

over the operating temperature range good to ±5ppm

accuracy. It also contains a clock/calendar with Daylight

Savings Time (DST) adjustment, power fail and low

battery monitors, brownout indicator, 1 periodic or

polled alarm, intelligent battery backup switching and

128 Bytes of battery-backed user SRAM.

IRQ/F

pin. There is a repeat mode for the alarm

OUT

allowing a periodic interrupt every minute, every hour,

every day, etc.

The device also offers a backup power input pin. This

V

pin allows the device to be backed up by battery or

BAT

supercapacitor with automatic switchover from V

to

DD

= 2.7V

V

. The ISL12022M device is specified for V

BAT DD

to 5.5V and the clock/calendar portion of the device

remains fully operational in battery backup mode down

The oscillator uses an internal 32.768kHz crystal. The

real time clock tracks time with separate registers for

hours, minutes and seconds. The device has calendar

registers for date, month, year and day of the week. The

calendar is accurate through 2099, with automatic leap

year correction. In addition, the ISL12022M can be

programmed for automatic Daylight Saving Time (DST)

adjustment by entering local DST information.

to 1.8V (Standby Mode). The V

BAT

level is monitored and

reported against preselected levels. The first report is

registered when the V level falls below 85% of

BAT

nominal level; the second level is set for 75%. Battery

levels are stored in PWR_V registers.

BAT

The ISL12022M offers a “Brownout” alarm once the V

DD

falls below a pre-selected trip level. This allows system

Micro to save vital information to memory before

complete power loss. There are six V levels that

could be selected for initiation of the Brownout alarm.

The ISL12022M’s alarm can be set to any clock/calendar

value for a match. For example, every minute, every

Tuesday or at 5:23 AM on March 21. The alarm status is

DD

FN6668.7

June 4, 2010

10

ISL12022M

Functional Description

Power Control Operation

BATTERY BACKUP

MODE

V

DD

The power control circuit accepts a V

and a V

BAT

DD

V

BAT

3.0V

2.2V

input. Many types of batteries can be used with Intersil

RTC products. For example, 3.0V or 3.6V Lithium

batteries are appropriate, and battery sizes are available

that can power the ISL12022M for up to 10 years.

Another option is to use a supercapacitor for applications

V

TRIP

V

+ V

TRIPHYS

TRIP

where V

is interrupted for up to a month. See the

DD

FIGURE 13. BATTERY SWITCHOVER WHEN V

>

BAT

“Application Section” on page 26 for more information.

V

TRIP

Normal Mode (V ) to Battery Backup Mode

The device Time Stamps the switchover from V

to

DD

V

and V to V , and the time is stored in t

(V

)

BAT

and t

BAT DD SV2B

BAT

To transition from the V

registers respectively. If multiple V

DD

SB2V

to V

BAT

mode, both of the

DD

power-down sequences occur before the status is read,

the earliest V to V power-down time is stored and

following conditions must be met:

DD BAT

Condition 1:

the most recent V

to V

time is stored.

BAT DD

V

< V - V

BAT BATHYS

DD

where V

Temperature conversion and compensation can be

enabled in battery backup mode. Bit BTSE in the BETA

register controls this operation, as described in “BETA

Register (BETA)” on page 19.

≈ 50mV

BATHYS

Condition 2:

V

< V

DD

TRIP

Power Failure Detection

where V

≈ 2.2V

The ISL12022M provides a Real Time Clock Failure Bit

(RTCF) to detect total power failure. It allows users to

determine if the device has powered up after having lost

Battery Backup Mode (V

) to Normal

BAT

Mode (V

)

DD

The ISL12022M device will switch from the V

to V

DD

BAT

all power to the device (both V

and V ).

DD

BAT

mode when one of the following conditions occurs:

Brownout Detection

Condition 1:

The ISL12022M monitors the V

provides warning if the V

DD

levels. There are six (6) levels that can be selected for

level continuously and

level drops below prescribed

DD

V

> V

+ V

BATHYS

DD

where V

BAT

≈ 50mV

BATHYS

the trip level. These values are 85% below popular V

DD

Condition 2:

levels. The LVDD bit in the Status Register will be set to

V

> V

+ V

2

DD

where V

TRIP

TRIPHYS

≈ 30mV

“1” when brownout is detected. Note that the I C serial

TRIPHYS

bus remains active unless the Battery V

reached.

levels are

TRIP

These power control situations are illustrated in

Figures 12 and 13.

Battery Level Monitor

The ISL12022M has a built-in warning feature once the

backup battery level drops first to 85% and then to 75%

2

The I C bus is deactivated in battery backup mode to

reduce power consumption. Aside from this, all RTC

functions are operational during battery backup mode.

Except for SCL and SDA, all the inputs and outputs of

the ISL12022M are active during battery backup mode

unless disabled via the control register.

of the battery’s nominal V

level. When the battery

BAT

voltage drops to between 85% and 75%, the LBAT85 bit

is set in the status register. When the level drops below

75%, both LBAT85 and LBAT75 bits are set in the status

register.

BATTERY BACKUP

MODE

The battery level monitor is not functional in battery

backup mode. In order to read the monitor bits after

V

DD

powering up V , instigate a battery level measurement

by setting the TSE bit to "1" (BETA register), and then

read the bits.

DD

V

TRIP

2.2V

1.8V

V

BAT

There is a Battery Time Stamp Function available. Once

V

+ V

BATHYS

BAT

V

- V

BATHYS

BAT

the V

is low enough to enable switchover to the

DD

battery, the RTC time/date are written into the TSV2B

register. This information can be read from the TSV2B

registers to discover the point in time of the V

DD

power-down. If there are multiple power-down cycles

before reading these registers, the first values stored in

FIGURE 12. BATTERY SWITCHOVER WHEN

< V

V

BAT

TRIP

FN6668.7

June 4, 2010

11

ISL12022M

these registers will be retained. These registers will hold

the original power-down value until they are cleared by

setting CLRTS = 1 to clear the registers.

Frequency Output Mode

The ISL12022M has the option to provide a clock output

signal using the IRQ/F

open drain output pin. The

OUT

frequency output mode is set by using the FO bits to

select 15 possible output frequency values from 1/32Hz

to 32kHz. The frequency output can be enabled/disabled

during Battery Backup mode using the FOBATB bit.

The normal power switching of the ISL12022M is

designed to switch into battery backup mode only if the

V

power is lost. This will ensure that the device can

DD

accept a wide range of backup voltages from many types

of sources while reliably switching into backup mode.

General Purpose User SRAM

Note that the ISL12022M is not guaranteed to operate

The ISL12022M provides 128 bytes of user SRAM. The

SRAM will continue to operate in battery backup mode.

However, it should be noted that the I C bus is disabled

with V

< 1.8V. If the battery voltage is expected to

drop lower than this minimum, correct operation of the

BAT

2

device, (especially after a V

guaranteed.

power-down cycle) is not

in battery backup mode.

DD

2

I C Serial Interface

The minimum V

BAT

to insure SRAM is stable is 1.0V.

2

The ISL12022M has an I C serial bus interface that

Below that, the SRAM may be corrupted when V

power resumes.

DD

provides access to the control and status registers and

2

the user SRAM. The I C serial interface is compatible

with other industry I C serial bus protocols using a

Real Time Clock Operation

bi-directional data signal (SDA) and a clock signal (SCL).

The Real Time Clock (RTC) uses an integrated 32.768kHz

quartz crystal to maintain an accurate internal

Oscillator Compensation

representation of second, minute, hour, day of week,

date, month, and year. The RTC also has leap-year

correction. The clock also corrects for months having

fewer than 31 days and has a bit that controls 24-hour or

AM/PM format. When the ISL12022M powers up after the

The ISL12022M provides both initial timing correction

and temperature correction due to variation of the

crystal oscillator. Analog and digital trimming control is

provided for initial adjustment, and a temperature

compensation function is provided to automatically

correct for temperature drift of the crystal. Initial values

for the initial AT and DT settings (ITR0), temperature

coefficient (ALPHA), crystal capacitance (BETA), as well

as the crystal turn-over temperature (XTO), are preset

internally and recalled to RAM registers on power-up.

These values can be overwritten by the user

although this is not suggested as the resulting

temperature compensation performance will be

compromised. The compensation function can be

enabled/disabled at any time and can be used in battery

mode as well.

loss of both V

and V , the clock will not begin

DD

BAT

incrementing until at least one byte is written to the clock

register.

Single Event and Interrupt

The alarm mode is enabled via the MSB bit. Choosing

single event or interrupt alarm mode is selected via the

IM bit. Note that when the frequency output function is

enabled, the alarm function is disabled.

The standard alarm allows for alarms of time, date,

day of the week, month, and year. When a time alarm

occurs in single event mode, the IRQ/F

pulled low and the alarm status bit (ALM) will be set

to “1”.

pin will be

OUT

Register Descriptions

The battery-backed registers are accessible following a

slave byte of “1101111x” and reads or writes to

addresses [00h:2Fh]. The defined addresses and default

values are described in the Table 1. The battery backed

general purpose SRAM has a different slave address

(1010111x), so it is not possible to read/write that

section of memory while accessing the registers.

The pulsed interrupt mode allows for repetitive or

recurring alarm functionality. Hence, once the alarm is

set, the device will continue to alarm for each occurring

match of the alarm and present time. Thus, it will alarm

as often as every minute (if only the nth second is set) or

as infrequently as once a year (if at least the nth month

is set). During pulsed interrupt mode, the IRQ/F

REGISTER ACCESS

OUT

will be pulled low for 250ms and the alarm status bit

(ALM) will be set to “1”.

The contents of the registers can be modified by

performing a byte or a page write operation directly to

any register address.

The ALM bit can be reset by the user or cleared

automatically using the auto reset mode (see ARST bit).

The alarm function can be enabled/disabled during

battery backup mode using the FOBATB bit. For more

information on the alarm, please see “ALARM Registers

(10h to 15h)” on page 20.

The registers are divided into 8 sections. They are:

1. Real Time Clock (7 bytes): Address 00h to 06h.

2. Control and Status (9 bytes): Address 07h to 0Fh.

3. Alarm (6 bytes): Address 10h to 15h.

4. Time Stamp for Battery Status (5 bytes): Address

16h to 1Ah.

FN6668.7

June 4, 2010

12

ISL12022M

5. Time Stamp for V

to 1Fh.

Status (5 bytes): Address 1Bh

A register can be read by performing a random read at

DD

any address at any time. This returns the contents of

that register location. Additional registers are read by

performing a sequential read. For the RTC and Alarm

registers, the read instruction latches all clock registers

into a buffer, so an update of the clock does not change

the time being read. At the end of a read, the master

supplies a stop condition to end the operation and free

the bus. After a read, the address remains at the

previous address +1 so the user can execute a current

address read and continue reading the next register.

When the previous address is 2Fh, the next address will

wrap around to 00h.

6. Day Light Saving Time (8 bytes): 20h to 27h.

7. TEMP (2 bytes): 28h to 29h.

8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah,

2Bh

9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch

10.Crystal ALPHA at high temperature, ALPHA_H (1

byte): 2Dh

11.Scratch Pad (2 bytes): Address 2Eh and 2Fh

Write capability is allowable into the RTC registers (00h

to 06h) only when the WRTC bit (bit 6 of address 08h) is

set to “1”. A multi-byte read or write operation should be

limited to one section per operation for best RTC time

keeping performance.

It is not necessary to set the WRTC bit prior to writing

into the control and status, alarm, and user SRAM

registers.

TABLE 1. REGISTER MEMORY MAP (YELLOW SHADING INDICATES READ-ONLY BITS)

BIT

REG

ADDR. SECTION NAME

7

0

6

5

SC21

MN21

HR21

DT21

0

4

SC20

MN20

HR20

DT20

MO20

YR20

0

3

2

1

0

RANGE DEFAULT

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

SC

MN

SC22

SC13

SC12

MN12

HR12

DT12

MO12

YR12

DW2

SC11

MN11

HR11

DT11

MO11

YR11

DW1

SC10

MN10

HR10

DT10

MO10

YR10

DW0

RTCF

FO0

0 to 59

0 to 23

1 to 31

1 to 12

0 to 99

0 to 6

N/A

00h

01h

00h

01h

00h

XXh

00h

0

MN22

MN13

HR13

DT13

HR

MIL

0

RTC

DT

0

MO

0

MO13

YR13

YR

YR23

0

YR22

YR21

0

DW

0

SR

BUSY

ARST

CLRTS

D

OSCF

DSTADJ

IM

ALM

LVDD

FO3

LBAT85

FO2

LBAT75

FO1

INT

WRTC

FOBATB

D

N/A

PWR_VDD

PWR_VBAT

ITRO

ALPHA

BETA

FATR

FDTR

SCA0

MNA0

HRA0

DTA0

MOA0

DWA0

D

V

Trip2

DD

V

Trip1

DD

V

Trip0

N/A

DD

RESEALB

VB85Tp2

IATR05

ALPHA5

BTSR

FFATR5

0

VB85Tp1

IATR04

ALPHA4

BETA4

FATR4

VB85Tp0

IATR03

ALPHA3

BETA3

FATR3

FDTR3

SCA013

MNA013

HRA013

DTA013

MOA013

D

VB75Tp2

IATR02

ALPHA2

BETA2

VB75Tp1

IATR01

ALPHA1

BETA1

VB75Tp0

IATR00

ALPHA0

BETA0

N/A

CSR

IDTR01

D

IDTR00

N/A

ALPHA6

N/A

TSE

0

BTSE

N/A

0

FATR2

FATR1

FATR0

N/A

0

FDTR4

SCA020

MNA020

HRA020

DTA020

MOA020

D

FDTR2

FDTR1

FDTR0

N/A

ESCA0

EMNA0

EHRA0

EDTA0

EMOA00

EDWA0

SCA022

SCA021

MNA021

HRA021

DTA021

D

SCA012

MNA012

HRA012

DTA012

MOA012

DWA02

SCA011

MNA011

HRA011

DTA011

MOA011

DWA01

SCA010

MNA010

HRA010

DTA010

MOA010

DWA00

00 to 59

0 to 23

01 to 31

01 to 12

0 to 6

MNA022

D

ALARM

D

FN6668.7

June 4, 2010

13

ISL12022M

TABLE 1. REGISTER MEMORY MAP (YELLOW SHADING INDICATES READ-ONLY BITS) (Continued)

BIT

REG

ADDR. SECTION NAME

7

6

5

4

3

2

1

0

RANGE DEFAULT

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

VSC

VMN

0

VSC22

VSC21

VMN21

VHR21

VDT21

0

VSC20

VMN20

VHR20

VDT20

VMO20

BSC20

BMN20

BHR20

BDT20

BMO20

VSC13

VMN13

VHR13

VDT13

VMO13

BSC13

BMN13

BHR13

BDT13

BMO13

VSC12

VMN12

VHR12

VDT12

VMO12

BSC12

BMN12

BHR12

BDT12

BMO12

VSC11

VMN11

VHR11

VDT11

VMO11

BSC11

BMN11

BHR11

BDT11

BMO11

VSC10

VMN10

VHR10

VDT10

VMO10

BSC10

BMN10

BHR10

BDT10

BMO10

0 to 59

0 to 23

1 to 31

1 to 12

0 to 59

0 to 23

1 to 31

1 to 12

00h

XXh

00h

0

VMN22

TSV2B

TSB2V

VHR

VMIL

0

VDT

0

VMO

0

BSC

0

BSC22

BSC21

BMN21

BHR21

BDT21

0

BMN

0

BMN22

BHR

BMIL

0

BDT

0

BMO

0

DstMoFd

DstDwFd

DstDtFd

DstHrFd

DstMoRv

DstDwRv

DstDtRv

DstHrRv

TK0L

DSTE

D

DstMoFd20 DstMoFd13 DstMoFd12 DstMoFd11 DstMoFd10 1 to 12

D

DstDwFdE DstWkFd12 DstWkFd11 DstWkFd10 DstDwFd12 DstDwFd11 DstDwFd10

0 to 6

1 to 31

0 to 23

D

DstDtFd21 DstDtFd20 DstDtFd13 DstDtFd12 DstDtFd11 DstDtFd10

DstHrFd21 DstHrFd20 DstHrFd13 DstHrFd12 DstHrFd11 DstHrFd10

D

DSTCR

D

DstMoRv20 DstMoRv13 DstMoR12v DstMoRv11 DstMoRv10 01 to 12

0 to 6

D

DstDwRvE DstWkrv12 DstWkRv11 DstWkRv10 DstDwRv12 DstDwRv11 DstDwRv10

D

DstDtRv21 DstDtRv20 DstDtRv13 DstDtRv12 DstDtRv11 DstDtRv10 01 to 31

DstHrRv21 DstHrRv20 DstHrRv13 DstHrRv12 DstHrRv11 DstHrRv10 0 to 23

D

TK07

0

TK06

0

TK05

0

TK04

0

TK03

0

TK02

0

TK01

TK09

TK00

TK08

00 to FF

00 to 03

00 to FF

00 to 07

00 to FF

00 to 7F

00 to FF

TEMP

NPPM

TK0M

NPPML

NPPMH

XT0

NPPM7

0

NPPM6

0

NPPM5

0

NPPM4

0

NPPM3

0

NPPM2

NPPM10

XT2

NPPM1

NPPM9

XT1

NPPM0

NPPM8

XT0

ALPHAH

GPM

D

XT4

XT3

ALPHAH

GPM1

GPM2

D

ALP_H6

GPM16

GPM26

ALP_H5

GPM15

GPM25

ALP_H4

GPM14

GPM24

ALP_H3

GPM13

GPM23

ALP_H2

GPM12

GPM22

ALP_H1

GPM11

GPM21

ALP_H0

GPM10

GPM20

GPM17

GPM27

be decided by the system software designer. The default

value is defined as “0”.

Real Time Clock Registers

Addresses [00h to 06h]

24-HOUR TIME

If the MIL bit of the HR register is “1”, the RTC uses a

24-hour format. If the MIL bit is “0”, the RTC uses a

12-hour format and HR21 bit functions as an AM/PM

indicator with a “1” representing PM. The clock defaults

to 12-hour format time with HR21 = “0”.

RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)

These registers depict BCD representations of the time.

As such, SC (Seconds) and MN (Minutes) range from 0 to

59, HR (Hour) can either be a 12-hour or 24-hour mode,

DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is

0 to 99, and DW (Day of the Week) is 0 to 6.

LEAP YEARS

Leap years add the day February 29 and are defined as

those years that are divisible by 4. Years divisible by 100

are not leap years, unless they are also divisible by 400.

This means that the year 2000 is a leap year and the

year 2100 is not. The ISL12022M does not correct for the

leap year in the year 2100.

The DW register provides a Day of the Week status and

uses three bits (DW2 to DW0) to represent the seven

days of the week. The counter advances in the cycle

0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical

value to a specific day of the week is arbitrary and may

FN6668.7

June 4, 2010

14

ISL12022M

LOW V

INDICATOR BIT (LVDD)

DD

Control and Status Registers

(CSR)

This bit indicates when V

has dropped below the

DD

pre-selected trip level (Brownout Mode). The trip points

for the brownout levels are selected by three bits: VDD

Trip2, VDD Trip1 and VDD Trip0 in PWR_ VDD registers.

The LVDD detection is only enabled in VDD mode and

the detection happens in real time. The LVDD bit is set

whenever the V

trip level, and self clears whenever the V

pre-selected trip level.

Addresses [07h to 0Fh]

The Control and Status Registers consist of the Status

Register, Interrupt and Alarm Register, Analog Trimming

and Digital Trimming Registers.

has dropped below the pre-selected

DD

is above the

STATUS REGISTER (SR)

DD

The Status Register is located in the memory map at

address 07h. This is a volatile register that provides

either control or status of RTC failure (RTCF), Battery

Level Monitor (LBAT85, LBAT75), alarm trigger, Daylight

Saving Time, crystal oscillator enable and temperature

conversion in progress bit.

LOW BATTERY INDICATOR 85% BIT (LBAT85)

In Normal Mode (V ), this bit indicates when the

DD

battery level has dropped below the pre-selected trip

levels. The trip points are selected by three bits:

VB85Tp2, VB85Tp1 and VB85Tp0 in the PWR_VBAT

registers. The LBAT85 detection happens automatically

once every minute when seconds register reaches 59.

The detection can also be manually triggered by setting

the TSE bit in BETA register to “1”. The LBAT85 bit is set

TABLE 2. STATUS REGISTER (SR)

ADDR

7

6

5

4

3

2

1

0

07h

BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF

when the V

has dropped below the pre-selected trip

is above the

BAT

level, and will self clear when the V

BAT

pre-selected trip level at the next detection cycle either

BUSY BIT (BUSY)

by manual or automatic trigger.

Busy Bit indicates temperature sensing is in progress. In

this mode, Alpha, Beta and ITRO registers are disabled

and cannot be accessed.

In Battery Mode (V

), this bit indicates the device has

BAT

entered into battery mode by polling once every 10

minutes. The LBAT85 detection happens automatically

once when the minute register reaches x9h or x0h

minutes.

OSCILLATOR FAIL BIT (OSCF)

Oscillator Fail Bit indicates that the oscillator has

stopped.

Example - When the LBAT85 is Set To “1” In

Battery Mode:

DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)

The minute the register changes to 19h when the device

is in battery mode, the LBAT85 is set to “1” the next time

the device switches back to Normal Mode.

Example - When the LBAT85 Remains at “0” In

Battery Mode:

DSTADJ is the Daylight Saving Time Adjusted Bit. It

indicates the daylight saving time forward adjustment

has happened. If a DST Forward event happens,

DSTADJ will be set to “1”. The DSTADJ bit will stay high

when DSTFD event happens, and will be reset to “0”

when the DST Reverse event happens.

If the device enters into battery mode after the minute

register reaches 20h and switches back to Normal Mode

before the minute register reaches 29h, then the LBAT85

bit will remain at “0” the next time the device switches

back to Normal Mode.

DSTADJ can be set to “1” for instances where the RTC

device is initialized during the DST Forward period. The

DSTE bit must be enabled when the RTC time is more

than one hour before the DST Forward or DST Reverse

event time setting, or the DST event correction will not

happen.

LOW BATTERY INDICATOR 75% BIT (LBAT75)

In Normal Mode (V ), this bit indicates when the

DD

battery level has dropped below the pre-selected trip

levels. The trip points are selected by three bits:

DSTADJ is reset to “0” upon power-up. It will reset to “0”

when the DSTE bit in Register 15h is set to “0” (DST

disabled), but no time adjustment will happen.

VB75Tp2, VB75Tp1 and VB75Tp0 in the PWR_VBAT

registers. The LBAT75 detection happens automatically

once every minute when seconds register reaches 59.

The detection can also be manually triggered by setting

the TSE bit in BETA register to “1”. The LBAT75 bit is set

ALARM BIT (ALM)

This bit announces if the alarm matches the real time

clock. If there is a match, the respective bit is set to “1”.

This bit can be manually reset to “0” by the user or

automatically reset by enabling the auto-reset bit (see

ARST bit). A write to this bit in the SR can only set it to

“0”, not “1”. An alarm bit that is set by an alarm

occurring during an SR read operation will remain set

after the read operation is complete.

when the V

level, and will self clear when the V

BAT

has dropped below the pre-selected trip

BAT

is above the

pre-selected trip level at the next detection cycle either

by manual or automatic trigger.

In Battery Mode (V

), this bit indicates the device has

BAT

entered into battery mode by polling once every

10 minutes. The LBAT85 detection happens

automatically once when the minute register reaches x9h

or x0h minutes.

FN6668.7

June 4, 2010

15

ISL12022M

Example - When the LBAT75 is Set to “1” in Battery

TABLE 4.

Mode:

IM BIT

INTERRUPT/ALARM FREQUENCY

Single Time Event Set By Alarm

The minute register changes to 30h when the device is in

battery mode, the LBAT75 is set to “1” the next time the

device switches back to Normal Mode.

0

1

Repetitive/Recurring Time Event Set By

Alarm

Example - When the LBAT75 Remains at “0” in

Battery Mode:

FREQUENCY OUTPUT AND INTERRUPT BIT

(FOBATB)

If the device enters into battery mode after the minute

register reaches 49h and switches back to Normal Mode

before minute register reaches 50h, then the LBAT75 bit

will remain at “0” the next time the device switches

back to Normal Mode.

This bit enables/disables the IRQ/F

battery backup mode (i.e. V

When the FOBATB is set to “1”, the IRQ/F

disabled during battery backup mode. This means that

both the frequency output and alarm output functions

are disabled. When the FOBATB is cleared to “0”, the

pin during

power source active).

OUT

BAT

pin is

OUT

REAL TIME CLOCK FAIL BIT (RTCF)

This bit is set to a “1” after a total power failure. This is a

read only bit that is set by hardware (ISL12022M

internally) when the device powers up after having lost

all power (defined as V

is set regardless of whether V

The loss of only one of the supplies does not set the RTCF

bit to “1”. The first valid write to the RTC section after a

complete power failure resets the RTCF bit to “0” (writing

one byte is sufficient).

IRQ/F

pin is enabled during battery backup mode.

pin will need a

OUT

Note that the open drain IRQ/F

OUT

pull-up to the battery voltage to operate in battery

backup mode.

= 0V and V

= 0V). The bit

is applied first.

DD

BAT

or V

DD

FREQUENCY OUT CONTROL BITS (FO <3:0>)

These bits enable/disable the frequency output function

and select the output frequency at the IRQ/F

See Table 5 for frequency selection. Default for the

ISL12022M is

FO<3:0> = 1h, or 32.768kHz output (F

pin.

OUT

Interrupt Control Register (INT)

is ON).

OUT

TABLE 3. INTERRUPT CONTROL REGISTER (INT)

When the frequency mode is enabled, it will override

the alarm mode at the IRQ/F pin.

OUT

ADDR

7

6

5

4

3

2

1

0

TABLE 5. FREQUENCY SELECTION OF IRQ/F

08h

ARST WRTC

IM

FOBATB FO3 FO2 FO1 FO0

OUT

FREQUENCY,

AUTOMATIC RESET BIT (ARST)

F

UNITS

Hz

FO3

0

FO2

0

FO1

0

FO0

0

OUT

This bit enables/disables the automatic reset of the ALM,

LVDD, LBAT85, and LBAT75 status bits only. When ARST

bit is set to “1”, these status bits are reset to “0” after a

valid read of the respective status register (with a valid

STOP condition). When the ARST is cleared to “0”, the

user must manually reset the ALM, LVDD, LBAT85, and

LBAT75 bits.

0

32768

4096

1024

64

Hz

0

1

Hz

0

1

0

Hz

0

1

Hz

0

1

0

32

Hz

0

1

0

1

WRITE RTC ENABLE BIT (WRTC)

The WRTC bit enables or disables write capability into the

RTC Timing Registers. The factory default setting of this

bit is “0”. Upon initialization or power-up, the WRTC must

be set to “1” to enable the RTC. Upon the completion of a

valid write (STOP), the RTC starts counting. The RTC

internal 1Hz signal is synchronized to the STOP condition

during a valid write cycle.

16

Hz

0

1

0

8

Hz

0

1

4

Hz

1

0

2

Hz

1

0

1

Hz

1

0

1

0

1/2

1/4

1/8

1/16

1/32

Hz

1

0

1

INTERRUPT/ALARM MODE BIT (IM)

Hz

1

0

This bit enables/disables the interrupt mode of the alarm

function. When the IM bit is set to “1”, the alarm will

operate in the interrupt mode, where an active low pulse

Hz

1

0

1

Hz

1

0

width of 250ms will appear at the IRQ/F

pin when

OUT

the RTC is triggered by the alarm, as defined by the

alarm registers (0Ch to 11h). When the IM bit is cleared

to “0”, the alarm will operate in standard mode, where

Hz

1

the IRQ/F

pin will be set low until the ALM status bit

is cleared to “0”.

OUT

FN6668.7

June 4, 2010

16

ISL12022M

BATTERY LEVEL MONITOR TRIP BITS (VB85TP

<2:0>)

Power Supply Control Register (PWR_VDD)

CLEAR TIME STAMP BIT (CLRTS)

Three bits select the first alarm (85% of Nominal V

)

BAT

level for the battery voltage monitor. There are total of

7 levels that could be selected for the first alarm. Any of

the of levels could be selected as the first alarm with no

reference as to nominal Battery voltage level. See

Table 8.

ADDR

7

6

5

4

3

2

1

0

09h

CLRTS

0

V

Trip2

V

Trip1 V Trip0

DD DD

DD

This bit clears Time Stamp V

Time Stamp Battery to V

DD

default setting is 0 (CLRTS = 0) and the Enabled setting

to Battery (TSV2B) and

Registers (TSB2V). The

DD

TABLE 8. VB85T ALARM LEVEL

is 1 (CLRTS = 1).

BATTERY ALARM

TRIP LEVEL

V

BROWNOUT TRIP VOLTAGE BITS

DD

VB85Tp2 VB85Tp1 VB85Tp0

(V)

(V TRIP<2:0>)

DD

0

1

0

1

0

1

0

1

0

1

0

1

0

2.125

2.295

2.550

2.805

3.060

4.250

4.675

These bits set the trip level for the V

alarm, indicating

DD

that V

has dropped below a preset level. In this event,

DD

the LVDD bit in the Status Register is set to “1”. See

Table 6.

TABLE 6. V

TRIP LEVELS

DD

TRIP

VOLTAGE

(V)

V

Trip2

V

Trip1

V Trip0

DD

BATTERY LEVEL MONITOR TRIP BITS (VB75TP

<2:0>)

0

1

0

1

0

1

0

1

0

1

2.295

2.550

2.805

3.060

4.250

4.675

Three bits select the second alarm (75% of Nominal

V

) level for the battery voltage monitor. There are

BAT

total of 7 levels that could be selected for the second

alarm. Any of the of levels could be selected as the

second alarm with no reference as to nominal Battery

voltage level. See Table 9.

TABLE 9. BATTERY LEVEL MONITOR TRIP BITS

(VB75TP <2:0>)

Battery Voltage Trip Voltage Register

(PWR_VBAT)

This register controls the trip points for the two V

alarms, with levels set to approximately 85% and 75% of

the nominal battery level.

BATTERY ALARM

TRIP LEVEL

BAT

VB75Tp2

VB75Tp1 VB75Tp0

(V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1.875

2.025

2.250

2.475

2.700

3.750

4.125

TABLE 7.

ADDR

7

6

5

4

3

2

1

0

0Ah

D RESEALB VB85 VB85 VB85 VB75 VB75 VB75

Tp2 Tp1 Tp0 Tp2 Tp1 Tp0

RESEAL BIT (RESEALB)

This is the Reseal bit for actively disconnecting the V

pin from the internal circuitry. Setting this bit allows the

device to disconnect the battery and eliminate standby

BAT

Initial AT and DT Setting Register (ITRO)

These bits are used to trim the initial error (at room

temperature) of the crystal. Both Digital Trimming (DT)

and Analog Trimming (AT) methods are available. The

digital trimming uses clock pulse skipping and insertion

for frequency adjustment. Analog trimming uses load

capacitance adjustment to pull the oscillator frequency. A

range of +62.5ppm to -61.5ppm is possible with

combined digital and analog trimming.

current drain while the device is unused. Once V

is

DD

pin is then

powered up, this bit is reset and the V

connected to the internal circuitry.

BAT

The application for this bit involves placing the chip on a

board with a battery and testing the board. Once the

board is tested and ready to ship, it is desirable to

disconnect the battery to keep it fresh until the board or

unit is placed into final use. Setting RESEALB = “1”

Initial values for the ITR0 register are preset internally

and recalled to RAM registers on power-up. These

values are pre-set in device production and are

READ-ONLY. They cannot be overwritten by the

initiates the battery disconnect, and after V

power is

DD

cycled down and up again, the RESEAL bit is cleared

to “0”.

FN6668.7

June 4, 2010

17

ISL12022M

TABLE 12. IATRO TRIMMING RANGE (Continued)

user. If an application requires adjustment of the

IATR bits outside the preset values, the user

should contact Intersil.

TRIMMING

RANGE

IATR05 IATR04 IATR03 IATR02 IATR01 IATR00

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

+19

+18

+17

+16

+15

+14

+13

+12

+11

+10

+9

AGING AND INITIAL TRIM DIGITAL TRIMMING

BITS (IDTR0<1:0>)

These bits allow ±30.5ppm initial trimming range for the

crystal frequency. This is meant to be a coarse

adjustment if the range needed is outside that of the

IATR control. See Table 10. The IDTR0 register should

only be changed while the TSE (Temp Sense Enable) bit

is “0”.

The ISL12022M has a preset Initial Digital Trimming

value corresponding to the crystal in the module. This

value is recalled on initial power-up and is

+8

READ-ONLY. It cannot be overwritten by the user.

+7

TABLE 10. IDTR0 TRIMMING RANGE

+6

IDTR01

IDTR00

TRIMMING RANGE

Default/Disabled

+5

+4

0

1

0

1

0

1

+3

+30.5ppm

0ppm

+2

+1

-30.5ppm

0

-1

AGING AND INITIAL ANALOG TRIMMING BITS

(IATR0<5:0>)

-2

-3

The Initial Analog Trimming Register allows +32ppm to

-31ppm adjustment in 1ppm/bit increments. This

enables fine frequency adjustment for trimming initial

crystal accuracy error or to correct for aging drift.

-4

-5

-6

-7

The ISL12022M has a preset Initial Analog Trimming

value corresponding to the crystal in the module. This

value is recalled on initial power-up, is preset in

device production and is READ-ONLY. It cannot be

overwritten by the user.

-8

-9

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

TABLE 11. INITIAL AT AND DT SETTING REGISTER

ADDR

7

6

5

4

3

2

1

0

0Bh

IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00

TABLE 12. IATRO TRIMMING RANGE

TRIMMING

IATR05 IATR04 IATR03 IATR02 IATR01 IATR00

RANGE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+32

+31

+30

+29

+28

+27

+26

+25

+24

+23

+22

+21

+20

FN6668.7

June 4, 2010

18

ISL12022M

battery mode. The BTSE is disabled when the battery

voltage is lower than 2.7V. No temperature

compensation will take place with VBAT<2.7V.

ALPHA Register (ALPHA)

TABLE 13. ALPHA REGISTER

ADD

R

FREQUENCY OF TEMPERATURE SENSING AND

CORRECTION BIT (BTSR)

7

6

5

4

3

2

1

0

0Ch

D

ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2 ALPHA1 ALPHA0

This bit controls the frequency of Temp Sensing and

Correction. BTSR = 0 default mode is every 10 minutes,

BTSR = 1 is every 1.0 minute. Note that BTSE has to be

enabled in both cases. See Table 15.

The ALPHA variable is 8 bits and is defined as the

temperature coefficient of crystal from -40°C to T0, or

the ALPHA Cold (there is an Alpha Hot register that

must be programmed as well). It is normally given in

TABLE 15. FREQUENCY OF TEMPERATURE SENSING

AND CORRECTION BIT

2

units of ppm/°C , with a typical value of -0.034. The

ISL12022M device uses a scaled version of the absolute

value of this coefficient in order to get an integer value.

Therefore, ALPHA <7:0> is defined as the (|Actual

ALPHA Value| x 2048) and converted to binary. For

example, a crystal with Alpha of -0.034ppm/°C is first

scaled (|2048*(-0.034)| = 70d) and then converted to

a binary number of 01000110b.

TC PERIOD IN

BATTERY MODE

BTSE

BTSR

0

1

0

1

0

1

OFF

2

OFF

10 Minutes

1 Minute

The practical range of Actual ALPHA values is from

-0.020 to -0.060.

The temperature measurement conversion time is the

same for battery mode as for V mode, approximately

The ISL12022M has a preset ALPHA value

DD

corresponding to the crystal in the module. This value

is recalled on initial power-up and is preset in

device production. It is READ ONLY and cannot

be overwritten by the user.

22ms. The battery mode current will increase during

this conversion time to typically 68µA. The average

increase in battery current is much lower than this due

to the small duty cycle of the ON-time versus OFF-time

for the conversion.

BETA Register (BETA)

To figure the average increase in battery current, we take

the change in current times the duty cycle. For the

1 minute temperature period, the average current is

expressed in Equation 1:

TABLE 14.

ADDR

7

6

5

4

3

2

1

0

0Dh

TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0

0.022s

(EQ. 1)

-----------------

× 68μA= 250nA

ΔI

=

BAT

60s

The BETA register has special Write properties. Only the

TSE, BTSE and BTSR bits can be written; the BETA bits

are READ-ONLY. A write to both bytes in this register will

only change the 3 MSB’s (TSE, BTSE, BTSR), and the

5 LSB’s will remain the same as set at the factory.

For the 10 minute temperature period the average

current is expressed in Equation 2:

0.022s

600s

(EQ. 2)

-----------------

× 68μA= 25nA

ΔI

=

BAT

If the application has a stable temperature environment

that doesn’t change quickly, the 10 minute option will

work well and the backup battery lifetime impact is

minimized. If quick temperature variations are expected

(multiple cycles of more than 10° within an hour), then

the 1 minute option should be considered and the slightly

higher battery current figured into overall battery life.

TEMPERATURE SENSOR ENABLED BIT (TSE)

This bit enables the Temperature Sensing operation,

including the temperature sensor, A/D converter and

FATR/FDTR register adjustment. The default mode after

power-up is disabled: (TSE = 0). To enable the operation,

TSE should be set to 1. (TSE = 1). When temp sense is

disabled, the initial values for IATR and IDTR registers

are used for frequency control.

GAIN FACTOR OF AT BIT (BETA<4:0>)

Beta is specified to take care of the Cm variations of the

crystal. Most crystals specify Cm around 2.2fF. For

example, if Cm > 2.2fF, the actual AT steps may reduce

from 1ppm/step to approximately 0.80ppm/step. Beta

is then used to adjust for this variation and restore the

step size to 1ppm/step.

When TSE is set to 1, the temperature conversion cycle

begins and will end when two temperature conversions

are completed. The average of the two conversions is in

the TEMP registers.

TEMP SENSOR CONVERSION IN BATTERY MODE

BIT (BTSE)

BETA values are limited in the range from 01000 to

11111, as shown in Table 16. To use Table 16, the device

is tested at two AT settings as follows:

This bit enables the Temperature Sensing and Correction

in battery mode. BTSE = 0 (default) no conversion, Temp

Sensing or Compensation in battery mode. BTSE = 1

indicates Temp Sensing and Compensation enabled in

BETA VALUES = (AT(max) - AT (min))/63, where:

FN6668.7

June 4, 2010

19

ISL12022M

AT(max) = F

in ppm (at AT = 00H) and

in ppm (at AT = 3FH).

Final Digital Trimming Register (FDTR)

OUT

This Register shows the final setting of DT after

temperature correction. It is read-only; the user cannot

overwrite a value to this register. The value is accessible

as a means of monitoring the temperature compensation

function. The corresponding clock adjustment values are

shown in Table 19. The FDTR setting has both positive

and negative settings to adjust for any offset in the

crystal.

AT(min) = F

OUT

The BETA VALUES result is indexed in the right hand

column and the resulting Beta factor (for the register) is

in the same row in the left column.

The ISL12022M has a preset BETA value corresponding

to the crystal in the module. This value is recalled on

initial power-up and is preset in device production.

It is READ ONLY and cannot be overwritten by the

user.

.

TABLE 18. FINAL DIGITAL TRIMMING REGISTER

ADDR

7

6

5

4

3

2

1

0

TABLE 16. BETA VALUES

0Fh

0

FDTR4 FDTR3 FDTR2 FDTR1 FDTR0

BETA<4:0>

01000

00111

00110

00101

00100

00011

00010

00001

00000

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

AT STEP ADJUSTMENT

0.5000

0.5625

0.6250

0.6875

0.7500

0.8125

0.8750

0.9375

1.0000

1.0625

1.1250

1.1875

1.2500

1.3125

1.3750

1.4375

1.5000

1.5625

1.6250

1.6875

1.7500

1.8125

1.8750

1.9375

2.0000

TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL

DIGITAL TRIMMING REGISTER

ppm

FDTR<2:0>

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

DECIMAL

ADJUSTMENT

0

1

0

30.5

2

61

3

91.5

4

122

5

152.5

183

6

7

213.5

244

8

9

274.5

305

10

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-30.5

-61

-91.5

-122

-152.5

-183

-213.5

-244

-274.5

-305

Final Analog Trimming Register (FATR)

This register shows the final setting of AT after

ALARM Registers (10h to 15h)

The alarm register bytes are set up identical to the RTC

register bytes, except that the MSB of each byte

functions as an enable bit (enable = “1”). These enable

bits specify which alarm registers (seconds, minutes,

etc.) are used to make the comparison. Note that there

is no alarm byte for year.

temperature correction. It is read-only; the user cannot

overwrite a value to this register. This value is accessible

as a means of monitoring the temperature compensation

function. See Table 17 and Table 18 (for values).

TABLE 17. FINAL ANALOG TRIMMING REGISTER

ADDR

7

6

5

4

3

2

1

0

The alarm function works as a comparison between the

alarm registers and the RTC registers. As the RTC

advances, the alarm will be triggered once a match

occurs between the alarm registers and the RTC

0Eh

0

FATR5 FATR4 FATR3 FATR2 FATR1 FATR0

FN6668.7

June 4, 2010

20

ISL12022M

registers. Any one alarm register, multiple registers, or

Example 2

all registers can be enabled for a match.

• Pulsed interrupt once per minute (IM = “1”)

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

• Interrupts at one minute intervals when the seconds

register is at 30 seconds.

• Single Event Mode is enabled by setting the bit 7

on any of the Alarm registers (ESCA0... EDWA0) to

“1”, the IM bit to “0”, and disabling the frequency

output. This mode permits a one-time match

between the Alarm registers and the RTC registers.

Once this match occurs, the ALM bit is set to “1” and

• Set Alarm registers as follows:

BIT

ALARM

REGISTER 7 6 5 4 3 2 1 0 HEX

DESCRIPTION

SCA0

1 0 1 1 0 0 0 0 B0h Seconds set to 30,

enabled

the IRQ/F

output will be pulled low and will

OUT

remain low until the ALM bit is reset. This can be

done manually or by using the auto-reset feature.

MNA0

HRA0

DTA0

MOA0

DWA0

0 0 0 0 0 0 0 0 00h Minutes disabled

0 0 0 0 0 0 0 0 00h Hours disabled

0 0 0 0 0 0 0 0 00h Date disabled

0 0 0 0 0 0 0 0 00h Month disabled

0 0 0 0 0 0 0 0 00h Day of week disabled

• Interrupt Mode is enabled by setting the bit 7 on

any of the Alarm registers (ESCA0... EDWA0) to “1”,

the IM bit to “1”, and disabling the frequency output.

The IRQ/F

output will now be pulsed each time

OUT

an alarm occurs. This means that once the interrupt

mode alarm is set, it will continue to alarm for each

occurring match of the alarm and present time. This

mode is convenient for hourly or daily hardware

interrupts in microcontroller applications such as

security cameras or utility meter reading.

Once the registers are set, the following waveform will be

seen at IRQ/F

:

OUT

RTC AND ALARM REGISTERS ARE BOTH “30s”

To clear a single event alarm, the ALM bit in the status

register must be set to “0” with a write. Note that if the

ARST bit is set to 1 (address 08h, bit 7), the ALM bit will

automatically be cleared when the status register is read.

60s

Following are examples of both Single Event and periodic

Interrupt Mode alarms.

FIGURE 14. IRQ/F

OUT

WAVEFORM

Note that the status register ALM bit will be set each time

the alarm is triggered, but does not need to be read or

cleared.

Example 1

• Alarm set with single interrupt (IM = “0”)

• A single alarm will occur on January 1 at 11:30 a.m.

• Set Alarm registers as follows:

Time Stamp V

(TSV2B)

to Battery Registers

DD

The TSV2B Register bytes are identical to the RTC

register bytes, except they do not extend beyond the

BIT

ALARM

Month. The Time Stamp captures the FIRST V

to

DD

REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION

Battery Voltage transition time, and will not update upon

subsequent events until cleared (only the first event is

captured before clearing). Set CLRTS = 1 to clear this

SCA0

MNA0

0

1

0 0 0 0 0 0

0 1 1 0 0 0

0

00h Seconds disabled

B0h Minutes set to

30, enabled

register (Add 09h, PWR_V

register).

DD

Note that the time stamp registers are cleared to all “0”,

including the month and day, which is different from the

RTC and alarm registers (those registers default to 01h).

This is the indicator that no time stamping has occurred

since the last clear or initial power-up. Once a time

stamp occurs, there will be a non-zero time stamp.

HRA0

DTA0

MOA0

DWA0

1

0

0 0 1 0 0 0

0 0 0 0 0 0

1

0

91h Hours set to 11,

enabled

81h Date set to 1,

enabled

81h Month set to 1,

enabled

Time Stamp Battery to V

(TSB2V)

Registers

DD

00h Day of week

disabled

The Time Stamp Battery to VDD Register bytes are

identical to the RTC register bytes, except they do not

extend beyond Month. The Time Stamp captures the

LAST transition of VBAT to VDD (only the last event of a

series of power-up/power-down events is retained). Set

After these registers are set, an alarm will be generated

when the RTC advances to exactly 11:30 a.m. on

January 1 (after seconds changes from 59 to 00) by

setting the ALM bit in the status register to “1” and also

CLRTS = 1 to clear this register (Add 09h, PWR_V

register).

DD

bringing the IRQ/F

output low.

OUT

FN6668.7

June 4, 2010

21

ISL12022M

must have the correct Day of Week entered in the RTC

registers for the Day/Week correction to work properly.

DST Control Registers (DSTCR)

8 bytes of control registers have been assigned for the

Daylight Savings Time (DST) functions. DST beginning

(set Forward) time is controlled by the registers

DstMoFd, DstDwFd, DstDtFd, and DstHrFd. DST ending

time (set Backward or Reverse) is controlled by DstMoRv,

DstDwRv, DstDtRv and DstHrRv.

• Bits 0, 1, 2 contain the Day of the week information

which sets the Day of the Week that DST starts. Note

that Day of the week counts from 0 to 6, like the RTC

registers. The default for the DST Forward Day of the

Week is 00h (normally Sunday).

Tables 20 and 21 describe the structure and functions of

the DSTCR.

• Bits 3, 4, 5 contain the Week of the Month information

that sets the week that DST starts. The range is from

1 to 5, and Week 7 is used to indicate the last week of

the month. The default for the DST Forward Week of

the Month is 00h.

DST FORWARD REGISTERS (20H TO 23H)

DST forward is controlled by the following DST Registers:

DST Enable

DST Date Forward

DSTE is the DST Enabling Bit located in bit 7 of register

20h (DstMoFdxx). Set DSTE = 1 will enable the DSTE

function. Upon powering up for the first time (including

battery), the DSTE bit defaults to “0”. When DSTE is set

to “1” the RTC time must be at least one hour before the

scheduled DST time change for the correction to take

place. When DSTE is set to “0”, the DSTADJ bit in the

Status Register automatically resets to “0”.

DstDtfd controls which Date DST begins. The format for

the Date is the same as for the RTC register, from 1 to

31. The default value for DST forward date is 00h.

DstDtFd is only effective if DstDwFdE = 0.

DST Hour Forward

DstHrFd controls the hour that DST begins. The RTC hour

and DstHrFd registers have the same formats except

there is no Military bit for DST hour. The user sets the

DST hour with the same format as used for the RTC hour

(AM/PM or MIL) but without the MIL bit, and the DST will

still advance as if the MIL bit were there. The default

value for DST hour Forward is 00h.

DST Month Forward

DstMoFd sets the Month that DST starts. The format is

the same as for the RTC register month, from 1 to 12.

The default value for the DST begin month is 00h.

DST REVERSE REGISTERS (24H TO 27H)

DST Day/Week Forward

DST end (reverse) is controlled by the following DST

Registers:

DstDwFd contains both the Day of the Week and the

Week of the Month data for DST Forward control. DST

can be controlled either by actual date or by setting both

the Week of the month and the Day of the Week.

DstDwFdE sets the priority of the Day/Week over the

Date. For DstDwFdE = 1, Day/Week is the priority. You

DST Month Reverse

DstMoRv sets the Month that DST ends. The format is

the same as for the RTC register month, from 1 to 12.

The default value for the DST end month is October

(10h).

TABLE 20. DST FORWARD REGISTERS

ADDRESS

FUNCTION

7

6

5

4

3

2

1

0

Month

DSTE

0

MoFd20

MoFd13

MoFd12

MoFd11

MoFd10

20h

21h

22h

Forward

Day Forward

0

DwFdE

0

WkFd12

DtFd21

WkFd11

DtFd20

WkFd10

DtFd13

DwFd12

DtFd12

DwFd11

DtFd11

DwFd10

DtFd10

Date

Forward

Hour

0

HrFd21

HrFd20

HrFd13

HrFd12

HrFd11

HrFd10

23h

Forward

TABLE 21. DST REVERSE REGISTERS

ADDRESS

NAME

7

6

5

4

3

2

1

0

Month

0

MoRv20

MoRv13

MoRv12

MoRv11

MoRv10

24h

25h

26h

27h

Reverse

Day Reverse

Date Reverse

Hour Reverse

0

DwRvE

WkRv12

DtRv21

HrRv21

WkRv11

DtRv20

HrRv20

WkRv10

DtRv13

HrRv13

DwRv12

DtRv12

HrRv12

DwRv11

DtRv11

HrRv11

DwRv10

DtRv10

HrRv10

0

FN6668.7

June 4, 2010

22

ISL12022M

DST Day/Week Reverse

NPPM Registers (NPPM)

DstDwRv contains both the Day of the Week and the

Week of the Month data for DST Reverse control. DST

can be controlled either by actual date or by setting both

the Week of the month and the Day of the Week.

DstDwRvE sets the priority of the Day/Week over the

Date. For DstDwRvE = 1, Day/Week is the priority. You

must have the correct Day of Week entered in the RTC

registers for the Day/Week correction to work properly.

The NPPM value is exactly 2x the net correction, in ppm,

required to bring the oscillator to 0ppm error. The value

is the combination of oscillator Initial Correction (IPPM)

and crystal temperature dependent correction (CPPM).

IPPM is used to compensate the oscillator offset at room

temperature and is controlled by the ITR0 and BETA

registers. This value is normally set during room

temperature testing.

• Bits 0,1,2 contain the Day of the week information

which sets the Day of the Week that DST ends. Note

that Day of the week counts from 0 to 6, like the RTC

registers. The default for the DST Reverse Day of the

Week is 00h (normally Sunday).

The CPPM compensates the oscillator frequency

fluctuation over-temperature. It is determined by the

temperature (T), crystal curvature parameter (ALPHA),

and crystal turnover temperature (XT0). T is the result of

the temp sensor/ADC conversion, whose decimal result is

2x the actual temperature in Kelvin. ALPHA is from either

the ALPHA (cold) or ALPHAH (hot) register depending on

T, and XT0 is from the XT0 register.

• Bits 3, 4, 5 contain the Week of the Month information

that sets the week that DST ends. The range is from

1 to 5, and Week 7 is used to indicate the last week of

the month. The default for the DST Reverse Week of

the Month is 00h.

NPPM is governed by Equations 4 and 5:

NPPM = IPPM(ITR0, BETA) + ALPHA x (T-T0)2

NPPM = IPPM + CPPM

DST Date Reverse

2

DstDtRv controls which Date DST ends. The format for

the Date is the same as for the RTC register, from

1 to 31. The default value for DST Date Reverse is 00h.

The DstDtRv is only effective if the DwRvE = 0.

ALPHA • (T – T0)

(EQ. 4)

---------------------------------------------------

NPPM = IPPM +

4096

where

ALPHA = α • 2048

DST Hour Reverse

T is the reading of the ADC, result is 2 x temperature in

degrees Kelvin.

DstHrRv controls the hour that DST ends. The RTC hour

and DstHrFd registers have the same formats except

there is no Military bit for DST hour. The user sets the

DST hour with the same format as used for the RTC hour

(AM/PM or MIL) but without the MIL bit, and the DST will

still advance as if the MIL bit were there. The default

value for DST hour Reverse is 00h.

T = (2 • 298) + XT0

(EQ. 5)

or T = 596 + XT0

Note that NPPM can also be predicted from the FATR and

FDTR register by the relationship (all values in decimal):

TEMP Registers (TEMP)

NPPM = 2*(BETA*FATR - (FDTR-16)

XT0 Registers (XT0)

The temperature sensor produces an analog voltage

output which is input to an A/D converter and produces a

10-bit temperature value in degrees Kelvin. TK07:00 are

the LSBs of the code, and TK09:08 are the MSBs of the

code. The temperature result is actually the average of

two successive temperature measurements to produce

greater resolution for the temperature control. The

output code can be converted to °C by first converting

from binary to decimal, dividing by 2, and then

subtracting 273d.

TURNOVER TEMPERATURE (XT<3:0>)

The apex of the Alpha curve occurs at a point called the

turnover temperature, or XT0. Crystals normally have a

turnover temperature between +20°C and +30°C, with

most occurring near +25°C.

TABLE 23. TURNOVER TEMPERATURE

ADDR

7

6

5

4

3

2

1

0

(EQ. 3)

Temperature in °C = [(TK <9:0>)/2] - 273

2Ch

0

XT4 XT3 XT2 XT1 XT0

The practical range for the temp sensor register output is

from 446d to 726d, or -50°C to +90°C. The temperature

compensation function is only guaranteed over -40°C to

+85°C. The TSE bit must be set to “1” to enable

temperature sensing.

The ISL12022M has a preset Turnover temperature

corresponding to the crystal in the module. This value is

recalled on initial power-up and is preset in device

production. It is READ ONLY and cannot be

overwritten by the user.

TABLE 22.

Table 24 shows the values available, with a range from

+17.5°C to +32.5°C in +0.5°C increments. The default

value is 00000b or +25°C.

TEMP

TK0L

7

6

5

4

3

2

1

0

TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00

TK0M

0

TK09 TK08

FN6668.7

June 4, 2010

23

ISL12022M

version, a scaled version of the absolute value of this

TABLE 24. XT0 VALUES

TURNOVER

coefficient is used in order to get an integer value.

Therefore, ALP_H <7:0> is defined as the (|Actual

Alpha Hot Value| x 2048) and converted to binary. For

XT<4:0>

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

TEMPERATURE

32.5

32.0

31.5

31

2

example, a crystal with Alpha Hot of -0.034ppm/°C is

first scaled (|2048*(-0.034)| = 70d) and then

converted to a binary number of 01000110b.

The practical range of Actual ALPHAH values is from

-0.020 to -0.060.

30.5

30

The ISL12022M has a preset ALPHAH value

corresponding to the crystal in the module. This value is

recalled on initial power-up and is preset in device

production. It is READ ONLY and cannot be

overwritten by the user.

29.5

29.0

28.5

28.0

27.5

27.0

26.5

26.0

25.5

25.0

24.5

24.0

23.5

23.0

22.5

22.0

21.5

21.0

20.5

20.0

19.5

19.0

18.5

18.0

17.5

User Registers (Accessed by

Using Slave Address

1010111x)

Addresses [00h to 7Fh]

These registers are 128 bytes of battery-backed user

2

SRAM. The separate I C slave address must be used to

read and write to these registers.

2

I C Serial Interface

The ISL12022M supports a bi-directional bus oriented

protocol. The protocol defines any device that sends data

onto the bus as a transmitter and the receiving device as

the receiver. The device controlling the transfer is the

master and the device being controlled is the slave. The

master always initiates data transfers and provides the

clock for both transmit and receive operations.

Therefore, the ISL12022M operates as a slave device in

all applications.

2

All communication over the I C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (see

Figure 15). On power-up of the ISL12022M, the SDA pin

is in the input mode.

2

All I C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA

while SCL is HIGH. The ISL12022M continuously

monitors the SDA and SCL lines for the START condition

and does not respond to any command until this

condition is met (see Figure 15). A START condition is

ignored during the power-up sequence.

ALPHA Hot Register (ALPHAH)

TABLE 25. ALPHAH REGISTER

ADDR

7

6

5

4

3

2

1

0

2Dh

D

ALP_H6 ALP_H5 ALP_H4 ALP_H3 ALP_H2 ALP_H1 ALP_H0

2

All I C interface operations must be terminated by a

The ALPHA Hot variable is 7 bits and is defined as the

temperature coefficient of Crystal from the XT0 value to

+85°C (both Alpha Hot and Alpha Cold must be

programmed to provide full temperature

compensation). It is normally given in units of ppm/°C ,

with a typical value of -0.034. Like the ALPHA Cold

STOP condition, which is a LOW to HIGH transition of

SDA while SCL is HIGH (see Figure 15). A STOP condition

at the end of a read operation or at the end of a write

operation to memory only places the device in its

standby mode.

2

FN6668.7

June 4, 2010

24

ISL12022M

SCL

SDA

DATA

START

STOP

STABLE CHANGE STABLE

FIGURE 15. VALID DATA CHANGES, START AND STOP CONDITIONS

SCL FROM

MASTER

1

8

9

SDA OUTPUT FROM

TRANSMITTER

HIGH IMPEDANCE

HIGH

SDA OUTPUT

FROM RECEIVER

START

ACK

FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

SIGNALS FROM

THE MASTER

S

T

A

R

T

S

T

O

P

IDENTIFICATION

BYTE

ADDRESS

BYTE

DATA

BYTE

SIGNAL AT SDA

1 1 0 1 1 1 1 0

0 0 0 0

SIGNALS FROM

THE ISL12022M

A

C

K

A

C

K

A

C

K

FIGURE 17. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)

An acknowledge (ACK) is a software convention used to

The last bit of the Slave Address Byte defines a read or

write operation to be performed. When this R/W bit is a

“1”, a read operation is selected. A “0” selects a write

operation (refer to Figure 18).

indicate a successful data transfer. The transmitting

device, either master or slave, releases the SDA bus

after transmitting eight bits. During the ninth clock cycle,

the receiver pulls the SDA line LOW to acknowledge the

reception of the eight bits of data (see Figure 16).

After loading the entire Slave Address Byte from the SDA

bus, the ISL12022M compares the device identifier and

device select bits with “1101111” or “1010111”. Upon a

correct compare, the device outputs an acknowledge on

the SDA line.

The ISL12022M responds with an ACK after recognition

of a START condition followed by a valid Identification

Byte, and once again, after successful receipt of an

Address Byte. The ISL12022M also responds with an ACK

after receiving a Data Byte of a write operation. The

master must respond with an ACK after receiving a Data

Byte of a read operation.

Following the Slave Byte is a one byte word address. The

word address is either supplied by the master device or

obtained from an internal counter. On power-up, the

internal address counter is set to address 00h, so a

current address read starts at address 00h. When

required, as part of a random read, the master must

supply the 1 Word Address Bytes, as shown in Figure 20.

Device Addressing

Following a start condition, the master must output a

Slave Address Byte. The 7 MSBs are the device

identifiers. These bits are “1101111” for the RTC

registers and “1010111” for the User SRAM.

In a random read operation, the slave byte in the

“dummy write” portion must match the slave byte in the

FN6668.7

June 4, 2010

25

ISL12022M

“read” section. For a random read of the Control/Status

Registers, the slave byte must be “1101111x” in both

places.

strongly advised to monitor the low battery indicators in

the status registers and take action to replace discharged

batteries.

SLAVE

ADDRESS BYTE

If a supercapacitor is used, it is possible that it may

discharge to below 1.8V during prolonged power-down.

Once powered up, the device may lose serial bus

1

0

1

R/

communications until both V

and V are powered

WORD

A7

D7

A6

D6

A5

D5

A4

D4

A3

D3

A2

D2

A1

D1

A0

D0

DD

BAT

ADDRESS

down together. To avoid that situation, including

situations where a battery may discharge deeply, the

circuit in Figure 19 can be used.

DATA BYTE

D

BAT

BAT43W

J

ISL12022M

VDD VBAT

FIGURE 18. SLAVE ADDRESS, WORD ADDRESS, AND

DATA BYTES

BAT

V

= 2.7V

DD

TO 5.5V

V

= 1.8V

BAT

+

TO 3.2V

C

IN

BAT

Write Operation

0.1µF

A Write operation requires a START condition, followed by

a valid Identification Byte, a valid Address Byte, a Data

Byte, and a STOP condition. After each of the three

bytes, the ISL12022M responds with an ACK. At this

GND

FIGURE 19. SUGGESTED BATTERY BACKUP CIRCUIT

2

time, the I C interface enters a standby state.

The diode, D

BAT

will add a small drop to the battery

Read Operation

voltage but will protect the circuit should battery voltage

drop below 1.8V. The jumper is added as a safeguard

should the battery ever need to be disconnected from the

circuit.

A Read operation consists of a three byte instruction,

followed by one or more Data Bytes (see Figure 20).

The master initiates the operation issuing the following

sequence: a START, the Identification byte with the R/W

bit set to “0”, an Address Byte, a second START, and a

second Identification byte with the R/W bit set to “1”.

After each of the three bytes, the ISL12022M responds

with an ACK. Then the ISL12022M transmits Data Bytes

as long as the master responds with an ACK during the

SCL cycle following the eighth bit of each byte. The

master terminates the read operation (issuing a STOP

condition) following the last bit of the last Data Byte

(see Figure 20).

The V

DD

negative slew rate should be limited to below

the data sheet spec (10V/ms) otherwise battery

switchover can be delayed, resulting in SRAM contents

corruption and oscillator operation interruption.

Some applications will require separate supplies for the

2

RTC V

and the I C pull-ups. This is not advised, as it

2

DD

may compromise the operation of the I C bus. For

applications that do require serial bus communication

with the RTC V

powered down, the SDA pin must be

DD

pulled low during the time the RTC V

DD

ramps down to

The Data Bytes are from the memory location indicated

by an internal pointer. This pointer’s initial value is

determined by the Address Byte in the Read operation

instruction, and increments by one during transmission

of each Data Byte. After reaching the memory location

2Fh, the pointer “rolls over” to 00h, and the device

continues to output data for each ACK received.

0V. Otherwise, the device may lose serial bus

communications once V is powered up, and will return

DD

to normal operation ONLY once V

powered down together.

and V are both

DD

BAT

Layout Considerations

The ISL12022M contains a quarts crystal and requires

special handling during PC board assembly. Excessive

shock and vibrations should be avoided, especially with

automated handling equipment. Ultrasound cleaning is

not advisable as it subjects the crystal to resonance and

possible failure. See also Note 6 on page 5 in the

specifications tables, which pertains to solder reflow

effects on oscillator accuracy.

Application Section

Battery Backup Details

The ISL12022M has automatic switchover to battery

backup when the V

drops below the V mode

DD

BAT

threshold. A wide variety of backup sources can be used,

including standard and rechargeable lithium,

supercapacitors, or regulated secondary sources. The

serial interface is disabled in battery backup, while the

oscillator and RTC registers are operational. The SRAM

register contents are powered to preserve their contents

as well.

The part of the package that has NC pins from pin 1 to 5

and from pin 16 to 20 contains the crystal. Low

frequency RTC crystals are known to pick up noise very

easily if layout precautions are not followed, even

embedded within a plastic package. Most instances of

erratic clocking or large accuracy errors can be traced to

the susceptibility of the oscillator circuit to interference

from adjacent high speed clock or data lines. Careful

layout of the RTC circuit will avoid noise pickup and

insure accurate clocking.

The input voltage range for V

BAT

is 1.8V to 5.5V, but

keep in mind the temperature compensation only

operates for V > 2.7V. Note that the device is not

BAT

guaranteed to operate with a V

should be changed before discharging to that level. It is

< 1.8V, so the battery

BAT

FN6668.7

June 4, 2010

26

ISL12022M

S

T

A

R

T

SIGNALS

FROM THE

MASTER

T

S

T

O

P

IDENTIFICATION

BYTE WITH

R/W = 0

IDENTIFICATION

A

C

K

A

C

K

A

BYTE WITH

ADDRESS

BYTE

R

R/W = 1

T

SIGNAL AT

SDA

1 1 0 1 1 1 1 0

1 1 0 1 1 1 1

1

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIRST READ

DATA BYTE

LAST READ

DATA BYTE

FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)

Figure 21 shows a suggested layout for the ISL12022M

device. The following main precautions should be

followed:

Measuring Oscillator Accuracy

The best way to analyze the ISL12022M frequency

accuracy is to set the IRQ/F

pin for a specific

OUT

• Do not run the serial bus lines or any high speed logic

lines in the vicinity of pins 1 and 20, or under the

package. These logic level lines can induce noise in

the oscillator circuit, causing misclocking.

frequency, and look at the output of that pin on a high

accuracy frequency counter (at least 7 digits accuracy).

Note that the IRQ/F

is an drain output and will

require a pull-up resistor.

OUT

Using the 1.0Hz output frequency is the most convenient

as the ppm error is expressed in Equation 6:

• Add a ground trace around the device with one end

terminated at the chip ground. This guard ring will

provide termination for emitted noise in the vicinity of

the RTC device

ppm error = F

– 1 • 1e6

(EQ. 6)

OUT

Other frequencies may be used for measurement but the

error calculation becomes more complex. Use the F

• Be sure to ground pins 6 and 15 as well as pin 8 as

these all insure the integrity of the device ground

OUT

output and a frequency counter for the most accurate

results. Also, when the proper layout guidelines above

are observed, the oscillator should start-up in most

circuits in less than one second.

• Add a 0.1µF decoupling capacitor at the device V

DD

pin, especially when using the 32.768kHz F

function.

OUT

Temperature Compensation Operation

The best way to run clock lines around the RTC is to stay

outside of the ground ring by at least a few millimeters.

The ISL12022M temperature compensation feature

needs to be enabled by the user. This must be done in a

specific order as follows.

1. Read register 0Dh, the BETA register. This register

contains the 5-bit BETA trimmed value, which is

automatically loaded on initial power-up. Mask off

the 5 LSB’s of the value just read.

Also, use the V

and V as guard ring lines as well,

BAT

DD

they can isolate clock lines from the oscillator section. In

addition, if the IRQ/F pin is used as a clock, it should

OUT

be routed away from the RTC device as well.

2. Bit 7 of the BETA register is the master enable

control for temperature sense operation. Set this to

“1” to allow continuous temperature frequency

correction. Frequency correction will then happen

GROUND

RING

every 60 seconds with V

applied.

DD

3. Bits 5 and 6 of the BETA register control

temperature compensation in battery backup mode

(see Table 15). Set the values for the operation

desired.

F

OUT

4. Write back to register 0Dh making sure not to

change the 5 LSB values, and include the desired

compensation control bits.

SCL

SDA

Note that every time the BETA register is written with the

TSE bit = 1, a temperature compensation cycle is

instigated and a new correction value will be loaded into

the FATR/FDTR registers (if the temperature changed

since the last conversion).

FIGURE 21. SUGGESTED LAYOUT FOR THE

ISL12022M

Also note that registers 0Bh and 0Ch, the ITR0 and

ALPHA registers, are READ-ONLY, and cannot be written

to. Also the value for BETA is locked and cannot be

changed with a write. However, It is still a good idea to

do the bit masking when doing TSE bit changes.

FN6668.7

June 4, 2010

27

ISL12022M

The Enable bit (DSTE) is in the Month forward register,

Daylight Savings Time (DST) Example

so the BCD value for that register is altered with the

additional bit. The Week and Day values along with

Week/Day vs Date select bit is in the Week/Day register,

so that value is also not straight BCD. Hour and Month

are normal BCD, but the Hour doesn’t use the MIL bit

since Military time PM values are already discretely

different from AM/PM time PM values. The DST reverse

setting utilizes the option to select the last week of the

month for October, which could have 4 or 5 weeks but

needs to have the time change on the last Sunday.

DST involves setting the forward and back times and

allowing the RTC device to automatically advance the

time or set the time back. This can be done for current

year, and future years. Many regions have DST rules that

use standard months, weeks and time of the day, which

permit a pre-programmed, permanent setting.

Table 26 shows an example setup for the ISL12022M.

TABLE 26. DST EXAMPLE

VARIABLE

VALUE

April

REGISTER VALUE

Note that the DSTADJ bit in the status register monitors

whether the DST forward adjustment has happened.

When it is “1”, DST forward has taken place. When it is

“0”, then either DST reverse has happened, or it has

been reset either by initial power-up or if the DSTE bit

has been set to “0”.

Month Forward and

DST Enable

15h

84h

Week and Day Forward 1st Week and 16h

and select Day/Week, Sunday

not Date

48h

Date Forward

Hour Forward

Month Reverse

not used

2am

17h

18h

19h

1Ah

00h

02h

10h

78h

October

Week and Day Reverse Last Week

and select Day/Week, and Sunday

not Date

Date Reverse

Hour Reverse

not used

2am

1Bh

1Ch

00h

02h

FN6668.7

June 4, 2010

28

ISL12022M

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to

web to make sure you have the latest Rev.

DATE

REVISION

CHANGE

5/27/10

FN6668.6

Added CDM to “ESD Rating” on page 5

Added “Related Literature*(see page 30)” on page 1

1/20/10

FN6668.6

Updated Note 2 in Ordering Information table from “These Intersil Pb-free plastic packaged

products employ special Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and

compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.” to “These Intersil plastic packaged products employ

special material sets, molding compounds and 100% matte tin plate plus anneal (e3)

termination finish. These products do contain Pb but they are RoHS compliant by exemption 7

(lead in high melt temp solder for internal connections) and exemption 5 (lead in piezoelectric

elements). These Intersil RoHS compliant products are compatible with both SnPb and Pb-free

soldering operations. These Intersil RoHS compliant products are MSL classified at Pb-free peak

reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.”

Changed "Pb-Free" on page 1 and page 3 under package to: "RoHS Compliant"

10/26/09

FN6668.6

Added "Default 32.768kHz frequency output" right behind

"Interrupt Output/Frequency Output" in IRQ/Fout pin description.

Added Typical Application Circuit to Page 1.

Converted to New Intersil Template

Updated ordering information by numbering all notes, setting up links, added MSL

(Moisture Sensitivity Level) note.

Updated word "Pinout" to "Pin Configuration".

Pin Descriptions updated by adding descriptive text taken from page 9. Deleted Text Pin

Descriptions that were on page 9.

Pb-free reflow link now shown in blue. Updated Notes in Electrical Spec Table to follow flow of

numbers when referenced.

Added "boldface limits..." text in Electrical Spec Conditions to indicate Min and Max over-temp.

Bolded all over-temp Min and Max values.

Added Revision History and Products information with links.

Added Table of Contents.

In Features (removed):

1. Real Time Clock (I believe the title say we are RTC and register

map tells the list the things we keep track of).

2. Customer Programmable Day Light Saving (Many people are using

SW based day light saving).

3. Combine Alarm and Fout to "Interrupt for Alarm or 15 selectable

Frequency Outputs".

4. Combine Battery and VDD monitor to "VDD and Battery Status Monitors".

5. Remove Oscillator Failure Detection.

6. Shorten Time stamp for battery to "Time Stamp for Battery Switch Over".

7. Remove all sub-bullets for each feature to save space

In Application (removed):

1. Medical Devices, Vending Machine, and Security System.

Under thermal information, added theta Jc value of 35C/W. As this is special package with

offset die, added note 5 to read "For θ , the “case temp” location is on top of the package and

JC

measured in the center of the package between pins 6 and 15."

FN6668.7

June 4, 2010

29

ISL12022M

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to

web to make sure you have the latest Rev. (Continued)

DATE

REVISION

CHANGE

07/22/09

FN6668.5

Corrected date from July 10, 2008 to July 10, 2009 and repost. No rev, no formal review

necessary per M Casino.

07/10/09

FN6668.5

Refer to following link for detailed list of changes:

http://intranet.intrepid.intersil.com/Windchill/wtcore/jsp/isil/ViewIsilPart.jsp?oid=VR%3Aext

.isil.part.mcol.MCOL%3A114266645

12/18/08

12/15/08

12/09/08

FN6668.4

FN6668.3

FN6668.2

Changed Storage Temperature on page 3 from:

"-65°C to +165°C" to "-40°C to +85°C"

Added spec to datasheet - Delta FoutI on page 3.

Added Tape and Reel Reference Note to Ordering Information.

Updated the following parameters in the spec table on page 3:

1. Changed Max for IDD1@5V from 6.5 to 7, and IDD1 @3V from 5.5 to 6.

2. Removed ÄATLSB (AT Sensitivity per LSB) from spec table.

11/03/08

FN6668.1

Complete overhaul of data sheet. Changed web destination to YES; ready for formal review in

support of POQ

Revised with final specs and text. Changes include:

Added text and equations for Ibat for temp sense ON, and for relative accuracy for 1m vs 10m

interval

Added text clarifying that no compensation at Vbat<2.7V

Revised entire Daylights savings time section

Added Application Example for DST

Added requirement for Vbat>1.8V in Vbat note.

Added apps circuit to survive Vbat<1.8V

Corrected All occurrences of Alpha tables

Corrected equations in NPPM section

BOLD and shade the COMPENSATON registers in the big table to indicate READ ONLY, add note

at top of table. Add READ ONLY statements to IATR, ALPHA, BETA, XT0, ALPHAH

Fixed blank bits in register tables and in text.

Register table: Change default values for compensation to xx's, they are different with each

device.

Added Datasheet curves

Add statement to Apps section on crystal handling similar to Maxim's

Updated Pb-free note according to lead finish (Order Info)

3/21/08

FN6668.1

**8/11 - Vaulted NO to the web. Datasheet being updated by Jim Pflasterer with additional

edits. This version is NOT a released version**

- Removed the "VDD" from the title on the first page. Updated File info and MCOL properties

page too.

- Global change for VBAT and VDD throughout document. Made the "BAT" and "DD" subscript.

- Included Battery Reseal Function in Features and Description on page 1

- Note 3 page 5, lower case "i" as in "inactive"

- Included symbol "Temp" for temp sensor accuracy in DC table on page 3

- First paragraph of DST Forward Registers had incorrect address stated (changed from 15h to

20h)

- Corrected register 20h on Page 20, added the DSTE bit to column 7

-EQ2, page 20, corrected to "NPPM = IPPM+ALPHA(T-XT0)2/4096"

02/29/08

FN6668.0

Initial Release with FN6668 making this a Rev 0.

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The

Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,

handheld products, and notebooks. Intersil's product families address power management and analog signal

processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device

information page on intersil.com: ISL12022M

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

FN6668.7

June 4, 2010

30

ISL12022M

Small Outline Plastic Packages (SOIC)

M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

N

INDEX

AREA

M

B

0.25(0.010)

H

INCHES MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.35

0.23

MAX

2.65

NOTES

-B-

A

A1

B

0.0926

0.0040

0.014

0.1043

0.0118

0.019

-

0.30

-

1

2

3

L

0.49

9

SEATING PLANE

A

C

D

E

0.0091

0.4961

0.2914

0.0125

0.32

-

-A-

0.5118 12.60

13.00

7.60

3

D

h x 45°

0.2992

7.40

4

-C-

e

0.050 BSC

1.27 BSC

-

α

H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

M

S

B

0.25(0.010) C A

N

α

20

7

0°

8°

0°

8°

-

NOTES:

Rev. 2 6/05

1. Symbols are defined in the “MO Series Symbol List” in

Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions

or gate burrs. Mold flash, protrusion and gate burrs shall

not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or

protrusions. Interlead flash and protrusions shall not

exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present,

a visual index feature must be located within the

crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or

greater above the seating plane, shall not exceed a

maximum value of 0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch

dimensions are not necessarily exact.

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications

at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6668.7

June 4, 2010

31


型号：	ISL12022MIBZ
厂家：	Intersil
描述：	Low Power RTC with Battery Backed SRAM,Integrated ±5ppm Temperature Compensation and Auto Daylight Saving 低功耗RTC，带有电池供电的SRAM ，集成± 5ppm的温度补偿和自动夏令电池外围集成电路温度补偿静态存储器光电二极管时钟
文件：	总31页 (文件大小：614K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL12022MIBZ [INTERSIL]

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