ISL12057IBZ [INTERSIL]
Low Cost and Low Power I2C RTC Real Time Clock/Calendar; 低成本和低功耗的I2C RTC实时时钟/日历
| 型号： | ISL12057IBZ |
| 厂家： | 
Intersil |
| 描述： | Low Cost and Low Power I2C RTC Real Time Clock/Calendar |
| 文件： | 总17页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL12057
®
2
Low Cost and Low Power I C RTC Real Time Clock/Calendar
Data Sheet
June 15, 2009
FN6755.0
Low Power and Low Cost RTC with Alarm
Function and Dual IRQ pins
Features
• Pin Compatible to Maxim DS1337
• Functionally Equivalent to Maxim DS1337
• Real Time Clock/Calendar
The ISL12057 device is a low power real time clock that is
pin compatible and functionally equivalent to Maxim DS1337
with clock/calendar and alarm function.
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Date, Month, and Year
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
• Dual Interrupts for Frequency Output and Alarm interrupts
• 4 Selectable Frequency Outputs
• 2 Alarms
- Settable to the Second, Minute, Hour, Day of the Week,
and Date
Pinouts
2
• I C Interface
ISL12057
(8 LD SOIC, MSOP)
TOP VIEW
- 400kHz Data Transfer Rate
• Small Package Options
- 8 Ld 2mmx2mm µTDFN
- 8 Ld MSOP
X1
X2
1
2
3
4
8
7
6
5
V
DD
IRQ1/F
SCL
OUT
- 8 Ld SOIC
IRQ2
GND
- Pb-Free (RoHS Compliant)
SDA
Applications
• Utility Meters
• HVAC Equipment
ISL12057
(8 LD µTDFN)
TOP VIEW
• Audio/Video Components
• Set-Top Box/Television
• Modems
X1
X2
V
1
2
3
4
8
7
6
5
DD
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
IRQ1/F
OUT
IRQ2
GND
SCL
SDA
• Point Of Sale Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL12057
Ordering Information
PART
NUMBER
PART
MARKING
V
RANGE
(V)
TEMP. RANGE
PACKAGE
(Pb-Free)
PKG.
DWG. #
DD
(°C)
ISL12057IBZ (Note 1)
12057 IBZ
1.4 to 3.6
1.4 to 3.6
1.4 to 3.6
1.4 to 3.6
1.4 to 3.6
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
8 Ld SOIC
M8.15
ISL12057IBZ-T* (Note 1) 12057 IBZ
ISL12057IUZ (Note 1) 12057
8 Ld SOIC (Tape and Reel)
8 Ld MSOP
M8.15
M8.118
M8.118
L8.2x2
ISL12057IUZ-T* (Note 1) 12057
ISL12057IRUZ-T* (Note 2) 057
8 Ld MSOP (Tape and Reel)
8 Ld µTDFN (Tape and Reel)
*Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
SDA
SECONDS
MINUTES
HOURS
SDA
SCL
BUFFER
2
I C
RTC
CONTROL
LOGIC
INTERFACE
SCL
BUFFER
DAY OF WEEK
DATE
X1
X2
CRYSTAL
OSCILLATOR
RTC
DIVIDER
MONTH
YEAR
V
DD
POR
FREQUENCY
OUT
ALARM1
ALARM2
CONTROL
REGISTERS
IRQ2
INTERNAL
SUPPLY
IRQ1/
F
OUT
FN6755.0
June 15, 2009
2
ISL12057
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
X1
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal. This pin can also be driven by an external 32.768kHz oscillator with X2 pin floating.
2
3
X2
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz
quartz crystal.
IRQ2
Interrupt Output 2 is a multi-functional pin that can be used as alarm interrupt. This pin is open drain and requires an
external pull-up resistor. This pin is at high impedance at power up.
4
5
GND
SDA
Ground
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output
and may be wire OR’ed with other open drain or open collector outputs.
6
7
SCL
The Serial Clock (SCL) input is used to clock all serial data into and out of the device.
IRQ1/F
Interrupt Output 1/Frequency Output is a multi-functional pin that can be used as alarm interrupt or frequency output
pin. The function is set via the configuration register. This pin is open drain and requires an external pull-up resistor. It
has a default output of 32.768kHz at power up.
OUT
8
V
Power supply
DD
FN6755.0
June 15, 2009
3
ISL12057
Absolute Maximum Ratings
Thermal Information
Voltage on V
DD
(respect to GND) . . . . . . . . . . . . . . . . . . -0.2V to 4V
Thermal Resistance (Typical)
θ
(°C/W)
JA
8 Lead SOIC (Note 3) . . . . . . . . . . . . . . . . . . . . . . .
8 Lead MSOP (Note 3). . . . . . . . . . . . . . . . . . . . . . .
8 Lead µTDFN (Note 3) . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
120
169
160
Voltage on IRQ1/F
OUT
, IRQ2, SCL and SDA
(respect to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 6V
Voltage on X1 and X2 Pins (respect to GND) . . . . . . . . . -0.2V to 4V
ESD Rating ((Per MIL-STD-883 Method 3014)
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>350V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
DC Operating Characteristics – RTC Temperature = -40°C to +85°C, unless otherwise stated.
MIN
TYP
MAX
SYMBOL
PARAMETER
Full Operation Power Supply
Timekeeping Power Supply
Standby Supply Current
CONDITIONS
(Note 6) (Note 5) (Note 6) UNITS NOTES
V
1.8
1.4
3.6
1.8
950
V
DD
V
V
DDT
I
I
I
V
V
V
V
V
= 3.6V
600
500
400
350
15
nA
nA
nA
nA
µA
4, 10
4, 10
4
DD1
DD
DD
DD
DD
DD
= 3.3V
= 1.8V
= 1.6V
= 3.6V
Timekeeping Current
650
40
DD2
DD3
2
Supply Current With I C Active at Clock
Speed of 400kHz
I
Input Leakage Current on SCL
I/O Leakage Current on SDA
-100
-100
100
100
nA
nA
LI
I
LO
IRQ1/F
OUT
and IRQ2
Output Low Voltage
V
V
= 1.8V, I = 3mA
OL
0.4
V
OL
DD
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6)
(Note 5)
(Note 6) UNITS NOTES
SERIAL INTERFACE SPECS
V
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x V
5.5
V
V
IL
DD
V
SDA and SCL Input Buffer HIGH
Voltage
0.7 x V
DD
IH
Hysteresis SDA and SCL Input Buffer
Hysteresis
0.04 x V
V
DD
V
Maximum Pull-up voltage on
SDA during I C communication
V
+ 2
V
9
PULLUP
DD
2
V
SDA Output Buffer LOW Voltage,
Sinking 3mA
V
> 1.8V, V = 5.0V
PULLUP
0
0.4
V
OL
DD
Cpin
SDA and SCL Pin Capacitance
T
= +25°C, f = 1MHz, V
DD
= 5V,
10
pF
7, 8
A
V
= 0V, V
= 0V
IN
OUT
f
SCL Frequency
400
50
kHz
ns
SCL
t
Pulse width Suppression Time at Any pulse narrower than the max spec
SDA and SCL Inputs is suppressed.
IN
t
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of V
,
DD
900
ns
9
AA
Data Valid
until SDA exits the 30% to 70% of V
window.
DD
FN6755.0
June 15, 2009
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ISL12057
Serial Interface Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6)
(Note 5)
(Note 6) UNITS NOTES
t
Time the Bus Must Be Free
Before the Start of a New
Transmission
SDA crossing 70% of V
STOP condition, to SDA crossing 70%
during a
1300
ns
BUF
DD
of V
during the following START
DD
condition
t
Clock LOW Time
Measured at the 30% of V
Measured at the 70% of V
crossing
crossing
1300
600
ns
ns
ns
LOW
DD
DD
t
Clock HIGH Time
HIGH
t
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of V
600
SU:STA
DD
From SDA falling edge crossing 30% of
to SCL falling edge crossing 70%
t
t
START Condition Hold Time
Input Data Setup Time
600
100
0
ns
ns
HD:STA
V
DD
of V
DD
From SDA exiting the 30% to 70% of
window, to SCL rising edge
SU:DAT
HD:DAT
SU:STO
HD:STO
V
DD
crossing 30% of V
DD
From SCL falling edge crossing 30% of
to SDA entering the 30% to 70%
t
Input Data Hold Time
900
ns
ns
V
DD
of V
window
DD
t
STOP Condition Setup Time
From SCL rising edge crossing 70% of
600
V
, to SDA rising edge crossing 30%
DD
DD
of V
t
STOP Condition Hold Time
Output Data Hold Time
From SDA rising edge to SCL falling
edge. Both crossing 70% of V
600
0
ns
ns
DD
From SCL falling edge crossing 30% of
, until SDA enters the 30% to 70%
t
DH
V
DD
of V
window
DD
t
SDA and SCL Rise Time
SDA and SCL Fall Time
From 30% to 70% of V
From 70% to 30% of V
20 + 0.1 x Cb
300
300
400
ns
ns
pF
kΩ
7, 8
7, 8, 9
7, 8
R
DD
DD
t
20 + 0.1 x Cb
F
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
1
Rpu
SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by t and t
For Cb = 400pF, max is about
7, 8
R
F
2kΩ to~2.5kΩ.
For Cb = 40pF, max is about 15kΩ to
~20kΩ
NOTES:
4. IRQ1/F
inactive.
OUT
5. Typical values are for T = +25°C and 3.3V supply voltage.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits should be considered typical and are not production tested.
2
8. These are I C specific parameters and are not production tested, however, they are used to set conditions for testing devices to validate
specification.
2
limit but the t and t in the I C parameters are not guaranteed.
9. Parts will work with SDA pull-up voltage above the V
10. Specified at +25°C.
PULLUP
AA
F
FN6755.0
June 15, 2009
5
ISL12057
SDA vs SCL Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
HD:DAT
t
SU:STA
SU:STO
t
HD:STA
SDA
(INPUT TIMING)
t
t
BUF
DH
t
AA
SDA
(OUTPUT TIMING)
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A
Center Line is
High Impedance
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V
5.0V
= 5V
DD
FOR V = 0.4V
OL
1533Ω
AND I
OL
= 3mA
SDA,
IRQ1/F
OUT
AND
100pF
IRQ2
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH V
= 5.0V
DD
FN6755.0
June 15, 2009
6
ISL12057
Typical Performance Curves Temperature is +25°C unless otherwise specified
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.8
0.6
0.4
0.2
3.6
3.0
1.8
1.4
1.4
1.9
2.4
2.9
3.4
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
V
(V)
DD
FIGURE 2. I
DD1
vs V
DD
FIGURE 3. I
vs TEMPERATURE
DD1
32769.0
32768.8
32768.6
32768.4
32768.2
32768.0
32767.8
32767.6
32767.4
32767.2
32767.0
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
32768Hz
8192Hz
4096Hz
1Hz
1.4
1.9
2.4
V
2.9
3.4
1.4
1.9
2.4
V
2.9
3.4
(V)
(V)
DD
DD
FIGURE 4. I
DD
vs V
vs F
DD OUT
FIGURE 5. F
VS V
WITH A TYPICAL 32.768kHZ CRYSTAL
DD
OUT
General Description
Pin Description
The ISL12057 device is a low power real time clock with
clock/calendar, power fail indicator, and alarm function.
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal
is used with the ISL12057 to supply a timebase for the real
time clock. Refer to Figure 6.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The device can also be driven directly from a 32.768kHz
square wave source with peak-to-peak voltage from 0V to
VDD at X1 pin with X2 pin floating.
The ISL12057 has two flexible alarms; each can be set to any
clock/calendar value for a match. For example, every minute,
every Tuesday or at 5:23 AM on 1st day of a month. The alarm
status is available by checking the Status Register, or the
device can be configured to provide a hardware interrupt via the
X1
X2
IRQ1/F
or IRQ2 pin. There is a repeat mode for the alarm
OUT
allowing a periodic interrupt every second or every minute.
FIGURE 6. RECOMMENDED CRYSTAL CONNECTION
FN6755.0
June 15, 2009
7
ISL12057
corrects for months having fewer than 31 days and has a bit
that controls 24-hour or AM/PM format. The clock will begin
incrementing after power-up with valid oscillator condition.
IRQ1/F
(Interrupt Output 1/Frequency Output)
OUT
This dual function pin can be used as an alarm interrupt or
frequency output pin. The IRQ1/F mode is selected via
OUT
the control register (address 0Eh). The IRQ1/F
open drain output.
is an
OUT
ACCURACY OF THE REAL TIME CLOCK
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time base
for the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of
the crystal is a function of the turnover temperature of the
crystal from the crystal’s nominal frequency. For example, a
~20ppm frequency deviation translates into an accuracy of
~1 minute per month. These parameters are available from
the crystal manufacturer.
This pin has a default output of 32.768kHz at power-up.
• Interrupt Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that an alarm
has occurred and requests action.
• Frequency Output Mode. The pin outputs a clock signal
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I C bus.
2
IRQ2 (Interrupt Output 2)
2
The IRQ2 pin is used as an Alarm1 interrupt or/and Alarm2
interrupt. The IRQ2 mode is selected via the control register
(address 0Eh). The IRQ2 is an open drain output.
I C Serial Interface
2
The ISL12057 has an I C serial bus interface that provides
access to the real time clock registers, control and status
registers and the alarm registers. The I C serial interface is
compatible with other industry I C serial bus protocols using
2
This pin is high impedance at power-up.
2
The pin provides an interrupt signal output. This signal
notifies a host processor that an alarm has occurred and
requests action.
a bidirectional data signal (SDA) and a clock signal (SCL).
Register Descriptions
The registers are accessible following a slave byte of
“1101000x” and reads or writes to addresses [00h:0Fh]. The
defined addresses and default values are described in
Table 1.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of the
device. The input buffer on this pin is always active (not gated).
The SCL pin can accept a logic high voltage up to 5.5V.
REGISTER ACCESS
Serial Data (SDA)
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address. The address will wrap around from 0Fh to 00h.
SDA is a bi-directional pin used to transfer data into and out
of the device. It has an open drain output and may be ORed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
The registers are divided into 3 sections. These are:
An open drain output requires the use of a pull-up resistor,
and it can accept a pull-up voltage up to 5.5V. The output
circuitry controls the fall time of the output signal with the use
of a slope controlled pull-down. The circuit is designed for
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Alarm (7 bytes): Address 07h to 0Dh.
3. Control and Status (2 bytes): Address 0Eh to 0Fh.
There are no addresses above 0Fh.
2
400kHz I C interface speeds.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC registers, the read instruction
latches all clock registers into a buffer, so an update of the
clock does not change the time being read. A sequential
read will not result in the output of data from the memory
array. At the end of a read, the master supplies a stop
condition to end the operation and free the bus. After a read
or write instruction, the address remains at the previous
address +1 so the user can execute a current address read
and continue reading the next register.
NOTE: Parts will work with SDA pull-up voltage above the V
PULLUP
2
limit but the t and t in the I C parameters are not guaranteed.
AA
F
V
, GND
DD
Chip power supply and ground pins. The device will have full
operation with a power supply from 1.8V to 3.6VDC, and
timekeeping function with a power supply from 1.4V to 1.8V.
A 0.1µF decoupling capacitor is recommended on the V
pin to ground.
DD
Functional Description
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation
of second, minute, hour, day of week, date, month, and year.
The RTC also has leap-year correction. The RTC also
FN6755.0
June 15, 2009
8
ISL12057
TABLE 1. REGISTER MEMORY MAP
BIT
REG
REG
ADDR SECTION NAME
7
0
0
0
6
5
4
3
2
1
0
RANGE DEFAULT
00H
01H
02H
RTC
SC
MN
HR
SC22
MN22
MIL
SC21
MN21
AM/PM
SC20
MN20
HR20
SC13
MN13
HR13
SC12
MN12
HR12
SC11
MN11
HR11
SC10
MN10
HR10
0-59
0-59
00h
00h
00h
1-12
+AM/PM
HR21
0
0-23
1-7
03H
04H
05H
DW
DT
0
0
0
0
0
0
0
DW12
DT12
MO12
DW11
DT11
MO11
DW10
DT10
MO10
01h
01h
01h
DT21
0
DT20
MO20
DT13
MO13
1-31
MO
CENTUR
Y
0-12
+Century
06h
07h
08h
09h
YR
YR23
A1M1
A1M2
A1M3
YR22
A1SC22
A1MN22
A1MIL
YR21
YR20
YR13
YR12
YR11
YR10
0-99
0-59
0-59
00h
00h
00h
00h
Alarm1
A1SC
A1MN
A1HR
A1SC21
A1SC20 A1SC13 A1SC12 A1SC11 A1SC10
A1MN21 A1MN20 A1MN13 A1MN12 A1MN11 A1MN10
A1AM/PM A1HR20 A1HR13 A1HR12 A1HR11 A1HR10
1-12
+AM/PM
A1HR21
0-23
1-7
0Ah
A1DW/
DT
A1M4
A1DW/DT
0
0
0
A1DW12 A1DW11 A1DW10
00h
00h
00h
00h
A1DT21
A1DT20 A1DT13 A1DT12 A1DT11 A1DT10
1-31
0-59
0Bh
0Ch
Alarm2
A2MN
A2HR
A2M2
A2M3
A2MN22
A2MIL
A2MN21 A2MN20 A2MN13 A2MN12 A2MN11 A2MN10
A2AM/PM A2HR20 A2HR13 A2HR12 A2HR11 A2HR10
1-12
+AM/PM
A2HR21
0-23
1-7
0Dh
A2DW/
DT
A2M4
A2DW/DT
0
0
0
A2DW12 A2DW11 A2DW10
00h
00h
18h
80h
A2DT21
A2DT20 A2DT13 A2DT12 A2DT11 A2DT10
1-31
N/A
N/A
0Eh
0Fh
Control
Status
INT
SR
EOSC
OSF
0
0
0
0
RS2
0
RS1
0
INTCN
0
A2IE
A2F
A1IE
A1F
bit with logic high being PM. The clock defaults to 24-hour
format time.
Real Time Clock Registers
Addresses [00h to 06h]
CENTURY INDICATOR
RTC REGISTERS (SC, MN, HR, DW, DT, MO, YR)
The century bit (bit 7 of the MO register) is toggled when the
years register overflows from 99 to 00 to indicator the
change of century.
These registers depict BCD representations of the time. As
such, SC (Seconds, address 00h) and MN (Minutes,
address 01h) range from 0 to 59, HR (Hour, address 02h)
can either be a 12-hour or 24-hour mode, DW (Day of the
Week, address 03h) is 1 to 7, DT (Date, address 04h) is 1 to
31, MO (Month, address 05h) is 1 to 12, and YR (Year,
address 06h) is 0 to 99.
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year, the year 2100 is not. The
The DW register provides a Day of the Week status and uses
3 bits DW2 to DW0 to represent the seven days of the week.
The counter advances in the cycle 1-2-3-4-5-6-7-1-2-…
The assignment of a numerical value to a specific day of the
week is arbitrary and may be decided by the system
software designer.
ISL12057 does not correct for the leap year in the year 2100.
Addresses [0Eh to 0Fh]
The Control and Status Registers consist of the Status
Register, Interrupt and Alarm Register.
24-HOUR TIME
If the MIL bit of the HR register is “0”, the RTC uses a
24-hour format and bit 5 of the HR register is the second
10-hour bit (20–23 hours). If the MIL bit is “1”, the RTC uses
a 12-hour format and bit 5 of the HR register is the AM/PM
FN6755.0
June 15, 2009
9
ISL12057
Interrupt Control Register (INT) [Address 0Eh]
Status Register (SR) [Address 0Fh]
The Status Register is located in the memory map at
address 0Fh. This is a volatile register that provides status of
oscillator failure and alarm interrupts.
TABLE 2. INTERRUPT CONTROL REGISTER (INT)
ADDR
0Eh EOSC
Default
7
6
0
0
5
0
0
4
RS2
1
3
2
1
0
A1IE
0
RS1 INTCN A2IE
TABLE 5. STATUS REGISTER (SR)
0
1
0
0
ADDR
0Fh OSF
Default
7
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
A2F A1F
OSCILLATOR ENABLE BIT (EOSC)
The EOSC bit enables the crystal oscillator function when it
is set to “0”. When the EOSC bit is set to “1”, the crystal
oscillator function is disable and the device enters into power
saving mode. The EOSC bit is set to “0” at power-up.
1
0
0
ALARM1 INTERRUPT BIT (A1F)
These bits announce if the Alarm1 matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit is manually reset to “0” by the user. A write to this bit in
the SR can only set it to “0”, not “1”.
FREQUENCY OUT CONTROL BITS (RS2, RS1)
These bits select the output frequency at the IRQ1/F
OUT
pin. INTCN must be set to “0” for frequency output at the
IRQ1/F
pin. Please see Table 3 for Frequency Selection
pin.
ALARM2 INTERRUPT BIT (A2F)
OUT
of the F
OUT
These bits announce if the Alarm2 matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit is manually reset to “0” by the user. A write to this bit in
the SR can only set it to “0”, not “1”.
TABLE 3. FREQUENCY SELECTION OF F
OUT
PIN
FREQUENCY
(Hz)
F
RS2
RS1
COMMENT
OUT
OSCILLATOR FAILURE BIT (OSF)
32768
8192
4096
1
1
1
0
0
1
0
1
0
Free running crystal clock
Free running crystal clock
Free running crystal clock
Sync at RTC write
This bit is set to a “1” when there is no oscillation on X1 pin.
This is set by hardware (ISL12057 internally), and can only
be disabled by having an oscillation on X1 and and manually
reset to “0” to reset it..
Alarm1 Registers
INTERRUPT CONTROL BIT (INTCN) AND ALARM
INTERRUPT ENABLE BITS (A2IE, A1IE)
Addresses [Address 07h to 0Ah]
The INTCN bit controls the relationship between the alarm
The Alarm1 register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “0”). These enable bits specify which
alarm registers (seconds, minutes, etc) are used to make the
comparison. When all the enable bits are set to “1”, the
Alarm1 will trigger once per second. Note that there is no
alarm byte for month and year.
interrupts and the IRQ1/F
and IRQ2 pins. The A2IE and
OUT
A1IE bits enable the alarm interrupts, A2F and A1F, to assert
the IRQ1/F and IRQ2 pins. Please see Table 4 for Alarm
OUT
Interrupt Selection with INTCN, A2IE and A1IE bits.
TABLE 4. ALARM INTERRUPT SELECTION WITH INTCN,
A2IE AND A1IE BITS
The Alarm1 function works as a comparison between the
Alarm1 registers and the RTC registers. As the RTC
advances, the Alarm1 will be triggered once a match occurs
between the Alarm1 registers and the RTC registers. Any
one Alarm1 register, multiple registers, or all registers can be
enabled for a match.
INTCN
A2IE
A1IE
IRQ1/F
OUT
IRQ2
HIGH
A1F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
F
F
F
F
OUT
OUT
OUT
OUT
A2F
A1F or A2F
HIGH
A1F
To clear an Alarm1, the A1F status bit must be set to “0” with
a write.
HIGH
HIGH
A2F
TABLE 6. ALARM1 INTERRUPT WITH ENABLE BITS
SELECTION
HIGH
A1F
A2F
A1DW/DT A1M1 A1M2 A1M3 A1M4 ALARM1 INTERRUPT
X
X
X
1
0
1
1
1
0
1
1
1
1
1
1
Every Second
Match Second
Match Minute
FN6755.0
June 15, 2009
10
ISL12057
TABLE 6. ALARM1 INTERRUPT WITH ENABLE BITS
SELECTION (Continued)
make the comparison. When all the enable bits are set to “1”,
the Alarm2 will trigger once per minute. Note that there are
no alarm bytes for second, month and year.
A1DW/DT A1M1 A1M2 A1M3 A1M4 ALARM1 INTERRUPT
X
0
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
0
Match Hour
Match Date
The Alarm2 function works as a comparison between the
Alarm2 registers and the RTC registers. As the RTC
advances, the Alarm2 will be triggered once a match occurs
between the Alarm2 registers and the RTC registers. Any
one Alarm2 register, multiple registers, or all registers can be
enabled for a match.
Match Day
Match Second and Minute
Match Second and Hour
To clear an Alarm2, the A2F status bit must be set to “0” with
a write.
Match Second, Minute
and Hour
.
.
.
.
.
.
.
.
.
.
.
.
TABLE 7. ALARM2 INTERRUPT WITH ENABLE BITS
SELECTION
0
1
0
0
0
Match Minute Hour and
Date
A2DW/DT A2M2 A2M3 A2M4
ALARM2 INTERRUPT
Every Minute (Second=00)
Match Minute
X
X
X
0
1
X
0
0
0
1
1
1
1
0
1
1
1
0
1
0
0
0
1
0
1
1
0
1
1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Match Second, Minute
Hour and Date
Match Hour
.
.
.
.
.
.
.
.
.
.
.
.
Match Date
1
1
0
0
0
Match Minute, Hour, and
Day
Match Day
Match Minute and Hour
Match Hour and Date
Match Minute and Date
Match Minute, Hour, and Date
Match Minute and Day
Match Hour and Day
Match Minute, Hour, and Day
1
0
0
0
0
Match Second, Minute,
Hour, and Day
Note: X is don’t care, it can be set to 0 or 1.
Following is example of Alarm1 Interrupt.
Example – A single alarm will occur on Monday at 11:30am
(Monday is when DW = 2).
A. Set Alarm1 registers as follows:
BIT
ALARM1
REGISTER 7
Note: X is don’t care, it can be set to 0 or 1.
Following is example of Alarm2 Interrupt.
6
0
0
5
0
1
4
0
1
3
0
0
2
0
0
1
0
0
0
0
0
HEX
DESCRIPTION
A1SC
A1MN
1
0
80h Seconds disabled
Example – A single alarm will occur on every 1st day of the
month at 20:00 military time.
30h Minutes set to 30,
enabled
A1HR
0
0
1
1
0
0
1
0
0
0
0
0
0
1
1
0
51h Hours set to 11am,
enabled
A. Set Alarm registers as follows:
BIT
ALARM2
A1DW/DT
42h Day set to 1,
enabled
REGISTER 7
6
0
0
5
0
1
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
HEX
DESCRIPTION
A2MN
A2HR
1
0
80h Minutes disabled
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the A1F bit in the
status register to “1”.
20h Hours set to 20,
enabled
A2DW/DT
0
0
0
0
0
0
0
1
01h Date set to 1st,
enabled
Alarm2 Registers
After these registers are set, an alarm will be generated when
the RTC advances to exactly 20:00 on Monday (after minutes
changes from 59 to 00) by setting the A2F bit in the status
register to “1”.
Addresses [Address 12h to 14h]
The Alarm2 register bytes are set up identical to the RTC
register bytes except that the MSB of each byte functions as
an enable bit (enable = “0”). These enable bits specify which
alarm registers (minutes, hour, and date/day) are used to
FN6755.0
June 15, 2009
11
ISL12057
2
Figure 7). A START condition is ignored during the power-up
sequence.
I C Serial Interface
The ISL12057 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12057 operates as a slave device in all applications.
2
All I C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 7). A STOP condition at the end of
a read operation or at the end of a write operation to memory
only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting 8 bits. During the ninth clock cycle, the receiver
pulls the SDA line LOW to acknowledge the reception of the
8 bits of data (see Figure 8).
2
All communication over the I C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 7). On power-up of the ISL12057, the SDA pin is in
the input mode.
The ISL12057 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12057 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
2
All I C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL12057 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
SCL
SDA
DATA
STABLE
DATA
CHANGE STABLE
DATA
START
STOP
FIGURE 7. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN6755.0
June 15, 2009
12
ISL12057
WRITE
SIGNALS FROM
THE MASTER
S
T
A
R
T
S
T
O
P
LAST DATA
BYTE
IDENTIFICATION
ADDRESS
BYTE
FIRST DATA
BYTE
BYTE
SIGNAL AT SDA
1 1 0 1 0 0 0 0
0 0 0 0
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE ISL12057
A
C
K
A
C
K
FIGURE 9. SEQUENTIAL BYTE WRITE SEQUENCE
Device Addressing
Write Operation
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifier. These
bits are “1101000”. Slave bits “1101” access the register.
Slave bits “000” specify the device select bits.
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
2
ISL12057 responds with an ACK. At this time, the I C
interface enters a standby state.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
read operation is selected. A “0” selects a write operation
(refer to Figure 10).
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 11). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL12057 responds with an ACK. Then
the ISL12057 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (see Figure 11).
After loading the entire Slave Address Byte from the SDA
bus, the ISL12057 compares the device identifier and device
select bits with “1101000”. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up, the internal
address counter is set to address 0h, so a current address
read of the RTC array starts at address 0h. When required,
as part of a random read, the master must supply the 1 Word
Address Bytes as shown in Figure 11.
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer’s initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 13h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. For a random read of the Clock/Control Registers,
the slave byte must be “1101000x” in both places.
SLAVE
ADDRESS BYTE
0
0
0
R/W
1
1
0
1
WORD ADDRESS
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
DATA BYTE
FIGURE 10. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
FN6755.0
June 15, 2009
13
ISL12057
Application Section
S
T
A
R
S
SIGNALS
FROM THE
MASTER
S
T
O
P
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
IDENTIFICATION
BYTE WITH
A
C
K
A
C
K
ADDRESS
BYTE
R/W = 1
T
SIGNAL AT
SDA
1 1 0 1 0 0 0 0
1 1 0 1 0 0 0
1
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 11. READ SEQUENCE
2. Add a ground trace around the crystal with one end
terminated at the chip ground. This will provide
Oscillator Crystal Requirements
The ISL12057 uses a standard 32.768kHz crystal. Either
through hole or surface mount crystals can be used. Table 8
lists some recommended surface mount crystals and the
parameters of each. This list is not exhaustive and other
surface mount devices can be used with the ISL12057 if
their specifications are very similar to the devices listed.
The crystal should have a required parallel load capacitance
of 6pF and an equivalent series resistance of less than 50k.
The crystal’s temperature range specification should match
the application. Many crystals are rated for -10°C to +60°C
(especially through-hole and tuning fork types), so an
appropriate crystal should be selected if extended
temperature range is required.
termination for emitted noise in the vicinity of the RTC
device.
FIGURE 12. SUGGESTED LAYOUT FOR ISL12057 AND
CRYSTAL
TABLE 8. SUGGESTED SURFACE MOUNT CRYSTALS
In addition, it is a good idea to avoid a ground plane under
the X1 and X2 pins and the crystal, as this will affect the load
capacitance and therefore the oscillator accuracy of the
MANUFACTURER
Citizen
PART NUMBER
CM200S
circuit. If the IRQ1/F
pin is used as a clock, it should be
OUT
routed away from the RTC device as well. The trace for the
pins can be treated as a ground, and should be routed
MicroCrystal
ECS
MS3V
ECX-306
V
CC
around the crystal.
Layout Considerations
The crystal input at X1 has a very high impedance, and
oscillator circuits operating at low frequencies (such as
32.768kHz) are known to pick up noise very easily if layout
precautions are not followed. Most instances of erratic clocking
or large accuracy errors can be traced to the susceptibility of
the oscillator circuit to interference from adjacent high speed
clock or data lines. Careful layout of the RTC circuit will avoid
noise pickup and insure accurate clocking.
Figure 12 shows a suggested layout for the ISL12057 device
using a surface mount crystal. Two main precautions should
be followed:
1. Do not run the serial bus lines or any high speed logic
lines in the vicinity of the crystal. These logic level lines
can induce noise in the oscillator circuit to cause
misclocking.
FN6755.0
June 15, 2009
14
ISL12057
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
FN6755.0
June 15, 2009
15
ISL12057
Package Outline Drawing
L8.2x2
8 Lead Ultra Thin Dual Flat No-Lead COL Plastic Package (UTDFN COL)
Rev 3, 11/07
2X
1.5
2.00
A
PIN #1 INDEX AREA
6
6
6X 0.50
PIN 1
INDEX AREA
B
1
4
7X 0.4 ± 0.1
1X 0.5 ±0.1
2.00
(4X)
0.15
8
5
0.10 M C A B
0.25 +0.05 / -0.07
TOP VIEW
4
BOTTOM VIEW
( 8X 0 . 25 )
SEE DETAIL "X"
( 1X 0 .70 )
0 . 55 MAX
C
0.10
BASE PLANE
SEATING PLANE
C
0.08
C
( 1 . 8 )
SIDE VIEW
0 . 2 REF
C
( 7X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
( 6X 0 . 5 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6755.0
June 15, 2009
16
ISL12057
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6755.0
June 15, 2009
17
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